30679 Commits

Author SHA1 Message Date
Michael Kuperstein
501cad951b [X86] Add FXSR intrinsics
Add intrinsics for the FXSR instructions (FXSAVE/FXSAVE64/FXRSTOR/FXRSTOR64)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241049 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 08:49:35 +00:00
Adrian Prantl
85cd16c88e Debug info: Add dwarf backend support for DIModule.
rdar://problem/20965932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241034 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 02:13:04 +00:00
Matthias Braun
1a5b04c725 RegisterCoalescer: Cleanup empty subranges after shrinkToUses()
A call to removeEmptySubranges() is necessary after every operation that
potentially removes all segments from a subregister range; this case in
the register coalescer was missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 00:33:44 +00:00
Adrian Prantl
717764717b Add a DIModule metadata node to the IR.
It is meant to be used to record modules @imported by the current
compile unit, so a debugger an import the same modules to replicate this
environment before dropping into the expression evaluator.

DIModule is a sibling to DINamespace and behaves quite similarly.
In addition to the name of the module it also records the module
configuration details that are necessary to uniquely identify the module.
This includes the configuration macros (e.g., -DNDEBUG), the include path
where the module.map file is to be found, and the isysroot.

The idea is that the backend will turn this into a DW_TAG_module.

http://reviews.llvm.org/D9614
rdar://problem/20965932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241017 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 23:03:47 +00:00
Peter Collingbourne
a6367d9136 Teach LTOModule to emit linker flags for dllexported symbols, plus interface cleanup.
This change unifies how LTOModule and the backend obtain linker flags
for globals: via a new TargetLoweringObjectFile member function named
emitLinkerFlagsForGlobal. A new function LTOModule::getLinkerOpts() returns
the list of linker flags as a single concatenated string.

This change affects the C libLTO API: the function lto_module_get_*deplibs now
exposes an empty list, and lto_module_get_*linkeropts exposes a single element
which combines the contents of all observed flags. libLTO should never have
tried to parse the linker flags; it is the linker's job to do so. Because
linkers will need to be able to parse flags in regular object files, it
makes little sense for libLTO to have a redundant mechanism for doing so.

The new API is compatible with the old one. It is valid for a user to specify
multiple linker flags in a single pragma directive like this:

 #pragma comment(linker, "/defaultlib:foo /defaultlib:bar")

The previous implementation would not have exposed
either flag via lto_module_get_*deplibs (as the test in
TargetLoweringObjectFileCOFF::getDepLibFromLinkerOpt was case sensitive)
and would have exposed "/defaultlib:foo /defaultlib:bar" as a single flag via
lto_module_get_*linkeropts. This may have been a bug in the implementation,
but it does give us a chance to fix the interface.

Differential Revision: http://reviews.llvm.org/D10548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 22:04:09 +00:00
Tim Northover
9cbdfb5c05 ARM: add correct kill flags when combining stm instructions
When the store sequence being combined actually stores the base register, we
should not mark it as killed until the end.

rdar://21504262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:42:16 +00:00
Matthias Braun
7839b00d43 X86: Rework inline asm integer register specification.
This is a new version of http://reviews.llvm.org/D10260.

It turned out that when you specify an integer register in inline asm on
x86 you get the register of the required type size back. That means that
X86TargetLowering::getRegForInlineAsmConstraint() has to accept any of
the integer registers and adapt its size to the given target size which
may be any 8/16/32/64 bit sized type. Surprisingly that means given a
constraint of "{ax}" and a type of MVT::F32 we need to return X86::EAX.

This change makes this face explicit, the previous code seemed like
working by accident because there it never returned an error once a
register was found. On the other hand this rewrite allows to actually
return errors for invalid situations like requesting an integer register
for an i128 type.

Related to rdar://21042280

Differential Revision: http://reviews.llvm.org/D10813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241002 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:35:51 +00:00
Alexey Samsonov
93dd711033 [LoopSimplify] Set proper debug location in loop backedge blocks.
Set debug location for terminator instruction in loop backedge block
(which is an unconditional jump to loop header). We can't copy debug
location from original backedges, as there can be several of them,
with different debug info locations. So, we follow the approach of
SplitBlockPredecessors, and copy the debug info from first non-PHI
instruction in the header (i.e. destination block).

This is yet another change for PR23837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:30:14 +00:00
Sanjoy Das
35f25f9d7e [FaultMaps] Fix test case.
implicit-null-check-negative.ll had a missing 2>&1.  Fix this, and
remove an incorrect test case that this exposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240998 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:27:36 +00:00
Pawel Bylica
4c81aa2602 [DAGCombiner] Fix & simplify constant folding of sext/zext.
Summary: This patch fixes the cases of sext/zext constant folding in DAG combiner where constans do not fit 64 bits. The fix simply removes un$

Test Plan: New regression test included.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240991 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 20:28:47 +00:00
Alex Lorenz
1a4def3d97 MIR Serialization: Serialize the register mask machine operands.
This commit implements serialization of the register mask machine
operands. This commit serializes only the call preserved register
masks that are defined by a target, it doesn't serialize arbitrary
register masks.

This commit also extends the TargetRegisterInfo class and TableGen so that
the users of TRI can get the list of all the call preserved register masks and
their names.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10673


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240966 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 16:57:06 +00:00
Rafael Espindola
9a6c902332 Factor out the checking of string tables.
This moves the error checking for string tables to getStringTable which returns
an ErrorOr<StringRef>.

This improves error checking, makes it uniform across all string tables and
makes it possible to check them once instead of once per name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240950 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 14:39:25 +00:00
Rafael Espindola
528a204ab9 Add a testcase for an invalid file.
We were already checking this, but had no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240945 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 14:12:14 +00:00
Rafael Espindola
db89b93b44 Convert an assert that can fail into error checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240944 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 14:02:24 +00:00
Elena Demikhovsky
546178bfe5 AVX-512: all forms of SCATTER instruction on SKX,
encoding, intrinsics and tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240936 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 12:14:24 +00:00
Javed Absar
263dd533ee [ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.

Reviewers: rengolin, ranjeet.singh

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:32:29 +00:00
Igor Breger
048a1eb977 AVX-512: Implemented missing encoding and intrinsics for FMA instructions
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:10:00 +00:00
Matt Arsenault
8be74e16ef AMDGPU/SI: Fix extra space when printing v_div_fmas_*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 18:16:14 +00:00
Jingyue Wu
62bdd72542 [SLSR] S's basis must have the same type as S
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240910 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 17:45:05 +00:00
Asaf Badouh
13ce163855 [x86][AVX512]
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240906 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 14:30:39 +00:00
Elena Demikhovsky
b23b2fbd3a AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240905 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 10:53:29 +00:00
Adrian Prantl
1e7ecc8e57 Revert "Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed"
This reverts commit 240890. Breaking the gdb buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240893 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 21:55:00 +00:00
Benjamin Kramer
0bd9021d62 Don't use %llc_dwarf for target-specific tests.
Should fix running them on windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240892 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 21:11:43 +00:00
Benjamin Kramer
45b5f7e457 [SDAG] Now that we have a way to communicate the exact bit on sdiv use it to simplify sdiv by a constant.
We had a hack in SDAGBuilder in place to work around this but now we
can avoid that. Call BuildExactSDIV from BuildSDIV so DAGCombiner can
perform this trick automatically.

The added check in DAGCombiner is necessary to prevent exact sdiv by pow2
from regressing as the target-specific pow2 lowering is not aware of
exact bits yet.

This is mostly covered by existing tests. One side effect is that we
get the better lowering for exact vector sdivs now too :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 20:33:26 +00:00
Adrian Prantl
6b2ae13ea3 Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed
the DW_AT_bit_offset computation, the byte offset is in fact also
endian-dependent as it needs to point to the storage unit containing the
most-significant bit of the the bitfield.
I'm so looking forward to emitting the endian-agnostic DWARF 3 version
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240890 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 20:12:43 +00:00
Daniel Sanders
85f44d3917 [mips] Fold duplicate big-endian disassembler tests together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240887 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 17:56:44 +00:00
Daniel Sanders
279a7405e5 [mips] Sort big-endian disassembler tests by opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240885 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 16:13:59 +00:00
Daniel Sanders
44f5fc765f [mips] Make little-endian disassembler test filenames consistent.
Most are named *-el.txt. Renamed the three that were *-le.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 15:42:25 +00:00
Daniel Sanders
817cbdeae6 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 15:39:19 +00:00
David Majnemer
8a8d8b3e59 [LoopVectorize] Pointer indicies may be wider than the pointer
If we are dealing with a pointer induction variable, isInductionPHI
gives back a step value of Stride / size of pointer.  However, we might
be indexing with a legal type wider than the pointer width.
Handle this by inserting casts where appropriate instead of crashing.

This fixes PR23954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 08:38:17 +00:00
David Majnemer
1166ce2460 [PruneEH] A naked, noinline function can return via InlineAsm
The PruneEH pass tries to annotate functions as 'noreturn' if it doesn't
see a ReturnInst.  However, a naked function containing inline assembly
can contain control flow leaving the function.

This fixes PR23971.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 07:52:53 +00:00
Lang Hames
dee1d964f2 [Stackmap] Pre-assemble the stackmap parser test case. (Fix builders).
This case had been failing on testers that didn't have x86 support. Rather
than XFAIL it on testers without x86 support, I've just assembled it and used
the raw object as the test input.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240875 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 03:49:25 +00:00
NAKAMURA Takumi
9160c024b9 llvm/test/CodeGen/X86/xor.ll: Appease Win32 targets since r240796.
%struct.ref_s = type { %union.v, i16, i16 }
  %union.v = type { i64 }

It seems %struct.ref_s is incompatible in tail padding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240874 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 03:46:58 +00:00
Petr Hosek
bc245c01bf [MC] Ensure that pending labels are flushed when -mc-relax-all flag is used
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240870 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:54:17 +00:00
Petr Hosek
0aaf3287e3 [MC] Align fragments when -mc-relax-all flag is used
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:49:53 +00:00
Peter Collingbourne
e92934e078 LowerBitSets: Ignore bitset entries that do not directly refer to a global.
It is possible for a global to be substituted with another global of a
different type or a different kind (i.e. an alias) at IR link time. One
example of this scenario is when a Microsoft ABI vtable is substituted with
an alias referring to a larger vtable containing an RTTI reference.

This will cause the global to be RAUW'd with a possibly bitcasted reference
to the other global. This will of course also affect any references to the
global in bitset metadata.

The right way to handle such metadata is simply to ignore it. This is sound
because the linked module should contain another copy of the bitset entries as
applied to the new global.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 00:17:51 +00:00
Adrian Prantl
50a38dc049 Add original source code to test case as suggested in review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240863 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 00:01:33 +00:00
Lang Hames
63f4054f8e [StackMaps] Add a lightweight parser for stackmap version 1 sections.
The parser provides a convenient interface for reading llvm stackmap v1 sections
in object files.

This patch also includes a new option for llvm-readobj, '-stackmap', which uses
the parser to pretty-print stackmap sections for debugging/testing purposes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240860 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 23:56:53 +00:00
Adrian Prantl
60bd365f59 Debug Info: Fix a bug in the DW_AT_bit_offset calculation that would
result in negative offsets and attempt a better job at documenting
the algorithm.

rdar://21082998

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240853 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 23:31:27 +00:00
Alex Lorenz
d986612a1a MIR Serialization: Serialize global address machine operands.
This commit serializes the global address machine operands.
This commit doesn't serialize the operand's offset and target
flags, it serializes only the global value reference.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10671


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:56:48 +00:00
Philip Reames
60d74b7101 [RewriteStatepointsForGC] Generalized vector phi/select handling for base pointers
This change extends the detection of base pointers for vector constructs to handle arbitrary phi and select nodes. The existing non-vector code already handles those, so this is basically just extending the vector special case to be less special cased. It still isn't generalized vector handling since we can't handle arbitrary vector instructions (e.g. shufflevectors), but it's a lot closer.

The general structure of the change is as follows:
 * Extend the base defining value relation over a subset of vector instructions and vector typed phi & select instructions.
 * Move scalarization from before base pointer rewriting to after base pointer rewriting. The extension of the BDV relation is sufficient to find vector base phis for vector inputs.
 * Preserve the existing special case logic for when the base of a vector element is locally obvious. This general idea could be extended to the scalar case as well.

Differential Revision: http://reviews.llvm.org/D10461#inline-84275



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:47:37 +00:00
Jingyue Wu
a70d990f47 [NVPTX] noop when kernel pointers are already global
Summary:
Some front ends make kernel pointers global already. In that case,
handlePointerParams does nothing.

Test Plan: more tests in lower-kernel-ptr-arg.ll

Reviewers: grosser

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10779

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:35:43 +00:00
Tom Stellard
0be7d0cf17 AMDPGU/SI: Use correct resource descriptors for VI on HSA
Summary: We need to set MTYPE = 2 for VI shaders when targeting the HSA runtime.

Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D10777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:42 +00:00
Tom Stellard
4a888086a4 AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10772

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:31 +00:00
Philip Reames
f84a6504a6 [Verifier] Verify invokes of intrinsics
We support invoking a subset of llvm's intrinsics, but the verifier didn't account for this.  We had previously added a special case to verify invokes of statepoints.  By generalizing the code in terms of CallSite, we can verify invokes of other intrinsics as well.  Interestingly, this found one test case which was invalid.

Note: I'm deliberately leaving the naming change from CI to CS to a follow up change.  That will happen shortly, I just wanted to reduce the diff to make it clear what was happening with this one.

Differential Revision: http://reviews.llvm.org/D10118



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240836 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:39:44 +00:00
Adrian Prantl
110ef3ea12 Debug info: Add more test coverage for bitfields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240834 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:27:16 +00:00
Tom Stellard
d40b451727 AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240832 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:11 +00:00
Tom Stellard
ac1a45e511 AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:07 +00:00
Tom Stellard
4aad126e37 AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10706

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:03 +00:00
Tom Stellard
0d1bd457c6 AMDGPU/SI: Emit amd_kernel_code_t in EmitFunctionBodyStart()
Summary:
This way the function symbol points to the start of amd_kernel_code_t
rather than the start of the function.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:14:58 +00:00