140 Commits

Author SHA1 Message Date
Nikolay Haustov
1c038cf2fa [AMDGPU] Assembler: Basic support for MIMG
Add parsing and printing of image operands. Matches legacy sp3 assembler.
Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last.
Update SITargetLowering for new order.
Add basic MC test.
Update CodeGen tests.

Review: http://reviews.llvm.org/D17574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-26 09:51:05 +00:00
Nikolay Haustov
e49a867008 [AMDGPU] Assembler: Simplify handling of optional operands
Resubmit with index problem fixed. Verified with valgrind.

Prepare to support DPP encodings.

For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands.
However this means that when parsing instruction which has no mnemonic prefix,
we cannot add both default values for VOP3 and for DPP optional operands
to OperandVector - neither instructions would match. So add default values
for optional operands to MCInst during conversion instead.

Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.

Review: http://reviews.llvm.org/D17445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261856 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-25 10:58:54 +00:00
NAKAMURA Takumi
f9b2d20a17 Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"
It brought undefined behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261839 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-25 08:35:27 +00:00
Nikolay Haustov
8d04517faf [AMDGPU] Assembler: Simplify handling of optional operands
Prepare to support DPP encodings.

For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead.

Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.

Review: http://reviews.llvm.org/D17445

Reviewers: tstellarAMD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261742 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-24 14:22:47 +00:00
Tom Stellard
1d53227930 [AMDGPU][llvm-mc] Support for 32-bit inline literals
Patch by: Artem Tamazov

Summary:
Note: Support for 64-bit inline literals TBD
Added: Support of abs/neg modifiers for literals (incomplete; parsing TBD).
Added: Some TODO comments.
Reworked/clarity: rename isInlineImm() to isInlinableImm()
Reworked/robustness: disallow BitsToFloat() with undefined value in isInlinableImm()
Reworked/reuse: isSSrc32/64(), isVSrc32/64()
Tests added.

Reviewers: tstellarAMD, arsenm

Subscribers: vpykhtin, nhaustov, SamWot, arsenm

Projects: #llvm-amdgpu-spb

Differential Revision: http://reviews.llvm.org/D17204

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261559 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-22 19:17:56 +00:00
Nikolay Haustov
031bdd80ab Test commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261199 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-18 10:02:12 +00:00
Benjamin Kramer
ed899defb0 Fix uninitialized memory read.
Found by msan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260676 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-12 12:37:21 +00:00
Tom Stellard
0f13bd9bd1 [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing
Summary:
Added support for "VOP3Only" attribute in VOP3bInst encoding.
Set VOP3Only=1 for V_DIV_SCALE_F64/32 insns.
Added support for multi-dest instructions in AMDGPUAs::cvt*().
Added lit test for "V_DIV_SCALE_F64|F32 vreg,vcc|sreg,vreg,vreg,vreg".

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm, SamWot, nhaustov, vpykhtin

Differential Revision: http://reviews.llvm.org/D16995

Patch By: Artem Tamazov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260560 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-11 18:25:26 +00:00
Tom Stellard
4ea8ee7c76 [AMDGPU] Assembler: Fix VOP3 only instructions
Separate methods to convert parsed instructions to MCInst:

  - VOP3 only instructions (always create modifiers as operands in MCInst)
  - VOP2 instrunctions with modifiers (create modifiers as operands
    in MCInst when e64 encoding is forced or modifiers are parsed)
  - VOP2 instructions without modifiers (do not create modifiers
    as operands in MCInst)
  - Add VOP3Only flag. Pass HasMods flag to VOP3Common.
  - Simplify code that deals with modifiers (-1 is now same as
    0). This is no longer needed.
  - Add few tests (more will be added separately).
    Update error message now correct.

Patch By: Nikolay Haustov

Differential Revision: http://reviews.llvm.org/D16778

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-11 03:28:15 +00:00
Tom Stellard
641de45f36 AMDGPU: waitcnt operand fixes
Summary:
Allow lgkmcnt up to 0xF (hardware allows that).
Fix mask for ExpCnt in AMDGPUInstPrinter.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16314

Patch by: Nikolay Haustov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259059 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-28 17:13:44 +00:00
Benjamin Kramer
030c9dc308 Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258917 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-27 10:01:28 +00:00
Tom Stellard
1536863668 AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI
Summary:
These register has different encodings on CI and VI, so we add pseudo
FLAT_SCRACTH registers to be used before MC, and subtarget specific
registers to be used by the MC layer.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256178 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21 18:44:27 +00:00
Tom Stellard
d26f921796 AMDGPU/SI: Emit constant arrays in the .hsrodata_readonly_agent section
Summary: This is done only when targeting HSA.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D13807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-03 03:34:32 +00:00
Tom Stellard
27cbe8f717 AMDGPU/SI: Correctly emit agent global segment variables when targeting HSA
Differential Revision: http://reviews.llvm.org/D14508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254540 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-02 19:47:57 +00:00
Matt Arsenault
418d565e54 AMDGPU: Disallow flat_scr in SI assembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254459 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-01 20:31:08 +00:00
Akira Hatanaka
55c0268714 Reduce the size of MCRelaxableFragment.
MCRelaxableFragment previously kept a copy of MCSubtargetInfo and
MCInst to enable re-encoding the MCInst later during relaxation. A copy
of MCSubtargetInfo (instead of a reference or pointer) was needed
because the feature bits could be modified by the parser.

This commit replaces the MCSubtargetInfo copy in MCRelaxableFragment
with a constant reference to MCSubtargetInfo. The copies of
MCSubtargetInfo are kept in MCContext, and the target parsers are now
responsible for asking MCContext to provide a copy whenever the feature
bits of MCSubtargetInfo have to be toggled.
 
With this patch, I saw a 4% reduction in peak memory usage when I
compiled verify-uselistorder.lto.bc using llc.

rdar://problem/21736951

Differential Revision: http://reviews.llvm.org/D14346


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253127 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 06:35:56 +00:00
Akira Hatanaka
ff528b6f03 [MCTargetAsmParser] Move the member varialbes that reference
MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a
member function getSTI.

This is done in preparation for making changes to shrink the size of
MCRelaxableFragment. (see http://reviews.llvm.org/D14346).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253124 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-14 05:20:05 +00:00
Tom Stellard
65cad952e4 AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D13804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252291 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-06 11:45:14 +00:00
Matt Arsenault
944e560063 AMDGPU: Disallow s[102:103] on VI in assembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252142 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-05 03:11:27 +00:00
Matt Arsenault
0fa6f807f0 AMDGPU: Make flat_scratch name consistent
The printed name and the parsed assembler names weren't the same.
I'm not sure which name SC prints these as, but I think it's this one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-03 22:50:34 +00:00
Matt Arsenault
8ad4a20d3e AMDGPU: Fix asserts on invalid register ranges
If the requested SGPR was not actually aligned, it was
accepted and rounded down instead of rejected.

Also fix an assert if the range is an invalid size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252009 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-03 22:50:32 +00:00
Matt Arsenault
e2849a9de0 AMDGPU: Fix off by one error in register parsing
If trying to use one past the end, this would assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252008 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-03 22:50:27 +00:00
Matt Arsenault
1d04de1b64 AMDGPU: Print modifiers when dumping AMDGPUOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251160 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-24 00:12:56 +00:00
Matt Arsenault
481eaf3a10 AMDGPU: Fix parsing of 32-bit literals with sign bit set
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251132 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-23 18:07:58 +00:00
Tom Stellard
63c550368d AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp
Summary:
The assembly printing of these is still missing the encoding size
suffix, but this will be fixed in a later commit.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D13436

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249424 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 15:57:53 +00:00
Tom Stellard
1566e71dbd AMDGPU/SI: Use .hsatext section instead of .text for HSA
Reviewers: arsenm, grosbach, rafael

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248619 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-25 21:41:28 +00:00
Craig Topper
2e1b727d8d Don't pass StringRefs around by const reference. Pass by value instead per coding standards. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248136 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 00:18:00 +00:00
Matt Arsenault
3a8d465ddd AMDGPU: Use StringRef value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247344 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 21:51:15 +00:00
Matt Arsenault
fa7378ca6e AMDGPU/SI: Fix input vcc operand for VOP2b instructions
Adds vcc to output string input for e32. Allows option
of using e64 encoding with assembler.

Also fixes these instructions not implicitly reading exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247074 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-08 21:15:00 +00:00
Matt Arsenault
8f019b2aa3 AMDGPU: Implement AMDGPUOperand::print()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244381 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-08 00:41:51 +00:00
Tom Stellard
825c884e40 AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CI
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11604

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244254 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-06 19:28:38 +00:00
Colin LeMahieu
f78e199cb2 [llvm-mc] Pushing plumbing through for --fatal-warnings flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 21:56:53 +00:00
Ranjeet Singh
b0f7871d4e Reverting r241058 because it's causing buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241061 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 12:32:53 +00:00
Ranjeet Singh
a5106ca54d There are a few places where subtarget features are still
represented by uint64_t, this patch replaces these
usages with the FeatureBitset (std::bitset) type.

Differential Revision: http://reviews.llvm.org/D10542


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 11:30:42 +00:00
Tom Stellard
4a888086a4 AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10772

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:31 +00:00
Tom Stellard
4077bd9b3b AMDGPU/SI: Remove unused variable
This should fix some bots that were broken by r240831.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:26 +00:00
Tom Stellard
ac1a45e511 AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:07 +00:00
Alexander Kornienko
cd52a7a381 Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
Apparently, the style needs to be agreed upon first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 09:49:53 +00:00
Alexander Kornienko
cf0db29df2 Fixed/added namespace ending comments using clang-tidy. NFC
The patch is generated using this command:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
  -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \
  llvm/lib/


Thanks to Eugene Kosov for the original patch!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240137 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-19 15:57:42 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00