1369 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
fc0391434b [Hexagon] Deal with undefs when extending live intervals
Reapply r280275, since MSVC accepts r280358.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280369 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-01 13:59:35 +00:00
Dean Michael Berris
1d154049a4 [NFC] Remove unnecessary comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280336 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-01 01:58:24 +00:00
Dean Michael Berris
31a52c200b [XRay][NFC] Promote isTailCall() as virtual in TargetInstrInfo.
This change is broken out from D23986, where XRay detects tail call
exits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280331 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-01 01:03:22 +00:00
Reid Kleckner
27e101d577 Revert "Add an optional parameter with a list of undefs to extendToIndices"
This reverts commit r280268, it causes all MSVC 2013 to ICE. This
appears to have been fixed in a later MSVC 2013 update, because I cannot
reproduce it locally. That said, all upstream LLVM bots are broken right
now, so I am reverting.

Also reverts dependent change r280275, "[Hexagon] Deal with undefs when
extending live intervals".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-31 22:36:02 +00:00
Krzysztof Parzyszek
5cedb44a09 [Hexagon] Deal with undefs when extending live intervals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280275 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-31 18:52:09 +00:00
Ron Lieberman
79a4f4e2ea [Hexagon] Remove extraneous debug output from HexagonCopyToCombine.cpp
BB# ...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279750 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-25 16:46:09 +00:00
Ron Lieberman
142e7149f3 [Hexagon] vector store print tracing.
Add vector store print tracing option for hexagon vector instructions.

https://reviews.llvm.org/D23870



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-25 13:35:48 +00:00
Matthias Braun
690a3cbc95 MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to dump/parse it in .mir files.

Differential Revision: http://reviews.llvm.org/D23850

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279698 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-25 01:27:13 +00:00
Krzysztof Parzyszek
d720b00354 [Hexagon] Check for block end when skipping debug instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279681 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 22:36:35 +00:00
Krzysztof Parzyszek
9d1674fd71 [Hexagon] Change insertion of expand-condsets pass to avoid memory leaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279678 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 22:27:36 +00:00
Krzysztof Parzyszek
8f3d1c879f [Hexagon] Enable subregister liveness tracking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279642 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 17:17:39 +00:00
Krzysztof Parzyszek
dff4c003ac [Hexagon] Remove the utilization of IMPLICIT_DEFs from expand-condsets
This is no longer necessary, because since r279625 the subregister
liveness properly accounts for read-undefs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279637 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 16:36:37 +00:00
Krzysztof Parzyszek
31a5f885bf Create subranges for new intervals resulting from live interval splitting
The register allocator can split a live interval of a register into a set
of smaller intervals. After the allocation of registers is complete, the
rewriter will modify the IR to replace virtual registers with the corres-
ponding physical registers. At this stage, if a register corresponding
to a subregister of a virtual register is used, the rewriter will check
if that subregister is undefined, and if so, it will add the <undef> flag
to the machine operand. The function verifying liveness of the subregis-
ter would assume that it is undefined, unless any of the subranges of the
live interval proves otherwise.
The problem is that the live intervals created during splitting do not
have any subranges, even if the original parent interval did. This could
result in the <undef> flag placed on a register that is actually defined.

Differential Revision: http://reviews.llvm.org/D21189


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279625 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 13:37:55 +00:00
Matthias Braun
fa5c5c7db3 CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this patch, hopefully I will get away without any warnings
in the constructor now.

This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279602 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 01:52:46 +00:00
Richard Smith
5a65f77485 Revert r279564. It introduces undefined behavior (binding a reference to a
dereferenced null pointer) in MachineModuleInfo::MachineModuleInfo that causes
-Werror builds (including several buildbots) to fail.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279580 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 22:08:27 +00:00
Matthias Braun
1bb228f703 CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this commit with the deletion of a MachineFunction delegated to
a separate pass to avoid use after free when doing this directly in
AsmPrinter.

This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279564 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 20:58:29 +00:00
Krzysztof Parzyszek
7fd3acfecb [Hexagon] Packetize return value setup with the return instruction
Commit r279241 unintentionally reverted that ability.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279526 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 16:01:01 +00:00
Matthias Braun
eb3b7392bb Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses"
Reverting while tracking down a use after free.

This reverts commit r279502.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 05:17:11 +00:00
Matthias Braun
ded269b907 CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 03:20:09 +00:00
Krzysztof Parzyszek
48a33fd8e5 [Hexagon] Avoid register dependencies on indirect branches in packetizer
Do not packetize the instruction setting the branch address with the
indirect branch itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279324 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 21:07:35 +00:00
Krzysztof Parzyszek
23d2b8b052 [Hexagon] Fix subesthetic indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 19:29:15 +00:00
Krzysztof Parzyszek
f9a8e626ac [Hexagon] Allow i1 values for 'r' constraint in inline-asm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279302 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 19:17:28 +00:00
Krzysztof Parzyszek
35e408df06 [Hexagon] Do not cache alloca instructions during isel
They can be deleted or replicated, so the cache may become outdated.
They only need to be visited once during frame lowering, so just scan
the function instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279297 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 18:46:13 +00:00
Krzysztof Parzyszek
4ef1afc7ce [Hexagon] Fixes for new-value jump formation
- Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i.
- Avoid creating new-value instructions with both source operands equal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279286 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 17:54:49 +00:00
Krzysztof Parzyszek
40f2f0a8b7 [Hexagon] Fix a few omissions in HexagonInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279280 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 17:20:57 +00:00
Krzysztof Parzyszek
1ea0947ff4 [Hexagon] Enforce LLSC packetization rules
Ensure that load locked and store conditional instructions are only
packetized with ALU32 instructions.

Patch by Ben Craig.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279272 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 16:57:05 +00:00
Krzysztof Parzyszek
3930987e21 [Hexagon] Minor updates to register definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279269 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 16:40:19 +00:00
Krzysztof Parzyszek
0ad37f781f [Hexagon] Fix incorrect generation of S4_subi_asl_ri
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279267 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 16:35:05 +00:00
Krzysztof Parzyszek
66e19711ac [Hexagon] Add missing pattern for C4_cmplte
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279265 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 16:11:33 +00:00
Krzysztof Parzyszek
1e982df509 [Hexagon] Make p0 an explicit operand in VA1_clr* subinstructions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279255 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 15:17:19 +00:00
Krzysztof Parzyszek
f7fe146c5a [Hexagon] Add explicit default constructor for HexagonSelectionDAGInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279254 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 15:13:54 +00:00
Krzysztof Parzyszek
041a158c5d [Hexagon] Allow tail-call optimization when mixing C and fast calling conv
Patch by Arnold Schwaighofer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279251 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 15:02:18 +00:00
Krzysztof Parzyszek
b6b40cf4e9 [Hexagon] Check for empty live interval
Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279249 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:29:43 +00:00
Krzysztof Parzyszek
efe70d2368 [Hexagon] Consider zext/sext of a load to i32 to be free
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279248 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:22:07 +00:00
Krzysztof Parzyszek
09091ea512 [Hexagon] Handle J2_jumptpt and J2_jumpfpt instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279246 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:14:09 +00:00
Krzysztof Parzyszek
b8ce83f3cd [Hexagon] Fix indentation, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279245 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:12:51 +00:00
Krzysztof Parzyszek
89c1dd3771 [Hexagon] Remove unnecessary llvm::, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279244 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:10:57 +00:00
Krzysztof Parzyszek
288392e3a9 [Hexagon] Rename the HEXAGON_MC namespace to Hexagon_MC, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279243 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:09:47 +00:00
Krzysztof Parzyszek
8fa77e005c [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279241 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 14:04:45 +00:00
Krzysztof Parzyszek
43073745de [Hexagon] Improvements to handling and generation of FP instructions
Improved handling of fma, floating point min/max, additional load/store
instructions for floating point types.

Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279239 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-19 13:34:31 +00:00
Michael Kuperstein
175a34b53e [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround
The names of the tablegen defs now match the names of the ISD nodes.
This makes the world a slightly saner place, as previously "fround" matched
ISD::FP_ROUND and not ISD::FROUND.

Differential Revision: https://reviews.llvm.org/D23597


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279129 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-18 20:08:15 +00:00
Krzysztof Parzyszek
22850ef9c5 [Hexagon] Create vcombine in HexagonCopyToCombine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279067 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-18 14:12:34 +00:00
Justin Bogner
7d7a23e700 Replace a few more "fall through" comments with LLVM_FALLTHROUGH
Follow up to r278902. I had missed "fall through", with a space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278970 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-17 20:30:52 +00:00
Justin Bogner
6673ea81f6 Replace "fallthrough" comments with LLVM_FALLTHROUGH
This is a mechanical change of comments in switches like fallthrough,
fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-17 05:10:15 +00:00
Duncan P. N. Exon Smith
f623792723 Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278878 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-17 00:34:00 +00:00
Krzysztof Parzyszek
d179884eca [Hexagon] Standardize next batch of pseudo instructions
ALIGNA          PS_aligna
ALLOCA          PS_alloca
TFR_FI          PS_fi
TFR_FIA         PS_fia
TFR_PdFalse     PS_false
TFR_PdTrue      PS_true
VMULW           PS_vmulw
VMULW_ACC       PS_vmulw_acc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278832 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 18:08:40 +00:00
Krzysztof Parzyszek
84668a064a [Hexagon] Clean up some miscellaneous V60 intrinsics a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278823 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 17:14:44 +00:00
Krzysztof Parzyszek
0ebd4a8ba5 [Hexagon] Standardize vector predicate load/store pseudo instructions
- Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and
  the 128B counterparts.
- Rename:
    LDriq_pred_V6         PS_vloadrq_ai
    LDriq_pred_V6_128B    PS_vloadrq_ai_128B
    STriq_pred_V6         PS_vstorerq_ai
    STriq_pred_V6_128B    PS_vstorerq_ai_128B


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278813 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 15:43:54 +00:00
Sjoerd Meijer
47a3de7f4d MachineLoop: add methods findLoopControlBlock and findLoopPreheader
This adds two new utility functions findLoopControlBlock and findLoopPreheader
to MachineLoop and MachineLoopInfo. These functions are refactored and taken
from the Hexagon target as they are target independent; thus this is intendend to
be a non-functional change.

Differential Revision: https://reviews.llvm.org/D22959


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278661 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 08:22:42 +00:00
Ron Lieberman
26d2a23314 Fix unsupported relocation type R_HEX_6_X' for symbol .rodata
LowerTargetConstantPool is not properly setting the TargetFlag to indicate
desired relocation. Coding error, the offset parameter was omitted, so the
TargetFlag was used as the offset, and the TargetFlag defaulted to zero.

This only affects -fpic compilation, and only those items created in a
Constant Pool, for example a vector of constants. Halide ran into this issue.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278614 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-13 23:41:11 +00:00