Commit Graph

156726 Commits

Author SHA1 Message Date
Daniel Sanders
8f5a591f29 [globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
  (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
  (sext:i32 (load:i16 $ptr)<<unindexedload>>)

I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.

Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317971 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 03:23:44 +00:00
Craig Topper
975df6ffda [X86] Correct the execution domain on ROUND/VROUND instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317968 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:26:05 +00:00
Craig Topper
20487ae90c [X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC
No one ever uses this default and probably shouldn't since it sets the execution domain to generic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317967 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:26:02 +00:00
NAKAMURA Takumi
b99884c4a5 llvm/Support/TargetParser.h: Fix -fmodules build in rL317900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317966 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:05:47 +00:00
Tony Tye
995388dd36 [AMDGPU] Correct targets that support XNACK
Differential Revision: https://reviews.llvm.org/D39887


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317955 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 00:50:32 +00:00
Craig Topper
aa795776c9 [SelectionDAG] Make getUniformBase in SelectionDAGBuilder fail if any of the middle GEP indices are non-constant.
This is a fix for a bug in r317947. We were supposed to check that all the indices are are constant 0, but instead we're only make sure that indices that are constant are 0. Non-constant indices are being ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317950 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 23:36:56 +00:00
Zachary Turner
d3e2d8422a Update test_debuginfo.pl script to point to new tree location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317949 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 23:13:14 +00:00
Craig Topper
9d3d840987 [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.

This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.

We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.

Differential Revision: https://reviews.llvm.org/D39911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317947 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:50:50 +00:00
Evgeniy Stepanov
e3ff9fbdba [asan] Use dynamic shadow on 32-bit Android.
Summary:
The following kernel change has moved ET_DYN base to 0x4000000 on arm32:
https://marc.info/?l=linux-kernel&m=149825162606848&w=2

Switch to dynamic shadow base to avoid such conflicts in the future.

Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation
until PR35221 is fixed. This will eventually let use save one load per function.

Reviewers: kcc

Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39393

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317943 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:27:48 +00:00
Martin Storsjo
4a22e748f2 [llvm-cvtres] Add support for ARM64
Also change some default cases into llvm_unreachable in
WindowsResourceCOFFWriter, to make it easier to find if they
are triggerd from within e.g. lld, which supported ARM64 earlier
than llvm-cvtres did.

Differential Revision: https://reviews.llvm.org/D39892

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317942 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:27:41 +00:00
Mitch Phillips
7c7bb61bbf [cfi-verify] Made FileAnalysis operate on a GraphResult rather than build one and validate it.
Refactors the behaviour of building graphs out of FileAnalysis, allowing for analysis of the GraphResult by the callee without having to rebuild the graph. Means when we want to analyse the constructed graph (planned for later revisions), we don't do repeated work.

Also makes CFI verification in FileAnalysis now return an enum that allows us to differentiate why something failed, not just that it did/didn't fail.

Reviewers: vlad.tsyrklevich

Subscribers: kcc, pcc, llvm-commits

Differential Revision: https://reviews.llvm.org/D39764

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317927 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 21:00:22 +00:00
Amaury Sechet
24331f974f [DAGcombine] Do not replace truncate node by itself when doing constant folding, this trigger needless extra rounds of combine for nothing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317926 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:59:53 +00:00
Zachary Turner
cbf08c741a [debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang.  This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.

The goal of this patch is to migrate towards a more standard
workflow.  To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.

Differential Revision: https://reviews.llvm.org/D39605

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:57:57 +00:00
Tony Tye
2f2cb6b2a2 [AMDGPU] AMDGPUUsage.rst minor corrections
Differential Revision: https://reviews.llvm.org/D39887


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317924 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:51:43 +00:00
Davide Italiano
4013502618 [SimplifyCFG] Use auto * when the type is obvious. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317923 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:46:21 +00:00
Krzysztof Parzyszek
0f47b426bf Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC
The Windows builder did not reconstruct the HexagonGenDAGISel.inc file
after the TableGen binary has changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317921 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:09:46 +00:00
Konstantin Zhuravlyov
8f4df2fc0b AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td
Differential Revision: https://reviews.llvm.org/D39880


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317920 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:01:58 +00:00
Daniel Neilson
6850d9138b Expand IRBuilder interface for atomic memcpy to require pointer alignments. (NFC)
Summary:
 The specification of the @llvm.memcpy.element.unordered.atomic intrinsic requires
that the pointer arguments have alignments of at least the element size. The existing
IRBuilder interface to create a call to this intrinsic does not allow for providing
the alignment of these pointer args. Having an interface that makes it easy to
construct invalid intrinsic calls doesn't seem sensible, so this patch simply
adds the requirement that one provide the argument alignments when using IRBuilder
to create atomic memcpy calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317918 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:38:12 +00:00
Krzysztof Parzyszek
e8afbbe959 Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"
This reverts r317904: broke Windows build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:27:18 +00:00
Craig Topper
33a8b75763 [X86] Merge the template method selectAddrOfGatherScatterNode into selectVectorAddr. NFCI
Just need to initialize a couple variables differently based on the node type. No need for a whole separate template method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317915 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:26:04 +00:00
Adrian Prantl
23bd33afd4 Add back target triple to test which I accidentally removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317912 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:22:02 +00:00
Sanjoy Das
7af26ab717 [CVP] Remove some {s|u}add.with.overflow checks.
Summary:
This adds logic to CVP to remove some overflow checks.  It uses LVI to remove
operations with at least one constant.  Specifically, this can remove many
overflow intrinsics immediately following an overflow check in the source code,
such as:

if (x < INT_MAX)
    ... x + 1 ...

Patch by Joel Galenson!

Reviewers: sanjoy, regehr

Reviewed By: sanjoy

Subscribers: fhahn, pirama, srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D39483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:13:35 +00:00
Mandeep Singh Grang
12ca5fd711 [RISCV] Silence an unused variable warning in release builds [NFC]
Summary:
Also minor cleanups:
1. Avoided multiple calls to Fixup.getKind()
2. Avoided multiple calls to getFixupKindInfo()
3. Removed a redundant return.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, llvm-commits

Differential Revision: https://reviews.llvm.org/D39881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317908 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:09:28 +00:00
Craig Topper
1924c0ebef [X86] Add test case to demonstrate failure to fold the address computation of a simple gather from a global array. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317905 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:48:18 +00:00
Krzysztof Parzyszek
38f2fbe008 [Hexagon] Create HexagonISelDAGToDAG.h, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317904 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:39:45 +00:00
Krzysztof Parzyszek
9911901fcd Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.

Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:

  class FooDAGToDAGISel : public SelectionDAGISel {
    // Pull in declarations only.
    #define GET_DAGISEL_DECL
    #include "FooISelDAGToDAG.inc"
  };

  // Include the function bodies (with names qualified with the provided
  // class name).
  #define GET_DAGISEL_BODY FooDAGToDAGISel
  #include "FooISelDAGToDAG.inc"

When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).

Differential Revision: https://reviews.llvm.org/D39596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317903 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:36:04 +00:00
Lang Hames
9e7ee78426 [ADT] Rewrite mapped_iterator in terms of iterator_adaptor_base.
Summary:
This eliminates the boilerplate implementation of the iterator interface in
mapped_iterator.

This patch also adds unit tests that verify that the mapped function is applied
by operator* and operator->, and that references returned by the map function
are returned via operator*.

Reviewers: dblaikie, chandlerc

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D39855

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317902 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 17:41:28 +00:00
Craig Topper
ec87e5d458 [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
Summary:
I want to leverage this to clean up some of the code in clang. This will allow us to simplify D39521 which was trying to do some of the same.

If we accurately keep the code in Host.cpp synced with new CPUs added to compile-rt/libgcc we should be able to use this file as a proxy for what's implemented in the libraries.

The entries for the CPUs recognized by the libraries use separate macros that define additional parameters like the name for __builtin_cpu_is and an alias string for the couple cases where __builtin_cpu_is accepts two different names.

All of the macros contain an ARCHNAME that is usually the same as the __builtin_cpu_is string, but sometimes isn't. This represents the name recognized by X86.td and -march.

I'm following the precedent set by ARM and AArch64 and adding this information to lib/Support/TargetParser.cpp

Reviewers: erichkeane, echristo, asbirlea

Reviewed By: echristo

Subscribers: llvm-commits, aemerson, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317900 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 17:10:57 +00:00
Bob Haarman
d4f1cfbb84 LTO: don't fatal when value for cache key already exists
Summary:
LTO/Caching.cpp uses file rename to atomically set the value for a
cache key. On Windows, this fails when the destination file already
exists. Previously, LLVM would report_fatal_error in such
cases. However, because the old and the new value for the cache key
are supposed to be equivalent, it actually doesn't matter which one we
keep. This change makes it so that failing the rename when an openable
file with the desired name already exists causes us to report success
instead of fataling.

Reviewers: pcc, hans

Subscribers: mehdi_amini, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317899 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 17:08:21 +00:00
Adrian Prantl
dc7bbb86a4 Move test into X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:36:04 +00:00
Jatin Bhateja
be808009ac [WebAssembly] Fix stack offsets of return values from call lowering.
Summary: Fixes PR35220

Reviewers: vadimcn, alexcrichton

Reviewed By: alexcrichton

Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D39866

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317895 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:26:04 +00:00
Florian Hahn
9239900417 [AArch64][SVE] Asm: More concise test format
Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file.

The tests check the following:

 * All instructions are assembled correctly into the right encoding.
 * All instructions are disassembled correctly (into the preferred assembly format)
 * Without -mattr=+sve the instructions are not assembled.
 * Without -mattr=+sve the instructions are not disassembled.

This patch also adds several negative tests for SVE add/sub.


Patch by Sander De Smalen.

Reviewed by: rengolin, fhahn

Differential Revision: https://reviews.llvm.org/D39792


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 16:25:16 +00:00
Simon Pilgrim
3343c3a754 [X86] Add scheduling tests for DAA/DAS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317892 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 15:49:41 +00:00
Igor Laevsky
68960b1207 [llvm-opt-fuzzer] Add missed library dependence. Fir for rL317883
Differential Revision: https://reviews.llvm.org/D39555




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317889 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 15:08:14 +00:00
Simon Pilgrim
41ecf7e107 [X86] Test non-i64 shld/shll tests on x86_64 targets as well as i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317888 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 13:43:04 +00:00
Igor Laevsky
224217d714 [llvm-opt-fuzzer] Fix unused variable warning after rL317883
Differential Revision: https://reviews.llvm.org/D39555



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317887 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 13:19:14 +00:00
Simon Pilgrim
7702921068 [X86] Add scheduling tests
- CBW etc sign extensions
 - CLC/CLD/CMC flag modifiers
 - CPUID

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317885 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:32:34 +00:00
Alexander Timofeev
23476c4f80 [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one
Differential revision: https://reviews.llvm.org/D38754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317884 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:21:10 +00:00
Igor Laevsky
089f886ad9 [llvm-opt-fuzzer] Introduce llvm-opt-fuzzer for fuzzing optimization passes
This change adds generic fuzzing tools capable of running libFuzzer tests on
any optimization pass or combination of them.

Differential Revision: https://reviews.llvm.org/D39555



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317883 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:19:08 +00:00
Simon Pilgrim
d84a31be44 [X86] Added TODO list for missing generic x86 instruction scheduling tests.
Not sure if we want to add the more exotic system instructions (IRET etc.) as well?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317882 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 12:04:39 +00:00
Karl-Johan Karlsson
823bedeb8e [RegisterCoalescer] Move debug value after rematerialize trivial def
Summary:
The associated debug value is updated when the virtual source register
of a copy is completely eliminated and replaced with a rematerialize
value in the defed register of the copy. As the debug value now is
associated with another register it also need to be moved, otherwise
the debug value isn't valid.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: MatzeB, llvm-commits, qcolombet

Differential Revision: https://reviews.llvm.org/D38024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317880 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 09:48:40 +00:00
Jonas Paulsson
a9fba7123d [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.
* The method getRegAllocationHints() is now of bool type instead of void. If
true is returned, regalloc (AllocationOrder) will *only* try to allocate the
hints, as opposed to merely trying them before non-hinted registers.

* TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with
an increase in number of LOCRs.

In this case, it is desired to force the hints even though there is a slight
increase in spilling, because if a non-hinted register would be allocated,
the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR
(Load On Condition) SystemZ instruction must have both operands in either the
low or high part of the 64 bit register.

Reviewers: Quentin Colombet and Ulrich Weigand
https://reviews.llvm.org/D36795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317879 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 08:46:26 +00:00
Craig Topper
cad7a316e0 [X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C)
Support the opposite direction as well. Also add a TODO for not being able to combine FMSUB/FNMADD/FNMSUB with FNEG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317878 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 08:22:37 +00:00
Craig Topper
f737152c33 [X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
I've also added TODOs for intrinsic removal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 06:07:37 +00:00
Yaxun Liu
bd2cfd038d [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
r600 uses dummy pointer info for lowering load/store. Since dummy pointer info
assumes address space 0, this causes isel failure when temporary load/store SDNodes
are generated for amdgiz environment.

Since the offest is not constant, FixedStack pseudo source value cannot be used
to create the pointer info. This patch creates pointer info using llvm undef value.
At least this provides correct address space so that isel can be done correctly.

Differential Revision: https://reviews.llvm.org/D39698


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317862 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 02:03:28 +00:00
Yaxun Liu
d3bd6cf5cc [AMDGPU] Fix pointer info for pseudo source for r600
The pointer info for pseudo source for r600 is not correct when
alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D39670


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317861 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 01:53:24 +00:00
Tony Tye
9000e8c60d [AMDGPU] Update code object description
- Use ELF header flags to identify processor.
 - Remove isa note record.
 - Add target feature section.
 - Make metadata for NumVGPRs, NumSGPRs and MaxFlatWorkGroupSize required.
 - Add FixedWorkGroupSize to CodeProps metadata.
 - Add ReqdWorkGroupSize* to kernel descriptor and move MaxFlatWorkGroupSize to be adjacent.
 - Move IsXNACKEnabled in the kernel descriptor to be at the end of the unused flags.
 - Remove IsDynamicCallStack from the metadata and kernel descriptor.
 - Remove legacy debugger metadata.
 - Remove old XNACK enabled processor names.

Differential Revision: https://reviews.llvm.org/D39828


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317855 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 01:00:54 +00:00
Volodymyr Sapsai
8887214dfa [ThinLTO] Fix missing call graph edges for calls with bitcasts.
This change doesn't fix the root cause of the miscompile PR34966 as the root
cause is in the linker ld64. This change makes call graph more complete
allowing to have better module imports/exports.

rdar://problem/35344706

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39356



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317853 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 00:47:47 +00:00
Bob Haarman
37ff1dce27 [support] allocate exact size required for mapping in Support/Windws/Path.inc
Summary:
zturner suggested that mapped_file_region::init() on Windows seems to
create mappings that are larger than they need to be: Offset+Size
instead of Size. Indeed, that appears to be the case. I confirmed that
tests pass with mappings of just Size bytes, and fail with Size-1
bytes, suggesting that Size is indeed the correct value.

Reviewers: amccarth, zturner

Reviewed By: zturner

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317850 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 00:17:31 +00:00
Easwaran Raman
68d2cebf10 [SimplifyCFG] Fix a test case.
This was first committed in r317845, but had the order of branch weights
wrong and didn't properly check the output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317848 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09 23:17:52 +00:00