102590 Commits

Author SHA1 Message Date
Davide Italiano
9689ee1fa3 [NewGVN] Fix a consistent order for phi nodes operands.
The way we currently define congruency for two PHIExpression(s) is:

1) The operands to the phi functions are congruent
2) The PHIs are defined in the same BasicBlock.

NewGVN works under the assumption that phi operands are in predecessor
order, or at least in some consistent order. OTOH, is valid IR:

patatino:
  %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ]
  %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ]
  br label %end

and the in-memory representations of the two SSA registers have an
inconsistent order. This violation of NewGVN assumptions results into
two PHIs found congruent when they're not. While we think it's useful
to have always a consistent order enforced, let's fix this in NewGVN
sorting uses in predecessor order before creating a PHI expression.

Differential Revision:  https://reviews.llvm.org/D32990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:58:28 +00:00
Craig Topper
80f6556e8a [APInt] Remove return value from tcFullMultiply.
The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you.

No one uses the result today so rather than try to fix it, just remove it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:47:33 +00:00
Daniel Berlin
954e86756a NewGVN: Make all of symbolic evaluation logically const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:40:04 +00:00
Craig Topper
0e5156e98f [X86] Add more patterns for BZHI isel
This patch adds more patterns that a reasonable person might write that can be compiled to BZHI.

This adds support for

(~0U >> (32 - b)) & a;

and

a << (32 - b) >> (32 - b);

This was inspired by the code in APInt::clearUnusedBits.

This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case.

I think this is still missing cases where the subtract portion is an 8-bit operation.

Differential Revision: https://reviews.llvm.org/D32616

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:32:11 +00:00
Sanjay Patel
5c355ea7dc [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.
The comment says to avoid the case where zero bits are shifted into the truncated value, 
but the code checks that the shift is smaller than the truncated value instead of the 
number of bits added by the sign extension. Fixing this allows a shift by more than the 
value size to be introduced, which is undefined behavior, so the shift is capped at the 
value size minus one, which has the expected behavior of filling the value with the sign 
bit.

Patch by Jacob Young!

Differential Revision: https://reviews.llvm.org/D32285



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:24:59 +00:00
Guy Blank
a610a6eaf3 VX512] Only look at lower bit in constant scalar masks
for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit.
This patch handles cases where the lower bit is '1'.

Differential Revision: https://reviews.llvm.org/D32805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:16:48 +00:00
Reid Kleckner
7dfa173654 Re-land "Use the frame index side table for byval and inalloca arguments"
This re-lands r302483. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302544 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:02:20 +00:00
Reid Kleckner
d3285d0ce4 Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This re-lands commit r302461. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302543 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:01:47 +00:00
Tim Shen
f52671da9b [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction instead. NFC.
Now both emitLeadingFence and emitTrailingFence take the instruction
itself, instead of taking IsLoad/IsStore pairs.
Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used
for determining those two booleans.

The instruction argument is also useful for later D32763, in
emitTrailingFence. For emitLeadingFence, it seems to have cleaner
interface with the proposed change.

Differential Revision: https://reviews.llvm.org/D32762

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302539 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 15:27:17 +00:00
Aaron Ballman
25e22520d5 Amend r302535; ifndef and ifdef are different, as it turns out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302537 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 15:12:03 +00:00
Aaron Ballman
dd718cb76d ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:59:48 +00:00
Hans Wennborg
1f81185df2 Revert r302469 "Make it illegal for two Functions to point to the same DISubprogram"
This caused PR32977.

Original commit message:

> Make it illegal for two Functions to point to the same DISubprogram
>
> As recently discussed on llvm-dev [1], this patch makes it illegal for
> two Functions to point to the same DISubprogram and updates
> FunctionCloner to also clone the debug info of a function to conform
> to the new requirement. To simplify the implementation it also factors
> out the creation of inlineAt locations from the Inliner into a
> general-purpose utility in DILocation.
>
> [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
> <rdar://problem/31926379>
>
> Differential Revision: https://reviews.llvm.org/D32975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302533 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:44:15 +00:00
Anna Thomas
1fbed43c3e [LV] Fix insertion point for shuffle vectors in first order recurrence
Summary:
In first order recurrence vectorization, when the previous value is a phi node, we need to
set the insertion point to the first non-phi node.
We can have the previous value being a phi node, due to the generation of new
IVs as part of trunc optimization [1].

[1] https://reviews.llvm.org/rL294967

Reviewers: mssimpso, mkuper

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:29:33 +00:00
Aaron Ballman
9bd179193e Removing a file that is not necessary (and was causing link diagnostics with MSVC 2015); NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 14:22:48 +00:00
Serge Pavlov
1f4a80fdc1 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:35:13 +00:00
Simon Dardis
5cd1e6d400 Revert "[MIPS] Add support to match more patterns for DINS instruction"
This reverts commit rL302512. This broke the mips buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:18:48 +00:00
Simon Pilgrim
d1adb786cc [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)
Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD.

Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal.

Differential Revision: https://reviews.llvm.org/D32973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302525 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:14:40 +00:00
Diana Picus
42ab77b051 Revert "[Dwarf] Disable reference verification for now (PR32972)"
This reverts commit r302520 because it break the unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302524 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:05:43 +00:00
Renato Golin
972328b093 [Dwarf] Disable reference verification for now (PR32972)
There is no other explanation about why this only started happening
now, even though it crashes on old code (supposedly reachable from
here).

The only common factor between the failing bots is that they use GCC
(4.9 and 5.3) to compile Clang, while the others use Clang 3.8, but the
failure is while building the tests, as an assertion, on Clang.

Commenting it out for now in hope the bots will go back green, but we
should keep looking for the real cause, and update bugzilla.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302520 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 12:36:50 +00:00
Amara Emerson
8f1f7ce9d1 Introduce experimental generic intrinsics for horizontal vector reductions.
- This change allows targets to opt-in to using them instead of the log2
  shufflevector algorithm.
- The SLP and Loop vectorizers have the common code to do shuffle reductions
  factored out into LoopUtils, and now have a unified interface for generating
  reductions regardless of the preference of the target. LoopUtils now uses TTI
  to determine what kind of reductions the target wants to handle.
- For CodeGen, basic legalization support is added.

Differential Revision: https://reviews.llvm.org/D30086



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302514 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:43:25 +00:00
Nikolai Bozhenov
64dbd2ef25 [X86] Clang option -fuse-init-array has no effect when generating for MCU target
Reviewers: Eugene.Zelenko, dschuff, craig.topper

Reviewed By: craig.topper

Subscribers: ahatanak, aaboud, DavidKreitzer, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D32543
Patch by AndreiGrischenko <andrei.l.grischenko@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:14:03 +00:00
Strahinja Petrovic
4ab11e2a6b [MIPS] Add support to match more patterns for DINS instruction
This patch adds support for recognizing patterns to match
DINS instruction.

Differential Revision: https://reviews.llvm.org/D31465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302512 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:02:00 +00:00
Diana Picus
4f0f7c08bf [ARM GlobalISel] Remove hand-written G_FADD selection
Remove the code selecting G_FADD - now that TableGen can handle more
opcodes, it's not needed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302511 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 08:32:42 +00:00
Craig Topper
b23f8ea900 [ConstantRange] Rewrite shl to avoid repeated calls to getUnsignedMax and avoid creating the min APInt until we're sure we need it. Use inplace shift operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302510 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 07:04:04 +00:00
Craig Topper
eef1c41964 [ConstantRange] Combine the two adds max+1 in lshr into a single addition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302509 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 07:04:02 +00:00
Craig Topper
384ba40c27 [ConstantRange] Use APInt::isNullValue in place of comparing with 0. The compiler should be able to generate slightly better code for the former. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 05:01:29 +00:00
Reid Kleckner
5c900216f1 Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This reverts commit r302461.

It appears to be causing failures compiling gtest with debug info on the
Linux sanitizer bot. I was unable to reproduce the failure locally,
however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302504 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:57:44 +00:00
Teresa Johnson
bb89593724 Fix code section prefix for proper layout
Summary:
r284533 added hot and cold section prefixes based on profile
information, to enable grouping of hot/cold functions at link time.
However, it used "cold" as the prefix for cold sections, but gold only
recognizes "unlikely" (which is used by gcc for cold sections).
Therefore, cold sections were not properly being grouped. Switch to
using "unlikely"

Reviewers: danielcdh, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302502 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:43:24 +00:00
Kostya Serebryany
ea56ec314e [libFuzzer] update docs on -print_coverage/-dump_coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302498 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:34:27 +00:00
Kostya Serebryany
de20a5381a [libFuzzer] make sure the input data is not overwritten in the fuzz target (if it is -- report an error)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302494 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:17:29 +00:00
Reid Kleckner
3d5255af74 Revert "Use the frame index side table for byval and inalloca arguments"
This reverts r302483 and it's follow up fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302493 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:14:39 +00:00
Craig Topper
5bc7ae494b [APInt] Use default constructor instead of explicitly creating a 1-bit APInt in udiv and urem. NFC
The default constructor does the same thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:49:54 +00:00
Craig Topper
8894742d7d [APInt] Remove 'else' after 'return' in udiv and urem. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:49:49 +00:00
Evgeniy Stepanov
fa138d2588 Ignore !associated metadata with null argument.
Fixes PR32577 (comment 10).
Such metadata may legitimately appear in LTO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302485 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:46:20 +00:00
Reid Kleckner
8c3a49c4c1 Use the frame index side table for byval and inalloca arguments
Summary:
For inalloca functions, this is a very common code pattern:

  %argpack = type <{ i32, i32, i32 }>
  define void @f(%argpack* inalloca %args) {
  entry:
    %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0
    %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1
    %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2
    tail call void @llvm.dbg.declare(metadata i32* %a, ... "a")
    tail call void @llvm.dbg.declare(metadata i32* %c, ... "b")
    tail call void @llvm.dbg.declare(metadata i32* %b, ... "c")

Even though these GEPs can be simplified to a constant offset from EBP
or RSP, we don't do that at -O0, and each GEP is computed into a
register. Registers used to compute argument addresses are typically
spilled and clobbered very quickly after the initial computation, so
live debug variable tracking loses information very quickly if we use
DBG_VALUE instructions.

This change moves processing of dbg.declare between argument lowering
and basic block isel, so that we can ask if an argument has a frame
index or not. If the argument lives in a register as is the case for
byval arguments on some targets, then we don't put it in the side table
and during ISel we emit DBG_VALUE instructions.

Reviewers: aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302483 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:20:27 +00:00
Sanjoy Das
00d88a77e1 [InstNamer] Use range-for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302481 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:18:43 +00:00
Sanjoy Das
284277df9a [InstNamer] Don't check type of arguments (they're never void)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302480 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:18:39 +00:00
Sanjoy Das
447ca1ab6d Delete trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:18:36 +00:00
Greg Clayton
cca9d00b74 Add const to "DWARFDie &Die" in a few functions as they can't change the DWARFDie.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302471 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 21:29:17 +00:00
Eugene Zemtsov
4f230b8d83 Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302470 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 21:20:53 +00:00
Adrian Prantl
28bd5d128c Make it illegal for two Functions to point to the same DISubprogram
As recently discussed on llvm-dev [1], this patch makes it illegal for
two Functions to point to the same DISubprogram and updates
FunctionCloner to also clone the debug info of a function to conform
to the new requirement. To simplify the implementation it also factors
out the creation of inlineAt locations from the Inliner into a
general-purpose utility in DILocation.

[1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
<rdar://problem/31926379>

Differential Revision: https://reviews.llvm.org/D32975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302469 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 21:17:08 +00:00
Greg Clayton
a086b24688 Fix typo "veify" to "verify".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302466 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 20:53:00 +00:00
Sanjay Patel
b8a453126a [InstCombine] add folds for not-of-shift-right
This is another step towards getting rid of dyn_castNotVal, 
so we can recommit:
https://reviews.llvm.org/rL300977

As the tests show, we were missing the lshr case for constants
and both ashr/lshr vector splat folds. The ashr case with constant
was being performed inefficiently in 2 steps. It's also possible
there was a latent bug in that case because we can't do that fold
if the constant is positive:
http://rise4fun.com/Alive/Bge



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302465 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 20:49:59 +00:00
Davide Italiano
29aef3c4af [PartialInlining] Capture by reference rather than by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302464 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 20:44:01 +00:00
Tim Northover
a641bd93fb ARM: use divmod libcalls on embedded MachO platforms too.
The separated libcalls are implemented in terms of __divmodsi4 and __udivmodsi4
anyway, so we should always use them if possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302462 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 20:00:14 +00:00
Reid Kleckner
550359cb2f Don't add DBG_VALUE instructions for static allocas in dbg.declare
Summary:
An llvm.dbg.declare of a static alloca is always added to the
MachineFunction dbg variable map, so these values are entirely
redundant. They survive all the way through codegen to be ignored by
DWARF emission.

Effectively revert r113967

Two bugpoint-reduced test cases from 2012 broke as a result of this
change. Despite my best efforts, I haven't been able to rewrite the test
case using dbg.value. I'm not too concerned about the lost coverage
because these were reduced from the test-suite, which we still run.

Reviewers: aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32920

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302461 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 19:58:15 +00:00
Zachary Turner
f019c6b219 [CodeView] Add support for random access type visitors.
Previously type visitation was done strictly sequentially, and
TypeIndexes were computed by incrementing the TypeIndex of the
last visited record.  This works fine for situations like dumping,
but not when you want to visit types in random order.  For example,
in a debug session someone might lookup a symbol by name, find that
it has TypeIndex 10,000 and then want to go straight to TypeIndex
10,000.

In order to make this work, the visitation framework needs a mode
where it can plumb TypeIndices through the callback pipeline.  This
patch adds such a mode.  In doing so, it is necessary to provide
an alternative implementation of TypeDatabase that supports random
access, so that is done as well.

Nothing actually uses these random access capabilities yet, but
this will be done in subsequent patches.

Differential Revision: https://reviews.llvm.org/D32928

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302454 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 18:38:43 +00:00
Quentin Colombet
4a1e357426 [AArch64][RegisterBankInfo] Change the default mapping of fp loads.
This fixes PR32550, in a way that does not imply running the greedy
mode at O0.

The fix consists in checking if a load is used by any floating point
instruction and if yes, we return a default mapping with FPR instead
of GPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302453 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 18:16:31 +00:00
Quentin Colombet
3343d80c50 [AArch64][RegisterBankInfo] Fix mapping cost for GPR.
In r292478, we changed the order of the enum that is referenced by
PMI_FirstXXX. This had the side effect of changing the cost of the
mapping of all the loads, instead of just the FPRs ones.

Reinstate the higher cost for all but GPR loads.
Note: This did not have any external visible effects:
- For Fast mode, the cost would have been higher, but we don't care
  because we don't try to use alternative mappings.
- For Greedy mode, the higher cost of the GPR loads, would have
  triggered the use of the supposedly alternative mapping, that
  would be in fact the same GPR mapping but with a lower cost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302452 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 18:16:23 +00:00
Craig Topper
3f67904aa9 [ARM] Use a Changed flag to avoid making a pass's return value dependent on a compare with a Statistic object.
Statistic compile to always be 0 in release build so this compare would always return false. And in the debug builds Statistic are global variables and remember their values across pass runs. So this compare returns true anytime the pass runs after the first time it modifies something.

This was found after reviewing all usages of comparison operators on a Statistic object. We had some internal code that did a compare with a statistic that caused a mismatch in output between debug and release builds. So we did an audit out of paranoia.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302450 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 18:02:51 +00:00