Commit Graph

10587 Commits

Author SHA1 Message Date
Philip Reames
9bdd5df2ca Whitespace change to reduce diff in future patch.
Patch 2 of 11 in 'Add a "probe-stack" attribute' review thread

Patch by: john.kare.alsaker@gmail.com



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216235 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:19:16 +00:00
Philip Reames
ecad452885 [X86] Split out the logic to select the stack probe function (NFC)
Patch 1 of 11 in 'Add a "probe-stack" attribute' review thread.

Patch by: <john.kare.alsaker@gmail.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216233 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:15:20 +00:00
Adam Nemet
9db660ecaa [AVX512] Add class to group common template arguments related to vector type
We discussed the issue of generality vs. readability of the AVX512 classes
recently.  I proposed this approach to try to hide and centralize the mappings
we commonly perform based on the vector type.  A new class X86VectorVTInfo
captures these.

The idea is to pass an instance of this class to classes/multiclasses instead
of the corresponding ValueType.  Then the class/multiclass can use its field
for things that derive from the type rather than passing all those as separate
arguments.

I modified avx512_valign to demonstrate this new approach.  As you can see
instead of 7 related template parameters we now have one.  The downside is
that we have to refer to fields for the derived values.  I named the argument
'_' in order to make this as invisible as possible.  Please let me know if you
absolutely hate this.  (Also once we allow local initializations in
multiclasses we can recover the original version by assigning the fields to
local variables.)

Another possible use-case for this class is to directly map things, e.g.:

  RegisterClass KRC = X86VectorVTInfo<32, i16>.KRC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 19:50:07 +00:00
Josh Klontz
f19807db70 X86AsmPrinter MCJIT MSVC bug fix.
Summary:
This bug was introduced in r213006 which makes an assumption that MCSection is COFF for Windows MSVC. This assumption is broken for MCJIT users where ELF is used instead [1]. The fix is to change the MCSection cast to a dyn_cast.

[1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-December/068407.html.

Reviewers: majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 12:55:27 +00:00
Benjamin Kramer
f11ac42d01 X86: Turn redundant if into an assertion.
While there remove noop casts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216168 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 10:31:37 +00:00
Robert Khasanov
fec1abaeab [x86] Added _addcarry_ and _subborrow_ intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216164 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:43:43 +00:00
Robert Khasanov
375a68ca15 [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216163 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:34:12 +00:00
Robert Khasanov
10dacc4b52 [x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216162 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:27:00 +00:00
Robert Khasanov
3a34f5e115 [x86] Enable Broadwell target.
Added FeatureSMAP.

Broadwell ISA includes Haswell ISA + ADX + RDSEED + SMAP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:16:12 +00:00
Sanjay Patel
89305e5345 Don't prevent a vselect of constants from becoming a single load (PR20648).
Fix for PR20648 - http://llvm.org/bugs/show_bug.cgi?id=20648

This patch checks the operands of a vselect to see if all values are constants.
If yes, bail out of any further attempts to create a blend or shuffle because
SelectionDAGLegalize knows how to turn this kind of vselect into a single load.

This already happens for machines without SSE4.1, so the added checks just send
more targets down that path.

Differential Revision: http://reviews.llvm.org/D4934


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216121 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-20 20:34:56 +00:00
Duncan P. N. Exon Smith
5012f1db20 X86: Align the stack on word boundaries in LowerFormalArguments()
The goal of the patch is to implement section 3.2.3 of the AMD64 ABI
correctly.  The controlling sentence is, "The size of each argument gets
rounded up to eightbytes.  Therefore the stack will always be eightbyte
aligned." The equivalent sentence in the i386 ABI page 37 says, "At all
times, the stack pointer should point to a word-aligned area."  For both
architectures, the stack pointer is not being rounded up to the nearest
eightbyte or word between the last normal argument and the first
variadic argument.

Patch by Thomas Jablin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-20 19:40:59 +00:00
Keno Fischer
4b1cddbaf0 Do not insert a tail call when returning multiple values on X86
Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=19530.
The problem is that X86ISelLowering erroneously thought the third call
was eligible for tail call elimination.
It would have been if it's return value was actually the one returned
by the calling function, but here that is not the case and
additional values are being returned.

Test Plan: Test case from the original bug report is included.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D4968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216117 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-20 19:00:37 +00:00
Pavel Chupin
aadaac228d [x32] Fix FrameIndex check in SelectLEA64_32Addr
Summary:
Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new
lea-5.ll case.
Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in
ESP/EBP case.

Test Plan: lea tests modified to include x32/nacl and new test added

Reviewers: nadav, dschuff, t.p.northover

Subscribers: llvm-commits, zinovy.nis

Differential Revision: http://reviews.llvm.org/D4929

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-20 11:59:22 +00:00
Juergen Ributzka
96b1e70c66 Reapply [FastISel][X86] Add large code model support for materializing floating-point constants (r215595).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
In the large code model for X86 floating-point constants are placed in the
constant pool and materialized by loading from it. Since the constant pool
could be far away, a PC relative load might not work. Therefore we first
materialize the address of the constant pool with a movabsq and then load
from there the floating-point value.

Fixes <rdar://problem/17674628>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216012 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-19 19:44:13 +00:00
Juergen Ributzka
9c23685dd2 Reapply [FastISel][X86] Use XOR to materialize the "0" value (r215594).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216011 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-19 19:44:10 +00:00
Juergen Ributzka
e8757c5dbb Reapply [FastISel][X86] Emit more efficient instructions for integer constant materialization (r215593).
Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
This mostly affects the i64 value type, which always resulted in an 15byte
mobavsq instruction to materialize any constant. The custom code checks the
value of the immediate and tries to use a different and smaller mov
instruction when possible.

This fixes <rdar://problem/17420988>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216010 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-19 19:44:06 +00:00
Akira Hatanaka
6290308366 [X86, X87 stackifier] Do not mark an operand of a debug instruction as kill.
<rdar://problem/16952634>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215962 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-19 02:09:57 +00:00
Quentin Colombet
0526d167a9 [X86][Haswell][SchedModel] Tidy up.
<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215924 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:56:01 +00:00
Quentin Colombet
48e3a273de [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215923 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:59 +00:00
Quentin Colombet
7af88ec907 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:56 +00:00
Quentin Colombet
487ecab8d4 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Math instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215921 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:53 +00:00
Quentin Colombet
3d6a30ea3b [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:51 +00:00
Quentin Colombet
25529b337f [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Conversion instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215919 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:49 +00:00
Quentin Colombet
540b4f6c08 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215918 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:46 +00:00
Quentin Colombet
7bdfd1b443 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer MMX and XMM instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215917 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:43 +00:00
Quentin Colombet
0c5071f561 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer MMX and XMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215916 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:41 +00:00
Quentin Colombet
1cb132f921 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer MMX and XMM instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215915 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:39 +00:00
Quentin Colombet
84cab94cbb [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer MMX and XMM instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215914 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:36 +00:00
Quentin Colombet
f8da7e552c [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point x87 instructions.
Sub-group: Math instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215913 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:32 +00:00
Quentin Colombet
435fa2bddf [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point x87 instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215912 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:29 +00:00
Quentin Colombet
a49b463a19 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point x87 instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215911 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:26 +00:00
Quentin Colombet
d2ea3168ae [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215910 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:23 +00:00
Quentin Colombet
184c0f8b2f [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Synchronization instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215909 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:21 +00:00
Quentin Colombet
2a2fcc1a0e [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: String instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:19 +00:00
Quentin Colombet
0cccab7515 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Control transfer instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215907 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:16 +00:00
Quentin Colombet
29b31c6eaf [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:13 +00:00
Quentin Colombet
3f17d37327 [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215905 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:11 +00:00
Quentin Colombet
94ce368a5e [X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 17:55:08 +00:00
Elena Demikhovsky
9735ccb7ea AVX-512: Fixed a bug in emitting compare for MVT:i1 type.
Added a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 11:59:06 +00:00
Tim Northover
049ffbbdf2 TableGen: allow use of uint64_t for available features mask.
ARM in particular is getting dangerously close to exceeding 32 bits worth of
possible subtarget features. When this happens, various parts of MC start to
fail inexplicably as masks get truncated to "unsigned".

Mostly just refactoring at present, and there's probably no way to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 11:49:42 +00:00
Elena Demikhovsky
36d685d8e8 Reverted last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215828 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17 09:39:48 +00:00
Elena Demikhovsky
8b88009194 Reverted last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215827 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17 09:36:07 +00:00
Elena Demikhovsky
a73ac1f463 Added a table for intrinsics on X86.
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics.
I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17 09:00:20 +00:00
Chandler Carruth
48c67ed949 [x86] Fix an indentation goof in a prior commit. Should have re-run
clang-format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215824 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17 00:40:34 +00:00
Chandler Carruth
a3805f1c73 [x86] Teach lots of the new vector shuffle lowering to use UNPCK
instructions for blend operations at 128 bits. This was a serious hole
in our prior blend lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215819 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-16 09:42:15 +00:00
Robin Morisset
f0d509a1ba Get rid of dead code: SelectAtomic64 in X86ISelDAGtoDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215789 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 23:36:00 +00:00
Reid Kleckner
2726e7d60b Fix the build with MSVC 2013 after new shuffle code
MSVC gives this awesome diagnostic:

..\lib\Target\X86\X86ISelLowering.cpp(7085) : error C2971: 'llvm::VariadicFunction1' : template parameter 'Func' : 'isShuffleEquivalentImpl' : a local variable cannot be used as a non-type argument
        ..\include\llvm/ADT/VariadicFunction.h(153) : see declaration of 'llvm::VariadicFunction1'
        ..\lib\Target\X86\X86ISelLowering.cpp(7061) : see declaration of 'isShuffleEquivalentImpl'

Using an anonymous namespace makes the problem go away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215744 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 18:03:58 +00:00
Chandler Carruth
92ee945e2e [x86] Teach the new AVX v4f64 shuffle lowering to use UNPCK instructions
where applicable for blending.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 17:42:00 +00:00
Rafael Espindola
a348fc7fda Remove HasLEB128.
We already require CFI, so it should be safe to require .leb128 and .uleb128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215712 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 14:01:07 +00:00
Chandler Carruth
12e69a0267 [x86] Add the initial skeleton of type-based dispatch for AVX vectors in
the new shuffle lowering and an implementation for v4 shuffles.

This allows us to handle non-half-crossing shuffles directly for v4
shuffles, both integer and floating point. This currently misses places
where we could perform the blend via UNPCK instructions, but otherwise
generates equally good or better code for the test cases included to the
existing vector shuffle lowering. There are a few cases that are
entertainingly better. ;]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215702 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 11:01:40 +00:00