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752 Commits

Author SHA1 Message Date
Zoran Jovanovic
814c8910f2 LL and SC decoder method fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199316 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 13:17:33 +00:00
Zoran Jovanovic
f5c2d3896b Added support for LWU microMIPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199315 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 13:01:18 +00:00
Venkatraman Govindaraju
fcb6800dd4 [Sparc] Add support for parsing floating point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199033 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-12 04:48:54 +00:00
Saleem Abdulrasool
a2fce1169d ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions 
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-12 04:36:01 +00:00
Saleem Abdulrasool
793e2aaa73 ARM: fix regression caused by r198914 
The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 16:22:47 +00:00
Venkatraman Govindaraju
7ceaa8623c [Sparc] Add support for parsing branch instructions and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198738 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 06:14:52 +00:00
Venkatraman Govindaraju
9429f47d83 [Sparc] Add initial implementation of disassembler for sparc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 08:08:58 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:29:32 +00:00
Craig Topper
8dff260267 Add two fp test cases I missed in my previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 23:15:19 +00:00
Craig Topper
45e6393241 Add more X86 FP stack disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 22:51:53 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 17:21:44 +00:00
Elena Demikhovsky
09a63715ce AVX-512: decoder for AVX-512, made by Alexey Bader. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 11:40:51 +00:00
Richard Sandiford
f7e24324ba [SystemZ] Add MC support for interlocked-access 1 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197984 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 15:14:05 +00:00
Hal Finkel
1427abbf6b Add a disassembler to the PowerPC backend 
The tests for the disassembler were adapted from the encoder tests, and for the
most part, the output from the disassembler matches that encoder-test inputs.
There are some places where more-informative mnemonics could be produced
(notably for the branch instructions), and those cases are noted in the tests
with FIXMEs.

Future work includes:

 - Generating more-informative mnemonics when possible (this may also be done
   in the printer).

 - Remove the dependence on positional "numbered" operand-to-variable mapping
   (for both encoding and decoding).

 - Internally using 64-bit instruction variants in 64-bit mode (if this turns
   out to matter).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197693 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-19 16:13:01 +00:00
Kevin Qin
9224192321 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-29 01:29:16 +00:00
Hao Liu
cdd732cdd3 AArch64: Fix a bug about disassembling post-index load single element to 4 vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-28 01:07:45 +00:00
Chad Rosier
9fef0370c5 [AArch64] Add support for NEON scalar floating-point absolute difference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 01:45:58 +00:00
Chad Rosier
48f115aabf [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-26 22:17:37 +00:00
Hao Liu
e04ed6b8b1 Fixed a bug about disassembling AArch64 post-index load/store single element instructions. 
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-25 01:53:26 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 02:17:05 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 01:57:32 +00:00
Richard Sandiford
541c5de2fb [SystemZ] Add the general form of BCR 
At the moment this is just the MC support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 16:57:53 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 13:15:03 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 19:13:08 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 19:56:13 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 18:04:07 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-08 16:16:30 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-07 14:35:24 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 02:25:49 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 03:39:32 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-04 14:53:22 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 22:36:59 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 19:28:44 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 09:32:11 +00:00
Artyom Skrobov
3f04b50686 [ARM] NEON instructions were erroneously decoded from certain invalid encodings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 18:10:09 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 15:19:37 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 16:38:59 +00:00
Artyom Skrobov
b161955ffb Make ARM hint ranges consistent, and add tests for these ranges 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-23 10:14:40 +00:00
Tim Northover
01b0e94bb7 ARM: provide diagnostics on more writeback LDM/STM instructions 
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-22 19:00:39 +00:00
Richard Barton
485333df71 Add hint disassembly syntax for 16-bit Thumb hint instructions. 
Patch by Artyom Skrobov



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-18 14:09:49 +00:00
Chad Rosier
c439c205ba [AArch64] Add support for NEON scalar extract narrow instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-18 14:03:24 +00:00
Chad Rosier
3b370a2ac4 [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-17 18:12:29 +00:00
Chad Rosier
dceac4c5a6 [AArch64] Add support for NEON scalar negate instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:39 +00:00
Chad Rosier
a249914462 [AArch64] Add support for NEON scalar absolute value instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:34 +00:00
Chad Rosier
8225b23c6a Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 16:30:10 +00:00
Chad Rosier
a2cd42a0a7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 16:09:02 +00:00
Chad Rosier
1824bd0ef8 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-15 21:18:44 +00:00