Commit Graph

123747 Commits

Author SHA1 Message Date
Igor Laevsky
a277dc299e Strip metadata when speculatively hoisting instructions
This is fix for PR24059.

When we are hoisting instruction above some condition it may turn out
that metadata on this instruction was control dependant on the condition.
This metadata becomes invalid and we need to drop it.

This patch should cover most obvious places of speculative execution (which
I have found by greping isSafeToSpeculativelyExecute). I think there are more
cases but at least this change covers the severe ones.

Differential Revision: http://reviews.llvm.org/D14398



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 14:10:31 +00:00
Oliver Stannard
3d0708d4a4 Update test to use explicit triple
This is needed for targets which do not support big-endian with the default
triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 14:09:08 +00:00
Tilmann Scheller
dc09445cfe [PowerPC] Remove redundant code.
The local variable Hi is never being read.

Issue identified by the Clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252600 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 12:29:37 +00:00
Oliver Stannard
2358986dd4 [AArch64] Fix halfword load merging for big-endian targets
For big-endian targets, when we merge two halfword loads into a word load, the
order of the halfwords in the loaded value is reversed compared to
little-endian, so the load-store optimiser needs to swap the destination
registers.

This does not affect merging of two word loads, as we use ldp, which treats the
memory as two separate 32-bit words.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252597 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 11:04:18 +00:00
Hans Wennborg
be73ba8c82 Inliner: Do zero-cost inlines even if above a negative threshold (PR24851)
Differential Revision: http://reviews.llvm.org/D14499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 09:47:48 +00:00
Igor Breger
fcb6d5f29c AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions.
Differential Revision: http://reviews.llvm.org/D14492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252592 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 07:09:07 +00:00
David Blaikie
4156947702 Remove another variable unused in -Asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 04:10:04 +00:00
David Blaikie
3747ae395d Remove some unused variables to clean up the -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252580 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 03:16:28 +00:00
Colin LeMahieu
a19450f7b9 [Hexagon] Adding instruction aliases and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252579 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 01:58:26 +00:00
Andy Ayers
1d8af51850 Support for emitting inline stack probes
For CoreCLR on Windows, stack probes must be emitted as inline sequences that probe successive stack pages
between the current stack limit and the desired new stack pointer location. This implements support for
the inline expansion on x64.

For in-body alloca probes, expansion is done during instruction lowering. For prolog probes, a stub call
is initially emitted during prolog creation, and expanded after epilog generation, to avoid complications
that arise when introducing new machine basic blocks during prolog and epilog creation.

Added a new test case, modified an existing one to exclude non-x64 coreclr (for now).

Add test case

Fix tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252578 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 01:50:49 +00:00
Richard Diamond
8de644391a Fix mingw targets. Bandaid for r252532's buildbot brakage.
Reviewers: brad.king, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252576 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 01:03:51 +00:00
Colin LeMahieu
e9d8d5bb25 [Hexagon] Fixing compound register printing and reenabling more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:51:56 +00:00
Tim Northover
eefe9f5a54 AArch64: add experimental support for address tagging.
AArch64 has the ability to use the top 8-bits of an "address" for extra
information, with the memory subsystem automatically masking them off for loads
and stores. When that's happening, we can sometimes skip masks on memory
operations in the compiler.

However, this requires the host OS and support stack to preserve those bits so
it can't be enabled everywhere. In principle iOS 8.0 and above do take the
required precautions and but we'll put it under a flag for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:44:23 +00:00
Kevin Enderby
7f0edadcaf Fix llvm-nm(1) printing of llvm-bitcode files for -format darwin to match darwin’s nm(1).
Also a small fix to match printing of Mach-O objects with -format posix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252567 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:31:08 +00:00
Derek Schuff
537330de82 [WebAssembly] Support 'unreachable' expression
Lower LLVM's 'unreachable' terminator to ISD::TRAP, and lower ISD::TRAP to
wasm's 'unreachable' expression.

WebAssembly type-checks expressions, but a noreturn function with a
return type that doesn't match the context will cause a check
failure. So we lower LLVM 'unreachable' to ISD::TRAP and then lower that
to WebAssembly's 'unreachable' expression, which typechecks in any
context and causes a trap if executed.

Differential Revision: http://reviews.llvm.org/D14515

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252566 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:30:57 +00:00
Matt Arsenault
76916424be Remove unnecessary call to getAllocatableRegClass
I'm not sure what the point of this was. I'm not sure why
you would ever define an instruction that produces an unallocatable
register class. No tests fail with this removed, and it seems like
it should be a verifier error to define such an instruction.

This was problematic for AMDGPU because it would make bad decisions
by arbitrarily changing the register class when unsetting isAllocatable
for VS_32/VS_64, which is currently set as a workaround to this problem.

AMDGPU uses the VS_32/VS_64 register classes to represent operands which
can use either VGPRs or SGPRs. When  isAllocatable is unset for these,
this would need to pick  either the SGPR or VGPR class and insert either
a copy we don't want, or an illegal copy we would need to deal with
later. A semi-arbitrary register class ordering decision is made in tablegen,
which resulted in always picking a VGPR class because it happens to have
more registers than the SGPR register class. We really just want to
use whatever register class the original register had.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252565 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:30:14 +00:00
Xinliang David Li
bcd8e0aae7 [PGO] Make indexed value profile data more compact
- Make indexed value profile data more compact by peeling out 
  the per-site value count field into its own smaller sized array.
- Introduced formal data structure definitions to specify value 
  profile data layout in indexed format. Previously the layout 
  of the data is only assumed in the client code (scattered in 
  three different places : size computation, EmitData, and ReadData
- The new data structure  serves as a central place for layout documentation.
- Add interfaces to force BE output for value profile data (testing purpose)
- Add byte swap unit tests

Differential Revision: http://reviews.llvm.org/D14401


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252563 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:24:45 +00:00
Colin LeMahieu
a7f0a0a566 [Hexagon] Fixing store instructions and reenabling a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252561 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:22:00 +00:00
Akira Hatanaka
67f0f878cd [ARM] Handle t2ADDri in ARMAsmPrinter::EmitUnwindingInstruction.
This fixes a bug in ARMAsmPrinter::EmitUnwindingInstruction where
llvm_unreachable was reached because t2ADDri wasn't handled.

Test case provided by Tim Northover.

rdar://problem/23270609

http://reviews.llvm.org/D14518


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252557 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:10:41 +00:00
Colin LeMahieu
5ca8076fcc [Hexagon] Fixing load instruction parsing and reenabling tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252555 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-10 00:02:27 +00:00
Matthias Braun
ee21e9f823 MachineVerifier: Streamline live interval related error reporting
Simply perform additional report_context() calls after a report()
instead of adding more and more overloaded variations of report().  Also
improve several instances where information was output in an ad-hoc way
probably because no matching report() overload was available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252552 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:59:33 +00:00
Matthias Braun
7b4272f659 MachineVerifier: Add missing linebreak
MachineInstr::print() with SkipOppers==true does not produce a
linebreak, so we have to do that in MachineVerifier::report().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252551 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:59:29 +00:00
Matthias Braun
e5351a1797 MachineVerifier: MI::print has no TargetMachine overload
The code was passing a target machine pointer which degraded to a true
operand to SkipOppers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252550 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:59:25 +00:00
Matthias Braun
806e686676 MachineVerifier: print list of live intervals if available
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252549 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:59:23 +00:00
David Blaikie
53b5ea7f56 Simplify some APIs I was cleaning up while fixing -Wpessimizing-move warning
(Reid fixed the original error, but this seems nice to do in any case)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252548 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:51:45 +00:00
Reid Kleckner
d4f7699f94 Fix -Wpessimizing-move warning in llvm-config.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252542 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:37:26 +00:00
Reid Kleckner
ba2a27d116 [WinEH] Remove isBarrier from instructions that do not return
Fixes machine verification failures with David's latest EH change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252541 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:34:42 +00:00
Sanjay Patel
512052a88e add a SelectionDAG method to check if no common bits are set in two nodes; NFCI
This was suggested in:
http://reviews.llvm.org/D13956

and is a follow-on to:
http://reviews.llvm.org/rL252515
http://reviews.llvm.org/rL252519

This lets us remove logically equivalent/duplicated code from DAGCombiner and X86ISelDAGToDAG.

A corresponding function for IR instructions already exists in ValueTracking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:31:38 +00:00
Duncan P. N. Exon Smith
9df84ef7b9 CodeGen: Be clear about semantics in SlotIndex::getNextSlot(), NFC
Be honest about using iterator semantics in `SlotIndex::getNextSlot()`
and `SlotIndex::getPrevSlot()`.  Instead of calling `getNextNode()` --
which is documented (but fails) to check for the sentinel -- call
`&*++getIterator()`.

This is (surprisingly!) a NFC commit.  `ilist_traits<IndexListEntry>`
has an `ilist_half_node<IndexListEntry>` as a sentinel (and no other
fields), and so the layout of `ilist<IndexListEntry>` is:
--
struct ilist<IndexListEntry> {
  ilist_half_node<IndexListEntry> Sentinel;
  IndexListEntry *Head;

  IndexListEntry *getHead() { return Head; }
  IndexListEntry *getSentinel() { return cast<...>(&Sentinel); }
};
--
In memory, this happens to look just like:
--
struct ilist<IndexListEntry> {
  ilist_node<IndexListEntry> Sentinel;

  IndexListEntry *getHead() { return Sentinel.getNext(); }
  IndexListEntry *getSentinel() { return cast<...>(&Sentinel); }
};
--
As a result, `ilist_node<IndexListEntry>::getNextNode()` that checks
`getNext()` of the possible sentinel will get a pointer to the head of
the list; it will never detect the sentinel, and will return the
sentinel itself instead of `nullptr` in the special cases.

Since `getNextNode()` and `getPrevNode()` don't work, just be honest
that we're not checking for the end/beginning of the list here.  Since
this code works, I guess we must never go past the sentinel.

(It's possible we're just getting lucky, and the new code will get
"lucky" in the same situations.  To properly fix that hypothetical bug,
we would need to check the iterator against `end()`/`begin()`.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252538 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:31:01 +00:00
David Blaikie
b6cb6238b9 Fix -Wdeprecated warnings due to the use of copy ops on SCEVPredicate derived class objects
SCEVUnionPredicate is copied constructed here: lib/Transforms/Scalar/LoopDistribute.cpp:793
and move assigned (which can use the base class's copy ctor just
fine/without extra cost (I'd add it if it weren't for MSVC's issues
meaning = default is insufficient)) here: lib/Transforms/Utils/LoopVersioning.cpp:46

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252537 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:30:15 +00:00
Davide Italiano
36ee8db682 [TargetLibraryInfo] Add support for fls, flsl, flsll.
This is a prerequisite for further optimisations of these functions,
which will be commited as a separate patch.

Differential Revision:	http://reviews.llvm.org/D14219


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252535 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:23:20 +00:00
Kostya Serebryany
f41e3780b3 [libFuzzer] make libFuzzer link if there is no sanitizer coverage instrumentation (it will fail at start-up time)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:17:45 +00:00
Richard Diamond
6c6be14bb5 Fix llvm-config to adapt to the install environment.
Summary:
This patch does a couple of things:

  - Adds a new argument `--shared-mode` which accepts a list of components and prints whether or not the provided components need to be linked statically or shared.
  - Fixes `--libnames` when CMake BUILD_SHARED_LIBS is used.
  - Fixes `--libnames`, `--libs`, and `--libfiles` for dylib when static components aren't installed.
  - Fixes `--libnames`, `--libs`, `--libfiles`, and `--components` to use LLVM_DYLIB_COMPONENTS as the component manifest for dylib linking.
  - Uses the host platform's usual convention for filename extensions and such, instead of always defaulting to Unix-izms.

Because I don't own a Mac, I am not able to test the Mac platform dependent stuff locally. If someone would be willing to run a build for me on their machine (unless there's a better option), I'd appreciate it.

Reviewers: jfb, brad.king, whitequark, beanz

Subscribers: beanz, jauhien, llvm-commits

Differential Revision: http://reviews.llvm.org/D13198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252532 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:15:38 +00:00
Reid Kleckner
963c9c6d07 Combine ifdefs around dl_iterate_phdr in Unix/Signals.inc
This avoids the need to have two dummy implementations of
findModulesAndOffsets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:10:29 +00:00
David Majnemer
c30d240fb8 [WinEH] Don't emit CATCHRET from visitCatchPad
Instead, emit a CATCHPAD node which will get selected to a target
specific sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252528 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 23:07:48 +00:00
Chris Bieneman
5d89904858 Deprecate Autoconf
As per the very positive feedback from llvm-dev (http://lists.llvm.org/pipermail/llvm-dev/2015-November/092150.html), this commit officially deprecates the LLVM autoconf-based build system.

Anyone still using it should switch to CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:54:55 +00:00
Sanjay Patel
9c673d9c54 specify triple so Windows bots won't be sad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:53:58 +00:00
Rafael Espindola
9e4d3eb47d Add templated read/write to support::endian.
Expose read and write functions that take endianess as a template
parameter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252517 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:34:45 +00:00
Sanjay Patel
0e9a62e34f [x86] try harder to match bitwise 'or' into an LEA
The motivation for this patch starts with the epic fail example in PR18007:
https://llvm.org/bugs/show_bug.cgi?id=18007

...unfortunately, this patch makes no difference for that case, but it solves some
simpler cases. We'll get there some day. :)

The current 'or' matching code was using computeKnownBits() via 
isBaseWithConstantOffset() -> MaskedValueIsZero(), but that's an unnecessarily limited use. 
We can do more by copying the logic in ValueTracking's haveNoCommonBitsSet(), so we can 
treat the 'or' as if it was an 'add'.

There's a TODO comment here because we should lift the bit-checking logic into a helper
function, so it's not duplicated in DAGCombiner.

An example of the better LEA matching:

leal (%rdi,%rdi), %eax
andl $1, %esi
orl %esi, %eax

Becomes:

andl $1, %esi
leal (%rsi,%rdi,2), %eax

Differential Revision: http://reviews.llvm.org/D13956



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252515 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:16:49 +00:00
Colin LeMahieu
7fcebdc82b [Hexagon] Separating statement to match what clang-format would do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:06:28 +00:00
Reid Kleckner
c324f8dc3e [WinEH] Tweak funclet prologue/epilogue insertion to pass verifier
For some reason we'd never run MachineVerifier on WinEH code, and you
explicitly have to ask for it with llc. I added it to a few test cases
to get some coverage.

Fixes PR25461.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252512 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 21:04:00 +00:00
Andrew Kaylor
805b66a27c [WinEH] Re-committing r252249 (Clone funclets with multiple parents) with additional fixes for determinism problems
Differential Revision: http://reviews.llvm.org/D14454



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252508 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 19:59:02 +00:00
Reid Kleckner
c04d564033 [Hexagon] Fix -Wmicrosoft-enum-value warning with explicit enum type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 19:44:38 +00:00
Mike Aizatsky
da4cf2cda9 Windows-specific test for sys::path::remove_dots.
Differential Revision: http://reviews.llvm.org/D14503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252504 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 19:36:53 +00:00
Sanjay Patel
034a965d5a don't repeat function names in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252502 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 19:18:26 +00:00
Sanjay Patel
ea45c5101b fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 18:59:30 +00:00
Mike Aizatsky
8cda80ad24 Moving FileManager::removeDotPaths to llvm::sys::path::remove_dots
Differential Revision: http://reviews.llvm.org/D14393

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252499 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 18:56:31 +00:00
Adhemerval Zanella
98e40b8ddf [sanitizer] Use same shadow offset for ASAN on aarch64
This patch makes ASAN for aarch64 use the same shadow offset for all
currently supported VMAs (39 and 42 bits).  The shadow offset is the
same for 39-bit (36).  Similar to ppc64 port, aarch64 transformation
also requires to use an add instead of 'or' for 42-bit VMA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252495 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 18:03:48 +00:00
Dehao Chen
b16171eac2 Add discriminators for call instructions that are from the same line and same basic block.
Summary: Call instructions that are from the same line and same basic block needs to have separate discriminators to distinguish between different callsites.

Reviewers: davidxl, dnovillo, dblaikie

Subscribers: dblaikie, probinson, llvm-commits

Differential Revision: http://reviews.llvm.org/D14464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252492 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 17:30:38 +00:00
Chad Rosier
01eac64506 Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252491 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-09 16:56:06 +00:00