24703 Commits

Author SHA1 Message Date
Michael Berg
71bbcb1f4a propagate fast math flags via IR on fma and sub expressions
Summary: This change uses fmf subflags to guard fma optimizations as well as unsafe. These changes originated from D46483 and have been simplified via getNode.

Reviewers: spatel, arsenm, hfinkel, javed.absar

Reviewed By: spatel

Subscribers: nemanjai, wdng

Differential Revision: https://reviews.llvm.org/D47388

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334242 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-07 22:49:09 +00:00
Matt Arsenault
b6ab0f18f8 DAG: Avoid bitcast/ext/build_vector combine
This avoids regressions in a future AMDGPU change
to make v4i16/v4f16 legal. For these types, build_vector
is implemented as bitcasted operations on v2i32. This
combine was creating v4i16s out of what would have been
already been a v2i32 build_vector, creating a mess
of nodes that never get cleaned up.

I'm not sure this is the right condition to check.
I initially tried just checking for the legality of the
new build_vector. This works for my case, but breaks dozens
of x86 tests. A Mips test seems to show some improvement
or at least a neutral change. I don't want to think
about how long it would take to analyze the set of
different x86 vector operations impacted.

Test included in future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334218 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-07 19:42:27 +00:00
Karl-Johan Karlsson
1c7fca97fb [BranchFolding] Fix live-in's when hoisting code
Summary:
When the branch folder hoist code into a predecessor it adjust live-in's
in the blocks it hoist code from. However it fail to handle hoisted code
that contain a defed register that originally is live-in in the block
through a super register.

This is fixed by replacing the live-in handling code with calls to
utility functions in LivePhysRegs.

Reviewers: kparzysz, gberry, MatzeB, uweigand, aprantl

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334163 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-07 07:20:33 +00:00
Michael Berg
1de1655ed5 guard fsqrt with fmf sub flags
Summary:
This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483.
It contains only context for fsqrt.


Reviewers: spatel, hfinkel, arsenm

Reviewed By: spatel

Subscribers: hfinkel, wdng, andrew.w.kaylor, wristow, efriedma, nemanjai

Differential Revision: https://reviews.llvm.org/D47749

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334113 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 18:47:55 +00:00
David Green
b439319a25 [GlobalMerge] Set the alignment on merged global structs
If no alignment is set, the abi/preferred alignment of structs will be
used which may be higher than required. This can lead to extra padding
and in the end an increase in data size.

Differential Revision: https://reviews.llvm.org/D47633



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334099 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 14:48:32 +00:00
Sanjay Patel
863443f97f [CodeGen] assume max/default throughput for unspecified instructions
This is a fix for the problem arising in D47374 (PR37678):
https://bugs.llvm.org/show_bug.cgi?id=37678

We may not have throughput info because it's not specified in the model 
or it's not available with variant scheduling, so assume that those
instructions can execute/complete at max-issue-width.

Differential Revision: https://reviews.llvm.org/D47723


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334055 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 23:34:45 +00:00
Guozhi Wei
30557dd78b [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions
CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions.

Differential Revision: https://reviews.llvm.org/D45537

This is re-commit of r331783, which was reverted by r333305. The performance regression was caused by some unlucky alignment, not a code generation problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334049 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 21:03:52 +00:00
Michael Berg
e23e5cc5b1 guard fneg with fmf sub flags
Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483.

Reviewers: spatel, hfinkel

Reviewed By: spatel

Subscribers: nemanjai

Differential Revision: https://reviews.llvm.org/D47389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334037 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 18:49:47 +00:00
Matt Arsenault
e5fc674090 DAG: Stop dropping invariant/dereferencable
When legalizing illegal FP load results, this was
for some reason dropping the invariant and dereferencable
memory flags. There doesn't seem to be any reason for this,
and the equivalent isn't done for integer loads.

Fixes an issue in a future AMDGPU commit where some identical
loads fail to merge because one of the loads ends up
dropping the flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334020 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 14:52:24 +00:00
Nirav Dave
4c53b27f1f [RegAllocGreedy] Use simpler map class for EvicteeInfo. NFCI.
RegAlloc keeps a insertion-time ordered map of evictee information,
but we only use membership. Replace MapVector with contextually
equivalent DenseMap which is smaller and faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333981 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 03:16:28 +00:00
Francis Visoiu Mistrih
c29988523b Use MF instead of Fn for MachineFunction references. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333973 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 00:27:28 +00:00
Francis Visoiu Mistrih
e70aaf7304 [ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
Start by emitting remarks for very basic unsupported cases such as
irreducible CFGs and EHFunclets. The end goal is to be able to cover all
the cases where we give up with an explanation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333972 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 00:27:24 +00:00
Amara Emerson
b86b9032fd [MIRParser] Add parser support for 'true' and 'false' i1s.
We already output true and false in the printer, but the parser isn't able to
read it.

Differential Revision: https://reviews.llvm.org/D47424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333970 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 00:17:13 +00:00
Reid Kleckner
9d75364cfa Fix -Wcovered-switch-default warning and clang-format it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333967 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 23:47:29 +00:00
David Blaikie
8325fb20d4 Move Analysis/Utils/Local.h back to Transforms
Review feedback from r328165. Split out just the one function from the
file that's used by Analysis. (As chandlerc pointed out, the original
change only moved the header and not the implementation anyway - which
was fine for the one function that was used (since it's a
template/inlined in the header) but not in general)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333954 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 21:23:21 +00:00
Jessica Paquette
65c5ddb6f8 [MachineOutliner] NFC - Move intermediate data structures to MachineOutliner.h
This is setting up to fix bug 37573 cleanly.

This moves data structures that are technically both used in some way by the
target and the general-purpose outlining algorithm into MachineOutliner.h. In
particular, the `Candidate` class is of importance.

Before, the outliner passed the locations of `Candidates` to the target, which
would then make some decisions about the prospective outlined function. This
change allows us to just pass `Candidates` along to the target. This will allow
the target to discard `Candidates` that would be considered unsafe before cost
calculation. Thus, we will be able to remove the unsafe candidates described in
the bug without resorting to torching the entire prospective function.

Also, as a side-effect, it makes the outliner a bit cleaner.

https://bugs.llvm.org/show_bug.cgi?id=37573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333952 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 21:14:16 +00:00
Scott Linder
b9cccf44aa [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
Some overloads failed to update divergence.

Differential Revision: https://reviews.llvm.org/D47148



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333947 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 20:19:45 +00:00
Amaury Sechet
5f67380d0e [DAGcombine] Teach the combiner about -a = ~a + 1
Summary: This include variant for add, uaddo and addcarry. usubo and subcarry require the carry to be flipped to preserve semantic, but we chose to do the transform anyway in that case as to push the transform down the carry chain.

Reviewers: efriedma, spatel, RKSimon, zvi, bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333943 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 19:23:22 +00:00
Amaury Sechet
7436bb683e Get rid of SETCCE
Summary: It has been deprecated in favor of SETCCCARRY for a year now and isn't used by any in tree backend.

Reviewers: efriedma, craig.topper, dblaikie, bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333939 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 18:36:22 +00:00
Krzysztof Parzyszek
f181103bd3 [SelectionDAG] Add missing closing parentheses in comments, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 14:54:53 +00:00
Vedant Kumar
eacd22487e Add a debug dump for DbgValueHistoryMap
This makes it easier to inspect the results of
DbgValueHistoryCalculator.

Differential Revision: https://reviews.llvm.org/D47663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333801 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 22:33:15 +00:00
Nirav Dave
75446f106a [DAG] Avoid checking for consecutive stores in store merge. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333766 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 15:05:55 +00:00
Nirav Dave
08410ea64b [DAG] Simplify Expression. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333765 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 15:05:30 +00:00
Nirav Dave
5c84d3b038 [DAG] Remove untriggerable check. NFCI.
Candidate check precludes this check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333764 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 15:05:05 +00:00
Nirav Dave
3ef57a09b9 [DAG] Prune store merge legal store check to stop invalid size. NFCI.
Do not consider store sizes large than the maximum legal store size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333763 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 15:04:40 +00:00
Krzysztof Parzyszek
925c3a82e2 [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for target
Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing
the UADDO/USUBO expansion.

Differential Revision: https://reviews.llvm.org/D47559


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333751 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 14:00:32 +00:00
Amaury Sechet
876db10e96 Set ADDE/ADDC/SUBE/SUBC to expand by default
Summary:
They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while.

Target that uses these opcodes are changed in order to ensure their behavior doesn't change.

Reviewers: efriedma, craig.topper, dblaikie, bkramer

Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D47422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333748 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 13:21:33 +00:00
Amara Emerson
82441a3e01 [AArch64][GlobalISel] Zero-extend s1 values when returning.
Before we were relying on the any extend of the s1 to s32, but
for AAPCS we need to zero-extend it to at least s8.

Fixes PR36719

Differential Revision: https://reviews.llvm.org/D47425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333747 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 13:20:32 +00:00
Gabor Buella
48c1879dce NFC Avoid a warning in WasmEHPrepare.cpp
```
../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic]
                 false, false);
                              ^
```


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333732 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 07:47:46 +00:00
Heejin Ahn
2522e34cd5 Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.
Summary:
`getEHScopeMembership()` function is used not only for funclet-based
EHs; they apply to all EH schemes that use the scoped IR
(catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of
the term 'funclet' to 'EH scopes' in case they apply to all scoped EH,
and this fixes more of them. For `FuncletLayout` pass, I left it as is
because the pass is only used for funclet-based EH.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47611

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333711 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 00:03:21 +00:00
Heejin Ahn
60c0443a11 [WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.

Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.

This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)

Reviewers: dschuff, majnemer

Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D44090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333705 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 22:25:54 +00:00
Heejin Ahn
a6e37da488 [WebAssembly] Add Wasm exception handling prepare pass
Summary:
This adds a pass that transforms a program to be prepared for Wasm
exception handling. This is using Windows EH instructions and based on
the previous Wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)

Reviewers: dschuff, majnemer

Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D43746

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333696 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 22:02:34 +00:00
Jonas Devlieghere
7eeba255a6 [ADT] Make escaping fn conform to coding guidelines
As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in
StringExtras did not conform to the LLVM coding guidelines. This commit
rectifies that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333669 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 17:01:42 +00:00
Andrea Di Biagio
ae5fb65ace [MCSchedule] Add the ability to compute the latency and throughput information for MCInst.
This patch extends the MCSchedModel API with new methods that can be used to
obtain the latency and reciprocal througput information for an MCInst.

Scheduling models have recently gained the ability to resolve variant scheduling
classes associated with MCInst objects. Before, models were only able to resolve
a variant scheduling class from a MachineInstr object.

This patch is mainly required by D47374 to avoid regressing a pair of x86
specific -print-schedule tests for btver2. Patch D47374 introduces a new variant
class to teach the btver scheduling model (x86 target) how to correctly compute
the latency profile for some zero-idioms using the new scheduling predicates.

The new methods added by this patch would be mainly used by llc when flag
-print-schedule is specified. In particular, tests that contain inline assembly
require that code is parsed at code emission stage into a sequence of MCInst.
That forces the print-schedule functionality to query the latency/rthroughput
information for MCInst instructions too. If we don't expose this new API, then
we lose "-print-schedule" test coverage as soon as variant scheduling classes
are added to the x86 models.

The tablegen SubtargetEmitter changes teaches how to query latency profile
information using a object that derives from TargetSubtargetInfo. Note that this
should really have been part of r333286. To avoid code duplication, the logic
that "resolves" variant scheduling classes for MCInst, has been moved to a
common place in MC. That logic is used by the "resolveVariantSchedClass" methods
redefined in override by the tablegen'd GenSubtargetInfo classes.

Differential Revision: https://reviews.llvm.org/D47536


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333650 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 13:30:42 +00:00
Roman Tereshin
12dc03238a [GlobalISel][Legalizer] LegalizerInfo verifier: Making LegalizerInfo::verify(...) errors fatal
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333619 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 01:56:07 +00:00
Roman Tereshin
fd6d60ff75 [GlobalISel][Legalizer] LegalizerInfo verifier: check rules cover type indices
This commit adds a simple verifier that tracks type indices being
touched by legalization rules' builders.

Every target will now have an opportunity to call
LegalizerInfo::verify(...) at the end of its derived LegalizerInfo's
constructor and check there are no obvious mistakes like checking only
first type for an opcode that has more than one type index and therefore
implicitly declaring any type for the second (and higher) type index
legal.

The check is only ran in assert builds and should have very minor
performance impact in assert builds and none in release builds.

This commit does not add LegalizerInfo::verify(...) calls to
target-specific legalizers, look for separate commits for that.

This commit also doesn't make the verification errors fatal, only
produces an error message, look for a later commit that does.

Reviewers: aemerson, qcolombet

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D46338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333576 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 18:45:32 +00:00
Matt Arsenault
fec5a579e7 DAG: Remove redundant version of getRegisterTypeForCallingConv
There seems to be no real reason to have these separate copies.
The existing implementations just copy each other for x86.
For Mips there is a subtle difference, which is just a bug
since it changes based on the context where which one was called.
Dropping this version, all tests pass. If I try to merge them
to match the removed version, a test fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333440 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 17:42:26 +00:00
Cameron McInally
f5982f4773 [StrictFP] Make getStrictFPOpcodeAction(...) more accessible
NFCI. This function will be reused in upcoming patches.

Differential Revision: https://reviews.llvm.org/D47380



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333433 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 16:49:32 +00:00
Than McIntosh
6fa6453210 StackColoring: better handling of statically unreachable code
Summary:
Avoid assert/crash during liveness calculation in situations
where the incoming machine function has statically unreachable BBs.
Second attempt at submitting; this version of the change includes
a revised testcase.

Fixes PR37130.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47372

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333416 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 13:52:24 +00:00
Guozhi Wei
192d09bc6e [CodeGenPrepare] Revert r331783
The patch r331783 caused regression in one of our internal application. So revert it now, will investigate it further.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333305 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-25 20:30:26 +00:00
Jonas Paulsson
cc53486e92 [RegUsageInfoCollector] Bugfix for callee saved registers.
Previously, this pass would look at the (static) set returned by
getCallPreservedMask() and add those back as preserved in the case when
isSafeForNoCSROpt() returns false.

A problem is that a target may have to save some registers even when NoCSROpt
takes place. For instance, on SystemZ, the return register is needed upon
return from a function.

Furthermore, getCallPreservedMask() only includes the registers that the
target actually wishes to emit save/restore instructions for. This means that
subregs and (fully saved) superregs are missing.

This patch instead takes the (dynamic) set returned by target for the
function from determineCalleeSaves() and then adds sub/super regs to build
the set to be used when building the RegMask for the function.

Review: Quentin Colombet, Ulrich Weigand
https://reviews.llvm.org/D46315

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333261 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-25 08:42:02 +00:00
Vedant Kumar
fca4ed2fcf [DebugInfo] Maintain DI when converting GEP to bitcast
When a GEP with all zero indices is converted to bitcast, its DI wasn't
copied over to the newly created instruction. This patch fixes that bug.

Patch by Kareem Ergawy!

Differential Revision: https://reviews.llvm.org/D47347

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2018-05-24 23:00:21 +00:00
Jonas Paulsson
4a65e92703 [ScheduleDAGInstrs / buildSchedGraph] Clear subregister entries also.
In addPhysRegDeps, subregister entries of the defined register were previously
not removed from Uses or Defs, which resulted in extra redundant edges for
subregs around the register definition.

This is principally NFC (in very rare cases some node got a different height).

This makes the DAG more readable and efficient in some cases.

Review: Andy Trick
https://reviews.llvm.org/D46838

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2018-05-24 08:38:06 +00:00
Vedant Kumar
4e24f46cfd [DebugInfo] Maintain DI for sunken bitcasts
When a bitcast is being sunk in -codegenprepare pass, its DI wasn't
copied over to the newly created instruction. This patch fixes that
bug.

Patch by Kareem Ergawy!

Differential Revision: https://reviews.llvm.org/D47282

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2018-05-23 22:03:48 +00:00
Roman Tereshin
cb64cbca1c [GlobalISel] NFCI, Getting GlobalISel ~5% faster
by replacing DenseMap with IndexedMap for LLTs within MRI, as
benchmarked by cross-compiling sqlite3 amalgamation for AArch64
on x86 machine.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46809

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2018-05-23 21:12:02 +00:00
Heejin Ahn
a3ccaa9b88 [WebAssembly] Add functions for EHScopes
Summary:
There are functions using the term 'funclet' to refer to both
1. an EH scopes, the structure of BBs that starts with
catchpad/cleanuppad and ends with catchret/cleanupret, and
2. a small function that gets outlined in AsmPrinter, which is the
original meaning of 'funclet'.

So far the two have been the same thing; EH scopes are always outlined
in AsmPrinter as funclets at the end of the compilation pipeline. But
now wasm also uses scope-based EH but does not outline those, so we now
need to correctly distinguish those two use cases in functions.

This patch splits `MachineBasicBlock::isFuncletEntry` into
`isFuncletEntry` and `isEHScopeEntry`, and
`MachineFunction::hasFunclets` into `hasFunclets` and `hasEHScopes`, in
order to distinguish the two different use cases. And this also changes
some uses of the term 'funclet' to 'scope' in `getFuncletMembership` and
change the function name to `getEHScopeMembership` because this function
is not about outlined funclets but about EH scope memberships.

This change is in the same vein as D45559.

Reviewers: majnemer, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D47005

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2018-05-23 00:32:46 +00:00
Eli Friedman
73026bde12 [MachineOutliner] Add "thunk" outlining for AArch64.
When we're outlining a sequence that ends in a call, we can save up to
three instructions in the outlined function by turning the call into
a tail-call. I refer to this as thunk outlining because the resulting
outlined function looks like a thunk; suggestions welcome for a better
name.

In addition to making the outlined function shorter, thunk outlining
allows outlining calls which would otherwise be illegal to outline:
we don't need to save/restore LR, so we don't need to prove anything
about the stack access patterns of the callee.

To make this work effectively, I also added
MachineOutlinerInstrType::LegalTerminator to the generic MachineOutliner
code; this allows treating an arbitrary instruction as a terminator in
the suffix tree.

Differential Revision: https://reviews.llvm.org/D47173



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2018-05-22 19:11:06 +00:00
Paul Robinson
04a387aa0f [DWARFv5] Put the DWO ID in its place.
In DWARF v5, the DWO ID is in the (split/skeleton) CU header, not an
attribute on the CU DIE.

This changes the size of those headers, so use the parsed size whenever
we have one, for simplicitly.

Differential Revision: https://reviews.llvm.org/D47158

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2018-05-22 17:27:31 +00:00
Sanjay Patel
2f6b67546d [DAG] fold FP binops with undef operands to NaN
This is the FP sibling of D43141 with the corresponding IR change in rL327212.

We can't propagate undef here because if a variable operand is a NaN, these 
binops must propagate NaN. Neither global nor node-level fast-math makes a 
difference. If we have 'nnan', I think later folds can turn the NaN into undef.

The tests in X86/fp-undef.ll are meant to be the definitive verification for 
these folds - everything reduces identically now.

The other test changes are collateral damage. They may need to be altered to
preserve their intent.

Differential Revision: https://reviews.llvm.org/D47026



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2018-05-21 23:54:19 +00:00
Roman Lebedev
6a15b1928a [DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): look through bitcasts
Summary:
As pointed out in D46528, we errneously transform cases like `xor X, -1`,
even though we use said function.
It's because the `-1` is actually a bitcast there.
So i think we can just look through it in the function.

Differential Revision: https://reviews.llvm.org/D47156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332905 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 21:41:10 +00:00