24703 Commits

Author SHA1 Message Date
Puyan Lotfi
f1f8a6d536 [MIR-Canon] Adding ISA-Agnostic COPY Folding.
Transforms the following:

    %vreg1234:gpr32 = COPY %42
    %vreg1235:gpr32 = COPY %vreg1234
    %vreg1236:gpr32 = COPY %vreg1235
    $w0 = COPY %vreg1236

into:

    $w0 = COPY %42

Assuming %42 is also a gpr32



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330113 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-16 09:03:03 +00:00
Puyan Lotfi
388ad3d2f7 [NFC][MIR-Canon] clang-format cleanup of Mir Canonicalizer Pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330111 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-16 08:12:15 +00:00
Craig Topper
445c7b1daf [X86] Use APInt::isSubsetof instead of APInt::intersects to avoid a negation of an APInt value. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330105 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-15 19:11:25 +00:00
Roman Lebedev
6b8ddb4596 [SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notes
As suggested in https://reviews.llvm.org/D45631#1068338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330102 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-15 18:59:38 +00:00
Andrea Di Biagio
b5e23d13a5 [MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.
TargetSchedModel now always delegates to MCSchedModel the computation of
instruction latency and reciprocal throughput.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330099 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-15 17:32:17 +00:00
Sanjay Patel
8a7e3a43d6 [DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y) with multiple uses
This is a transform that I limited in instcombine in rL329821 because it was 
creating more instructions in IR when the cast has multiple uses.

But if the cast is free, then we can do the transform regardless of other
uses because it improves the potential throughput of the calculation by
removing a dependency on the fneg.

Differential Revision: https://reviews.llvm.org/D45598


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330098 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-15 16:43:48 +00:00
Jun Bum Lim
13bac7c13d [PostRASink]Add register dependency check for implicit operands
Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.

Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB

Reviewed By: thegameg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330018 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-13 14:23:09 +00:00
Hiroshi Inoue
7dc3d5f99a [NFC] fix trivial typos in comments
"the the" -> "the", "we we" -> "we", etc



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-13 11:37:06 +00:00
Sanjay Patel
c2943f0710 [DAGCombiner] simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329964 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 22:14:58 +00:00
Sanjay Patel
b7ab0ed219 revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329920 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 15:27:01 +00:00
Krzysztof Parzyszek
f0086dd6e3 [Pipeliner] Use std::stable_sort when ordering NodeSets
There are cases when individual NodeSets can be equal with respect to
the ordering criteria. Since they are stored in an ordered container,
use stable_sort to preserve the relative order of equal NodeSets. 

This should remove non-determinism discovered by shuffling done in
llvm::sort with expensive checks enabled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329915 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 15:11:11 +00:00
Francis Visoiu Mistrih
224d082089 [CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper
Don't assume SelectionDAG is non-null as the targets can use it with a
null pointer.

Differential Revision: https://reviews.llvm.org/D44611

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329908 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 12:59:50 +00:00
Jonas Paulsson
a83aa7ca2e [MachineScheduler] NFC refactoring
This patch makes tryCandidate() virtual and some utility functions like
tryLess(), tryGreater(), ... externally available (used to be static).

This makes it possible for a target to derive a new MachineSchedStrategy from
GenericScheduler and reuse most parts.

It was necessary to wrap functions with the same names in
AMDGPU/SIMachineScheduler in a local namespace.

Review: Andy Trick, Florian Hahn
https://reviews.llvm.org/D43329

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329884 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 07:21:39 +00:00
Craig Topper
47d409e1ca [LegalizeTypes] Remove unnecessary type action check on the type of operand 0 when promoting shift result type. NFC
Operand 0 should have the same type of the result. So if the result type needs to be promoted, operand 0 needs to be promoted unconditionally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329883 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 06:51:58 +00:00
Hiroshi Inoue
ef1bc2d3ca [NFC] fix trivial typos in documents and comments
"is is" -> "is", "if if" -> "if", "or or" -> "or"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329878 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 05:53:20 +00:00
Peter Collingbourne
2b8ec282c2 CodeGen: Don't try to canonicalize Unix-style paths in CodeView debug info.
Most importantly, we should not replace slashes with backslashes
because that would invalidate the path.

Differential Revision: https://reviews.llvm.org/D45473

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329838 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-11 18:24:03 +00:00
Reid Kleckner
1a785071aa [FastISel] Disable local value sinking by default
This is causing compilation timeouts on code with long sequences of
local values and calls (i.e. foo(1); foo(2); foo(3); ...).  It turns out
that code coverage instrumentation is a great way to create sequences
like this, which how our users ran into the issue in practice.

Intel has a tool that detects these kinds of non-linear compile time
issues, and Andy Kaylor reported it as PR37010.

The current sinking code scans the whole basic block once per local
value sink, which happens before emitting each call. In theory, local
values should only be introduced to be used by instructions between the
current flush point and the last flush point, so we should only need to
scan those instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329822 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-11 16:03:07 +00:00
Steven Wu
bba7686b46 [MachO] Emit Weak ReadOnlyWithRel to ConstDataSection
Summary:
Darwin dynamic linker can handle weak symbols in ConstDataSection.
ReadonReadOnlyWithRel symbols should be emitted in ConstDataSection
instead of normal DataSection.

rdar://problem/39298457

Reviewers: dexonsmith, kledzik

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329752 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-10 20:16:35 +00:00
Krzysztof Parzyszek
b8924a00e7 [CodeGen] Fix printing bundles in MIR output
Delay printing the newline until after the opening bracket was
printed, e.g.
  BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 {
    renamable $r1 = S2_asr_i_r renamable $r1, 1
    renamable $r21 = A2_tfrsi 0
  }
instead of
  BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1
 {    renamable $r1 = S2_asr_i_r renamable $r1, 1
    renamable $r21 = A2_tfrsi 0
  }


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329719 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-10 16:46:13 +00:00
Pavel Labath
e6ac37f218 [CodeGen/Dwarf] Rename the "sizetype" synthetic type and add it to the accelerator table
Summary:
This type is created on-demand and used as the base type for array
ranges. Since it is "special", its construction did not go through the
createTypeDIE function and so it was never inserted into the accelerator
table, although it clearly belongs there.

I add an explicit addAccelType call to insert it into the table.

During review, we also decided to rename the type to something more
unique to avoid confusion in case the user has own "sizetype" type. The
new name for the type size __ARRAY_SIZE_TYPE__.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329705 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-10 14:23:41 +00:00
Chandler Carruth
21a0c18174 [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues.
The key idea is to lower COPY nodes populating EFLAGS by scanning the
uses of EFLAGS and introducing dedicated code to preserve the necessary
state in a GPR. In the vast majority of cases, these uses are cmovCC and
jCC instructions. For such cases, we can very easily save and restore
the necessary information by simply inserting a setCC into a GPR where
the original flags are live, and then testing that GPR directly to feed
the cmov or conditional branch.

However, things are a bit more tricky if arithmetic is using the flags.
This patch handles the vast majority of cases that seem to come up in
practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of
partially preserved EFLAGS as LLVM doesn't currently model that at all.

There are a large number of operations that techinaclly observe EFLAGS
currently but shouldn't in this case -- they typically are using DF.
Currently, they will not be handled by this approach. However, I have
never seen this issue come up in practice. It is already pretty rare to
have these patterns come up in practical code with LLVM. I had to resort
to writing MIR tests to cover most of the logic in this pass already.
I suspect even with its current amount of coverage of arithmetic users
of EFLAGS it will be a significant improvement over the current use of
pushf/popf. It will also produce substantially faster code in most of
the common patterns.

This patch also removes all of the old lowering for EFLAGS copies, and
the hack that forced us to use a frame pointer when EFLAGS copies were
found anywhere in a function so that the dynamic stack adjustment wasn't
a problem. None of this is needed as we now lower all of these copies
directly in MI and without require stack adjustments.

Lots of thanks to Reid who came up with several aspects of this
approach, and Craig who helped me work out a couple of things tripping
me up while working on this.

Differential Revision: https://reviews.llvm.org/D45146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329657 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-10 01:41:17 +00:00
Daniel Sanders
0b943e2bc4 [globalisel][legalizerinfo] Add support for the Lower action in getActionDefinitionsBuilder() and use it in AArch64.
Lower is slightly odd. It often doesn't change the type but the lowerings
do use the new type to decide what code to create. Treat it like a mutation
but provide convenience functions that re-use the existing type.

Re-uses the existing tests:
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
test/CodeGen/AArch64/GlobalISel//legalize-mul.mir
test/CodeGen/AArch64/GlobalISel//legalize-cmpxchg-with-success.mir


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329623 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 21:10:09 +00:00
Matt Arsenault
4668d9f5c1 Fix printing of stack id in MachineFrameInfo
uint8_t is printed as a char, so it needs to be
casted to do the right thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329622 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 21:04:30 +00:00
Alexandre Ganea
2031cf6be1 [Debuginfo][COFF] Minimal serialization support for precompiled types records
This change adds support for the LF_PRECOMP and LF_ENDPRECOMP records required
to read/write Microsoft precompiled types .objs.
See https://en.wikipedia.org/wiki/Precompiled_header#Microsoft_Visual_C_and_C++

This also adds handling for the .debug$P section, which is actually a .debug$T
section in disguise, found only in precompiled .objs.

Differential Revision: https://reviews.llvm.org/D45283

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329613 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 20:17:56 +00:00
Daniel Sanders
0e32281b0c Fix type mismatch between MachineMemOperand constructor and accessors. NFC
This allows MachineMemOperand::getSize()'s result to be fed directly into 
MachineMemOperand::MachineMemOperand() without a narrowing type conversion
warning.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329602 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 18:42:19 +00:00
Aditya Nandakumar
b9f22e8394 [GISel] Refactor MachineIRBuilder to allow transformations while
building.

https://reviews.llvm.org/D45067

This change attempts to do two things:
1) It separates out the state that is stored in the
MachineIRBuilder(InsertionPt, MF, MRI, InsertFunction etc) into a
separate object called MachineIRBuilderState.
2) Add the ability to constant fold operations while building instructions
(optionally). MachineIRBuilder is now refactored into a MachineIRBuilderBase
which contains lots of non foldable build methods and their implementation.
Instructions which can be constant folded/transformed are now in a class
called FoldableInstructionBuilder which uses CRTP to use the implementation
of the derived class for buildBinaryOps. Additionally buildInstr in the derived
class can be used to implement other kinds of transformations.

Also because of separation of state, given a MachineIRBuilder in an API,
if one wishes to use another MachineIRBuilder, a new one can be
constructed from the state locally. For eg,

void doFoo(MachineIRBuilder &B) {
  MyCustomBuilder CustomB(B.getState());
  // Use CustomB for building.
}

reviewed by : aemerson

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329596 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 17:30:56 +00:00
Simon Pilgrim
767f692c45 Support generic expansion of ordered vector reduction (PR36732)
Without the fast math flags, the llvm.experimental.vector.reduce.fadd/fmul intrinsic expansions must be expanded in order.

This patch scalarizes the reduction, applying the accumulator at the start of the sequence: ((((Acc + Scl[0]) + Scl[1]) + Scl[2]) + ) ... + Scl[NumElts-1]

Differential Revision: https://reviews.llvm.org/D45366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329585 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 15:44:20 +00:00
Zaara Syeda
dbec9f78b1 [MachineLICM] Re-enable hoisting of constant stores
This patch fixes an issue exposed on the SystemZ build bots when committing
https://reviews.llvm.org/rL327856. The hoisting was temporarily disabled with
an option. This patch now re-enables hoisting and checks that we only hoist a
store instruction when all its operands are either constant caller preserved
registers or immediates.

Differential Revision: https://reviews.llvm.org/D45286

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329577 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 14:50:02 +00:00
Pavel Labath
62bde38843 [CodeGen/AccelTable] Don't emit zero-CU name indexes
Summary:
If an input DICompileUnit is completely empty (e.g., the result of
running "clang -g" on an empty file), we don't bother emitting an empty
DWARF CU. When we do that, we must make sure we don't also emit a DWARF v5
name index, as DWARF specifies that each index must reference at least
one compilation unit.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45435

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329575 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 14:38:53 +00:00
Pavel Labath
099f934b4f [CodeGen/AccelTable]: Don't emit accelerator entries for functions with no names
Summary:
We were emitting accelerator entries for functions with no name, which
is contrary to the DWARF v5 spec: "All other (i.e., *not*
DW_TAG_namespace) debugging information entries without a DW_AT_name
attribute are excluded." Besides that, a name table entry with an empty
string as a key is fairly useless.

We can sometimes end up with functions which have a DW_AT_linkage_name but no
DW_AT_name. One such example is the global-constructor-initialization functions,
which C++ compilers synthesize for each compilation unit with global
constructors.
A very strict reading of the DWARF v5 spec would suggest that we should not even
emit the accelerator entry for the linkage name in this case, but I don't think
we should go that far.

I found this when running the dwarf verifier over llvm codebase compiled
with DWARF v5 accelerator tables.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: vleschuk, clayborg, echristo, probinson, llvm-commits

Differential Revision: https://reviews.llvm.org/D45367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329552 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 08:41:57 +00:00
Sam Parker
3757f28f1d [DAGCombine] Improve ReduceLoad for SRL
Recommitting r329283, third time lucky...

If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.

Differential Revision: https://reviews.llvm.org/D41350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329551 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 08:16:11 +00:00
Michael Zolotukhin
f65fa6681f Remove MachineLoopInfo dependency from AsmPrinter.
Summary:
Currently MachineLoopInfo is used in only two places:
1) for computing IsBasicBlockInsideInnermostLoop field of MCCodePaddingContext, and it is never used.
2) in emitBasicBlockLoopComments, which is called only if `isVerbose()` is true.
Despite that, we currently have a dependency on MachineLoopInfo, which makes
pass manager to compute it and MachineDominator Tree. This patch removes the
use (1) and makes the use (2) lazy, thus avoiding some redundant
recomputations.

Reviewers: opaparo, gadi.haber, rafael, craig.topper, zvi

Subscribers: rengolin, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D44812

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329542 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-09 00:54:47 +00:00
Sanjay Patel
e599ceafb8 [TargetSchedule] shrink interface for init(); NFCI
The TargetSchedModel is always initialized using the TargetSubtargetInfo's 
MCSchedModel and TargetInstrInfo, so we don't need to extract those and 
pass 3 parameters to init().

Differential Revision: https://reviews.llvm.org/D44789


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329540 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-08 19:56:04 +00:00
Zvi Rackover
7ac44f2885 DAGCombiner: Combine SDIV with non-splat vector pow2 divisor
Summary:
Extend existing SDIV combine for pow2 constant divider to handle
non-splat vectors of pow2 constants.

Reviewers: RKSimon, craig.topper, spatel, hfinkel, efriedma

Reviewed By: RKSimon

Subscribers: magabari, llvm-commits

Differential Revision: https://reviews.llvm.org/D42479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329525 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-08 11:35:20 +00:00
Guozhi Wei
5c6d787053 [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))
In our real world application, we found the following optimization is missed in DAGCombiner

(zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst))

If the user of original zext is an add, it may enable further lea optimization on x86.

This patch add a new function CombineZExtLogicopShiftLoad to do this optimization.

Differential Revision: https://reviews.llvm.org/D44402



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329516 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-07 23:36:10 +00:00
Craig Topper
ae102799e0 [DAGCombiner] Add a combine to turn a build vector of zero extends of extract vector elts into a vector zero extend and possibly an extract subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329509 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-07 19:09:50 +00:00
Tim Northover
f6621a4e4b Reapply ARM: Do not spill CSR to stack on entry to noreturn functions
Should fix UBSan bot by also checking there's no "uwtable" attribute
before skipping. Otherwise the unwind table will be useless since its
moves expect CSRs to actually be preserved.

A noreturn nounwind function can be expected to never return in any way, and by
never returning it will also never have to restore any callee-saved registers
for its caller. This makes it possible to skip spills of those registers during
function entry, saving some stack space and time in the process. This is rather
useful for embedded targets with limited stack space.

Should fix PR9970.

Patch mostly by myeisha (pmb).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329494 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-07 10:57:03 +00:00
Vitaly Buka
38738ec786 Revert "ARM: Do not spill CSR to stack on entry to noreturn functions"
Breaks ubsan test TestCases/Misc/missing_return.cpp on ARM

This reverts commit r329287

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329486 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-07 05:36:44 +00:00
Matt Davis
41a887af5a [StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic.
Summary:
The 'strong' StackProtector heuristic takes into consideration call instructions.
Certain intrinsics, such as lifetime.start, can cause the
StackProtector to protect functions that do not need to be protected.

Specifically, a volatile variable, (not optimized away), but belonging to a stack
allocation will encourage a llvm.lifetime.start to be inserted during
compilation. Because that intrinsic is a 'call' the strong StackProtector
will see that the alloca'd variable is being passed to a call instruction, and
insert a stack protector. In this case the intrinsic isn't really lowered to a
call. This can cause unnecessary stack checking, at the cost of additional
(wasted) CPU cycles.

In the future we should rely on TargetTransformInfo::isLoweredToCall, but as of
now that routine considers all intrinsics as not being lowerable. That needs
to be corrected, and such a change is on my list of things to get moving on.

As a side note, the updated stack-protector-dbginfo.ll test always seems to
pass.  I never see the dbg.declare/dbg.value reaching the
StackProtector::HasAddressTaken, but I don't see any code excluding dbg
intrinsic calls either, so I think it's the safest thing to do.

Reviewers: void, timshen

Reviewed By: timshen

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329450 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-06 20:14:13 +00:00
Mandeep Singh Grang
8ba42a9352 [CodeGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, rnk, MatzeB, RKSimon

Reviewed By: rnk

Subscribers: JDevlieghere, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329435 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-06 18:08:42 +00:00
Francis Visoiu Mistrih
995c80d511 [MIR] Add support for MachineFrameInfo::LocalFrameSize
MFI.LocalFrameSize was not serialized.

It is usually set from LocalStackSlotAllocation, so if that pass doesn't
run it is impossible do deduce it from the stack objects. Until now, this
information was lost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329382 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-06 08:56:25 +00:00
Tim Northover
1444c19a6b ARM: Do not spill CSR to stack on entry to noreturn functions
A noreturn nounwind function can be expected to never return in any way, and by
never returning it will also never have to restore any callee-saved registers
for its caller. This makes it possible to skip spills of those registers during
function entry, saving some stack space and time in the process. This is rather
useful for embedded targets with limited stack space.

Should fix PR9970.

Patch by myeisha (pmb).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329287 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 14:26:06 +00:00
Sam Parker
b326c6e97a [DAGCombine] Revert r329160
Again, broke the big endian stage 2 builders.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329283 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 13:46:17 +00:00
Puyan Lotfi
1fb4289a13 [MIR-Canon] Fixing warnings in Non-assert builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329258 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 06:56:44 +00:00
Puyan Lotfi
a7f9b6aaad [MIR-Canon] Improving performance by switching to named vregs.
No more skipping thounsands of vregs. Much faster running time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329246 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 00:27:15 +00:00
Puyan Lotfi
29bc6472de [MIR-Canon] Adding support for multi-def -> user distance reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329243 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-05 00:08:15 +00:00
Jessica Paquette
7d72684477 [MachineOutliner] Add useMachineOutliner target hook
The MachineOutliner has a bunch of target hooks that will call llvm_unreachable
if the target doesn't implement them. Therefore, if you enable the outliner on
such a target, it'll just crash. It'd be much better if it'd just *not* run
the outliner at all in this case.

This commit adds a hook to TargetInstrInfo that returns false by default.
Targets that implement the hook make it return true. The outliner checks the
return value of this hook to decide whether or not to continue.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329220 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-04 19:13:31 +00:00
Pavel Labath
0e5d6b2640 Fix build breakage from r329201
Some compilers do not like having an enum type and a variable with the
same name (AccelTableKind). I rename the variable to TheAccelTableKind.

Suggestions for a better name welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329202 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-04 14:54:08 +00:00
Pavel Labath
3fb0112ac2 Re-commit r329179 after fixing build&test issues
- MSVC was not OK with a static_assert referencing a non-static member
  variable, even though it was just in a sizeof(expression). I move the
  assert into the emit function, where it is probably more useful.
- Tests were failing in builds which did not have the X86 target
  configured. Since this functionality is not target-specific, I have
  removed the target specifiers from the .ll files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329201 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-04 14:42:14 +00:00
Nico Weber
f72ca59cae Revert r329179 (and follow-up unsuccessful fix attempts 329184, 329186); it doesn't build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329190 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-04 13:06:22 +00:00