Commit Graph

186866 Commits

Author SHA1 Message Date
Roman Lebedev
b93a52f5fe [InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375378 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:52:06 +00:00
Roman Lebedev
150b0bedb7 [NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and' pat. can be 'or' pattern.
In this pattern, all the "magic" bits that we'd add are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375377 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:51:37 +00:00
GN Sync Bot
b7aa2ef391 gn build: Merge r375375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375376 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:44:56 +00:00
Vladimir Vereschaka
eec7ef7443 Reverted r375254 as it has broken some build bots for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375375 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:39:33 +00:00
Nikita Popov
e568120da3 [InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0
This adds folds for comparing uadd.sat/usub.sat with zero:

 * uadd.sat(a, b) == 0 => a == 0 && b == 0 => (a | b) == 0
 * usub.sat(a, b) == 0 => a <= b

And inverted forms for !=.

Differential Revision: https://reviews.llvm.org/D69224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375374 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:19:42 +00:00
Zinovy Nis
2b0c82a99f Fix buildbot error in SIRegisterInfo.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375373 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:01:16 +00:00
Nikita Popov
3ab0cb15c0 [InstCombine] Add tests for uadd/sub.sat(a, b) == 0; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375372 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:50:31 +00:00
Roman Lebedev
32d24a3249 [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595)
Summary:
This problem consists of several parts:
* Basic sign bit extraction - `trunc? (?shr %x, (bitwidth(x)-1))`.
  This is trivial, and easy to do, we have a fold for it.
* Shift amount reassociation - if we have two identical shifts,
  and we can simplify-add their shift amounts together,
  then we likely can just perform them as a single shift.
  But this is finicky, has one-use restrictions,
  and shift opcodes must be identical.

But there is a super-pattern where both of these work together.
to produce sign bit test from two shifts + comparison.
We do indeed already handle this in most cases.
But since we get that fold transitively, it has one-use restrictions.
And what's worse, in this case the right-shifts aren't required to be
identical, and we can't handle that transitively:

If the total shift amount is bitwidth-1, only a sign bit will remain
in the output value. But if we look at this from the perspective of
two shifts, we can't fold - we can't possibly know what bit pattern
we'd produce via two shifts, it will be *some* kind of a mask
produced from original sign bit, but we just can't tell it's shape:
https://rise4fun.com/Alive/cM0 https://rise4fun.com/Alive/9IN

But it will *only* contain sign bit and zeros.
So from the perspective of sign bit test, we're good:
https://rise4fun.com/Alive/FRz https://rise4fun.com/Alive/qBU
Superb!

So the simplest solution is to extend `reassociateShiftAmtsOfTwoSameDirectionShifts()` to also have a
sudo-analysis mode that will ignore extra-uses, and will only check
whether a) those are two right shifts and b) they end up with bitwidth(x)-1
shift amount and return either the original value that we sign-checking,
or null.

This does not have any functionality change for
the existing `reassociateShiftAmtsOfTwoSameDirectionShifts()`.

All that being said, as disscussed in the review, this yet again
increases usage of instsimplify in instcombine as utility.
Some day that may need to be reevaluated.

https://bugs.llvm.org/show_bug.cgi?id=43595

Reviewers: spatel, efriedma, vsk

Reviewed By: spatel

Subscribers: xbolva00, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68930

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375371 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:38:50 +00:00
Roman Lebedev
7bd6e166d9 [ConstantRange] makeGuaranteedNoWrapRegion(): shl support
Summary:
If all the shifts amount are already poison-producing,
then we can add more poison-producing flags ontop:
https://rise4fun.com/Alive/Ocwi

Otherwise, we should only consider the possible range of shift amts that don't result in poison.

For unsigned range not not overflow, we must not shift out any set bits,
and the actual limit for `x` can be computed by backtransforming
the maximal value we could ever get out of the `shl` - `-1` through
`lshr`. If the `x` is any larger than that then it will overflow.

Likewise for signed range, but just in signed domain..

This is based on the general idea outlined by @nikic in https://reviews.llvm.org/D68672#1714990

Reviewers: nikic, sanjoy

Reviewed By: nikic

Subscribers: hiraditya, llvm-commits, nikic

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375370 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:36:55 +00:00
Nikita Popov
467514942a [ConstantRange] Optimize nowrap region test, remove redundant tests; NFC
Enumerate one less constant range in TestNoWrapRegionExhaustive,
which was unnecessary. This allows us to bump the bit count from
3 to 5 while keeping reasonable timing.

Drop four tests for multiply nowrap regions, as these cover subsets
of the exhaustive test. They do use a wider bitwidth, but I don't
think it's worthwhile to have them additionally now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375369 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 18:59:14 +00:00
Matt Arsenault
2df5f8ca5d AMDGPU: Increase vcc liveness scan threshold
Avoids a test regression in a future patch. Also add debug printing on
this case, so I waste less time debugging folds in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375367 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 17:44:17 +00:00
Matt Arsenault
f154896069 AMDGPU: Split flat offsets that don't fit in DAG
We handle it this way for some other address spaces.

Since r349196, SILoadStoreOptimizer has been trying to do this. This
is after SIFoldOperands runs, which can change the addressing
patterns. It's simpler to just split this earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375366 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 17:34:44 +00:00
Matt Arsenault
d8b4d6f7e1 AMDGPU: Fix missing OPERAND_IMMEDIATE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375365 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:56:10 +00:00
Matt Arsenault
2f75f81688 AMDGPU: Add baseline tests for flat offset splitting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375364 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:33:21 +00:00
Matt Arsenault
01d98c6ec5 AMDGPU: Don't re-get the subtarget
It's already available in the class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375363 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:26:26 +00:00
George Rimar
38d4353156 [yaml2obj][obj2yaml] - Do not create a symbol table by default.
This patch tries to resolve problems faced in D68943
and uses some of the code written by Konrad Wilhelm Kleine
in that patch.

Previously, yaml2obj tool always created a .symtab section.
This patch changes that. With it we only create it when
have a "Symbols:" tag in the YAML document or when
we need to create it because it is used by another section(s).

obj2yaml follows the new behavior and does not print "Symbols:"
anymore when there is no symbol table.

Differential revision: https://reviews.llvm.org/D69041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375361 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 14:47:17 +00:00
Zinovy Nis
9873f72649 Fix minor warning in DWARFVerifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375357 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 07:55:50 +00:00
Matt Arsenault
b0113baebf AMDGPU: Don't error on calls to null or undef
Calls to constants should probably be generally handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375356 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 07:46:04 +00:00
Philip Reames
c624032000 [SCEV] Simplify umin/max of zext and sext of the same value
This is a common idiom which arises after induction variables are widened, and we have two or more exit conditions.  Interestingly, we don't have instcombine or instsimplify support for this either.

Differential Revision: https://reviews.llvm.org/D69006



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375349 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 17:23:02 +00:00
Simon Pilgrim
f7d6a8bc69 [X86] Pulled out helper to decode target shuffle element sentinel values to 'Zeroable' known undef/zero bits. NFCI.
Renamed 'resolveTargetShuffleAndZeroables' to 'resolveTargetShuffleFromZeroables' to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375348 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:58:24 +00:00
Sanjay Patel
0d04cbb578 [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)
Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling
codegen improvements on targets with no multiple shift instructions and cheap selects
or branches.

Contributes to a Fix for PR43559:
https://bugs.llvm.org/show_bug.cgi?id=43559

Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375347 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:57:02 +00:00
Nemanja Ivanovic
3166412328 [ARM] Add dependency on GlobalISel for unit tests to fix shared libs build
The unit test uses GlobalISel but the dependency is not listed in the
CMakeLists.txt file which causes failures in shared libs build with GCC.

This just adds the dependency.

Differential revision: https://reviews.llvm.org/D69064


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375346 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:40:26 +00:00
Sanjay Patel
896dde46ee [MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69099

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375345 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:29:32 +00:00
Simon Pilgrim
200d59f918 [X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack args
tryToWidenViaDuplication lowers using the shuffle_v8i16(unpack_v16i8(shuffle_v8i16(x),shuffle_v8i16(x))) pattern, but the unpack only needs the even/odd 16i8 args if the original v16i8 shuffle mask references the even/odd elements - which isn't true for many extension style shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375342 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 13:18:02 +00:00
Simon Pilgrim
39580be1ee [X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops
We were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea.

Differential Revision: https://reviews.llvm.org/D69175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375341 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 11:53:48 +00:00
Sylvestre Ledru
0b2777c548 Explicit in the doc the current list of projects (with easy copy and paste)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375339 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 09:55:24 +00:00
Sylvestre Ledru
f878e5cae9 Make it clear in the doc that 'all' in LLVM_ENABLE_PROJECTS does install ALL projects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375337 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 09:27:14 +00:00
Reid Kleckner
8ed36b6cc7 Avoid including CodeView/SymbolRecord.h from MCStreamer.h
Move the types needed out so they can be forward declared instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375325 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:44:09 +00:00
Matt Arsenault
e9835c0f31 AMDGPU: Remove optnone from a test
It's not clear why the test had this. I'm unable to break the original
case with the original patch reverted with or without optnone.

This avoids a failure in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375321 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:34:59 +00:00
Reid Kleckner
a83ebc9d3b Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
Now X86ISelLowering doesn't depend on many IR analyses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375320 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:31:09 +00:00
Reid Kleckner
c4185e8c3c Prune Analysis includes from SelectionDAG.h
Only forward declarations are needed here. Follow-on to r375311.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375319 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:07:48 +00:00
Reid Kleckner
d4448b8ece Move endian constant from Host.h to SwapByteOrder.h, prune include
Works on this dependency chain:
  ArrayRef.h ->
  Hashing.h -> --CUT--
  Host.h ->
  StringMap.h / StringRef.h

ArrayRef is very popular, but Host.h is rarely needed. Move the
IsBigEndianHost constant to SwapByteOrder.h. Clients of that header are
more likely to need it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375316 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 00:48:11 +00:00
Reid Kleckner
ccf0b77ef9 Prune two MachineInstr.h includes, fix up deps
MachineInstr.h included AliasAnalysis.h, which includes a world of IR
constructs mostly unneeded in CodeGen. Prune it. Same for
DebugInfoMetadata.h.

Noticed with -ftime-trace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375311 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 00:22:07 +00:00
Matt Arsenault
8672594561 LiveIntervals: Fix handleMoveUp with subreg def moving across a def
If a subregister def was moved across another subregister def and
another use, the main range was not correctly updated. The end point
of the moved interval ended too early and missed the use from theh
other lanes in the subreg def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375300 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 23:24:25 +00:00
Peter Collingbourne
f6288975c0 gn build: Build compiler-rt code with -fvisibility=hidden.
This matches the CMake build.

Differential Revision: https://reviews.llvm.org/D69202

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375299 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 22:52:17 +00:00
Stanislav Mekhanoshin
6cfc726a65 [AMDGPU] move PHI nodes to AGPR class
If all uses of a PHI are in AGPR register class we should
avoid unneeded copies via VGPRs.

Differential Revision: https://reviews.llvm.org/D69200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375297 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 22:48:45 +00:00
Wei Mi
762a6a2124 [SampleFDO] Add profile remapping support for profile on-demand loading used
by ExtBinary format profile

Profile on-demand loading was added for ExtBinary format profile in rL374233,
but currently profile on-demand loading doesn't work well with profile
remapping. The patch adds the support.

Suppose a function in the current module has outline instance in the profile.
The function name in the module is different from the name of the outline
instance, but remapper knows the two names are equal. When loading profile
on-demand, the outline instance has to be loaded with remapper's help.

At the same time SampleProfileReaderItaniumRemapper is changed from a proxy
of SampleProfileReader to a helper member in SampleProfileReader.

Differential Revision: https://reviews.llvm.org/D68901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375295 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 22:35:20 +00:00
Jay Foad
1e88075ba3 [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
Summary: The implementation was never completed and never used except in tests.

Reviewers: arsenm, mareko

Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375293 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 21:48:22 +00:00
Roman Lebedev
e3de752ca5 [CVP] setDeducedOverflowingFlags(): actually inc per-opcode stats
This is really embarrassing. Those are pointers, so that offsets the
pointers, not the statistics pointed-by the pointer...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375290 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 21:19:26 +00:00
GN Sync Bot
c3ec070fae gn build: Merge r375288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375289 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 21:11:20 +00:00
Vedant Kumar
fa78819405 Disable exit-on-SIGPIPE in lldb
Occasionally, during test teardown, LLDB writes to a closed pipe.
Sometimes the communication is inherently unreliable, so LLDB tries to
avoid being killed due to SIGPIPE (it calls `signal(SIGPIPE, SIG_IGN)`).
However, LLVM's default SIGPIPE behavior overrides LLDB's, causing it to
exit with IO_ERR.

Opt LLDB out of the default SIGPIPE behavior. I expect that this will
resolve some LLDB test suite flakiness (tests randomly failing with
IO_ERR) that we've seen since r344372.

rdar://55750240

Differential Revision: https://reviews.llvm.org/D69148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375288 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 21:05:30 +00:00
Reid Kleckner
88cdc6927e [X86] Fix register parsing in .seh_* in Intel syntax
Previously, the parser checked for a '%' prefix to indicate a register.
In Intel syntax mode, LLVM does not print a '%' prefix on registers, so
LLVM could not parse its own assembly output. Instead, require that
register numbers be integer literals, or at least start with an integer
literal, which is consistent with .cfi_* directive register parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375287 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 21:01:41 +00:00
Roman Lebedev
a82e2a53ab [NFC][CVP] Some tests for mul no-wrap deduction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375285 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 20:36:19 +00:00
Thomas Lively
523325a26c [WebAssembly] Allow multivalue signatures in object files
Summary:
Also changes the wasm YAML format to reflect the possibility of having
multiple return types and to put the returns after the params for
consistency with the binary encoding.

Reviewers: aheejin, sbc100

Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, arphaman, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375283 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 20:27:30 +00:00
Quentin Colombet
8df88e8ad7 [GISel][CallLowering] Make isIncomingArgumentHandler a pure virtual method
The default implementation of isIncomingArgumentHandler could lead
to generating incorrect code.
Make it a pure virtual method, so that targets know they have to
override it to produce correct code.

NFC

Differential Revision: https://reviews.llvm.org/D69187

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375277 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 20:13:42 +00:00
Roman Lebedev
e1659b963e [CVP] After proving that @llvm.with.overflow()/@llvm.sat() don't overflow, also try to prove other no-wrap
Summary:
CVP, unlike InstCombine, does not run till exaustion.
It only does a single pass.

When dealing with those special binops, if we prove that they can
safely be demoted into their usual binop form,
we do set the no-wrap we deduced. But when dealing with usual binops,
we try to deduce both no-wraps.

So if we convert e.g. @llvm.uadd.with.overflow() to `add nuw`,
we won't attempt to check whether it can be `add nuw nsw`.

This patch proposes to call `processBinOp()` on newly-created binop,
which is identical to what we do for div/rem already.

Reviewers: nikic, spatel, reames

Reviewed By: nikic

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69183

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375273 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 19:32:47 +00:00
Lang Hames
4e1c632114 [examples] Fix some comments in the LLJITWithJITLink example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375269 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 18:35:02 +00:00
Matt Arsenault
7d97468a23 AMDGPU: Relax 32-bit SGPR register class
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.

For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375267 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 18:26:37 +00:00
Lang Hames
90696971b2 [examples] Add an example of how to use JITLink and small-code-model with LLJIT.
JITLink is LLVM's newer jit-linker. It is an alternative to (and hopefully
eventually a replacement for) LLVM's older jit-linker, RuntimeDyld. Unlike
RuntimeDyld which requries JIT'd code to be complied with the large code
model, JITlink can link code compiled with the small code model, which is
the native code model for a number of targets (including all supported MachO
targets).

This example shows how to:

-- Create a JITLink InProcessMemoryManager
-- Set the code model to small
-- Use a JITLink backed ObjectLinkingLayer as the linking layer for LLJIT
   (rather than the default RTDyldObjectLinkingLayer).

Note: This example will only work on platforms supported by JITLink. As of
this commit that's MachO/x86-64 and MachO/arm64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375266 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 18:25:15 +00:00
Austin Kerbow
0a8dc0861b AMDGPU: Fix SMEM WAR hazard for gfx10 readlane
Summary: Hazard recognizer fails to see hazard with V_READLANE_B32_gfx10.

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69172

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375265 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 18:20:30 +00:00