Commit Graph

388 Commits

Author SHA1 Message Date
Craig Topper f38b0f184c [X86] Add FPCW as an implicit use on floating point load instructions.
These instructions can generate a stack overflow exception so technically they read the stack overflow exception mask bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353564 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 20:50:09 +00:00
Craig Topper 5e75b645f6 [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions.
Summary:
FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence.

This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529.

Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor

Subscribers: dim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57735

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353489 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 00:44:39 +00:00
Matt Arsenault ab8dc6c3bd MIR: Validate LLT types when parsing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353107 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-04 22:59:56 +00:00
Matt Arsenault 714cc866c2 MIR: Reject non-power-of-4 alignments in MMO parsing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352686 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-30 23:09:28 +00:00
Matt Arsenault 50de4990f0 GlobalISel: Verify load/store has a pointer input
I expected this to be automatically verified, but it seems
nothing uses that the type index was declared as a "ptype"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352319 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-27 15:57:23 +00:00
Amara Emerson 171d728596 Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""
I reverted it originally due to a bot failing. The underlying bug has been fixed
as of r352311.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352312 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-27 11:34:41 +00:00
Amara Emerson b3cf54ea95 Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"
This new assertion triggered on the AArch64 GlobalISel bots. Reverting while it's being investigated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351617 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-19 00:36:11 +00:00
Matt Arsenault 04c7d10f65 GlobalISel: Verify g_zextload and g_sextload
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351584 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-18 20:17:37 +00:00
Luke Cheeseman b48bc9992e [Dwarf/AArch64] Return address signing B key dwarf support
- When signing return addresses with -msign-return-address=<scope>{+<key>},
  either the A key instructions or the B key instructions can be used. To
  correctly authenticate the return address, the unwinder/debugger must know
  which key was used to sign the return address.
- When and exception is thrown or a break point reached, it may be necessary to
  unwind the stack. To accomplish this, the unwinder/debugger must be able to
  first authenticate an the return address if it has been signed.
- To enable this, the augmentation string of CIEs has been extended to allow
  inclusion of a 'B' character. Functions that are signed using the B key
  variant of the instructions should have and FDE whose associated CIE has a 'B'
  in the augmentation string.
- One must also be able to preserve these semantics when first stepping from a
  high level language into assembly and then, as a second step, into an object
  file. To achieve this, I have introduced a new assembly directive
  '.cfi_b_key_frame ', that tells the assembler the current frame uses return
  address signing with the B key.
- This ensures that the FDE is associated with a CIE that has 'B' in the
  augmentation string.

Differential Revision: https://reviews.llvm.org/D51798



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349895 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-21 10:45:08 +00:00
Luke Cheeseman a0875a91cb [AArch64] - Return address signing dwarf support
- Reapply changes intially introduced in r343089
- The archtecture info is no longer loaded whenever a DWARFContext is created
- The runtimes libraries (santiziers) make use of the dwarf context classes but
  do not intialise the target info
- The architecture of the object can be obtained without loading the target info
- Adding a method to the dwarf context to get this information and multiplex the
  string printing later on

Differential Revision: https://reviews.llvm.org/D55774



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349472 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-18 10:37:42 +00:00
Daniel Sanders a3836a558f [mir] Serialize DILocation inline when not possible to use a metadata reference
Summary:
Sometimes MIR-level passes create DILocations that were not present in the
LLVM-IR. For example, it may merge two DILocations together to produce a
DILocation that points to line 0.

Previously, the address of these DILocations were printed which prevented the
MIR from being read back into LLVM. With this patch, DILocations will use
metadata references where possible and fall back on serializing them inline like so:
    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 1, scope: !15)

Reviewers: aprantl, vsk, arphaman

Reviewed By: aprantl

Subscribers: probinson, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D55243

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349035 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 14:25:27 +00:00
Hsiangkai Wang 3c67822cb8 [CodeGen] Fix bugs in BranchFolderPass when debug labels are generated.
Skip DBG_VALUE and DBG_LABEL in branch folding algorithms.

The bug is reported in
https://bugs.chromium.org/p/chromium/issues/detail?id=898160.

Differential Revision: https://reviews.llvm.org/D54199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347964 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-30 08:07:29 +00:00
Luke Cheeseman c8ecb42041 Revert r347490 as it breaks address sanitizer builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347499 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-23 17:13:06 +00:00
Luke Cheeseman 7ef46a70af Revert r343341
- Cannot reproduce the build failure locally and the build logs have
  been deleted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347490 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-23 11:01:47 +00:00
Zaara Syeda 7bade9c965 [Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.

Differential Revision: https://reviews.llvm.org/D39386

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346512 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 16:36:24 +00:00
Daniel Sanders bcb50253e9 Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346368 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 23:33:55 +00:00
Reid Kleckner cc8a1a635b [codeview] Let the X86 backend tell us the VFRAME offset adjustment
Use MachineFrameInfo's OffsetAdjustment field to pass this information
from the target to CodeViewDebug.cpp. The X86 backend doesn't use it for
any other purpose.

This fixes PR38857 in the case where there is a non-aligned quantity of
CSRs and a non-aligned quantity of locals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346062 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-03 00:41:52 +00:00
Matthias Braun 83c015bd73 MachineOperand/MIParser: Do not print debug-use flag, infer it
The debug-use flag must be set exactly for uses on DBG_VALUEs.  This is
so obvious that it can be trivially inferred while parsing. This will
reduce noise when printing while omitting an information that has little
value to the user.

The parser will keep recognizing the flag for compatibility with old
`.mir` files.

Differential Revision: https://reviews.llvm.org/D53903

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345671 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-30 23:28:27 +00:00
Francis Visoiu Mistrih 1ba9cfd74f [MIR] Simplify and move MIR test
Also fixes a Machine Verifier issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345396 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26 16:00:29 +00:00
Reid Kleckner 6d4c271eeb [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL
Summary:
Before this change, LLVM would always describe locals on the stack as
being relative to some specific register, RSP, ESP, EBP, ESI, etc.
Variables in stack memory are pretty common, so there is a special
S_DEFRANGE_FRAMEPOINTER_REL symbol for them. This change uses it to
reduce the size of our debug info.

On top of the size savings, there are cases on 32-bit x86 where local
variables are addressed from ESP, but ESP changes across the function.
Unlike in DWARF, there is no FPO data to describe the stack adjustments
made to push arguments onto the stack and pop them off after the call,
which makes it hard for the debugger to find the local variables in
frames further up the stack.

To handle this, CodeView has a special VFRAME register, which
corresponds to the $T0 variable set by our FPO data in 32-bit.  Offsets
to local variables are instead relative to this value.

This is part of PR38857.

Reviewers: hans, zturner, javed.absar

Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D52217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343543 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:59:45 +00:00
Matthias Braun 429bce6ae9 MIRParser: Check that instructions only reference DILocation metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343505 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:50:52 +00:00
Carlos Alberto Enciso 42b5443507 [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.
When MachineCopyPropagation eliminates a dead 'copy', its associated debug information becomes invalid. as the recorded register has been removed.  It causes the debugger to display wrong variable value.

Differential Revision: https://reviews.llvm.org/D52614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343445 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 08:14:44 +00:00
Luke Cheeseman 4c6cb9f427 Revert r343317
- asan buildbots are breaking and I need to investigate the issue



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343341 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 17:01:50 +00:00
Luke Cheeseman 96f82d5c18 Reapply changes reverted by r343235
- Add fix so that all code paths that create DWARFContext
  with an ObjectFile initialise the target architecture in the context
- Add an assert that the Arch is known in the Dwarf CallFrameString method



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343317 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 13:37:27 +00:00
Luke Cheeseman 4d42c19cd1 Revert r343192 as an ubsan build is currently failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343235 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 16:47:30 +00:00
Luke Cheeseman a26da93994 Reapply changes reverted in r343114, lldb patch to follow shortly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343192 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 10:39:20 +00:00
Luke Cheeseman 9f0b248da5 Revert r343112 as CallFrameString API change has broken lldb builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343114 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 14:48:03 +00:00
Luke Cheeseman 538d8c7d85 [AArch64] - Return address signing dwarf support
- Reapply r343089 with a fix for DebugInfo/Sparc/gnu-window-save.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343112 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 14:30:29 +00:00
Hans Wennborg 21491992cf Revert r343089 "[AArch64] - Return address signing dwarf support"
This caused the DebugInfo/Sparc/gnu-window-save.ll test to fail.

> Functions that have signed return addresses need additional dwarf support:
> - After signing the LR, and before authenticating it, the LR register is in a
>   state the is unusable by a debugger or unwinder
> - To account for this a new directive, .cfi_negate_ra_state, is added
> - This directive says the signed state of the LR register has now changed,
>   i.e. unsigned -> signed or signed -> unsigned
> - This directive has the same CFA code as the SPARC directive GNU_window_save
>   (0x2d), adding a macro to account for multiply defined codes
> - This patch matches the gcc implementation of this support:
>   https://patchwork.ozlabs.org/patch/800271/
>
> Differential Revision: https://reviews.llvm.org/D50136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343103 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 12:57:45 +00:00
Luke Cheeseman e99f0eb61e [AArch64] - Return address signing dwarf support
Functions that have signed return addresses need additional dwarf support:
- After signing the LR, and before authenticating it, the LR register is in a
  state the is unusable by a debugger or unwinder
- To account for this a new directive, .cfi_negate_ra_state, is added
- This directive says the signed state of the LR register has now changed,
  i.e. unsigned -> signed or signed -> unsigned
- This directive has the same CFA code as the SPARC directive GNU_window_save
  (0x2d), adding a macro to account for multiply defined codes
- This patch matches the gcc implementation of this support:
  https://patchwork.ozlabs.org/patch/800271/

Differential Revision: https://reviews.llvm.org/D50136



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343089 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 10:14:15 +00:00
Michael Berg 87d1f822bf add IR flags to MI
Summary: Initial support for nsw, nuw and exact flags in MI

Reviewers: spatel, hfinkel, wristow

Reviewed By: spatel

Subscribers: nlopes

Differential Revision: https://reviews.llvm.org/D51738

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341996 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-11 21:35:32 +00:00
Matt Arsenault 7c299a76cf AMDGPU: Fix tests using old number for constant address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341770 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-10 02:54:25 +00:00
Michael Berg 6dc9199bec [NFC] - in preparation for adding nsw, nuw and exact as flags to MI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341565 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-06 17:07:29 +00:00
Krzysztof Parzyszek 7e54adc682 Consistently use MemoryLocation::UnknownSize to indicate unknown access size
1. Change the software pipeliner to use unknown size instead of dropping
   memory operands. It used to do it before, but MachineInstr::mayAlias
   did not handle it correctly.
2. Recognize UnknownSize in MachineInstr::mayAlias.
3. Print and parse UnknownSize in MIR.

Differential Revision: https://reviews.llvm.org/D50339


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340208 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-20 20:37:57 +00:00
Chandler Carruth e90d44039a [x86/MIR] Implement support for pre- and post-instruction symbols, as
well as MIR parsing support for `MCSymbol` `MachineOperand`s.

The only real way to test pre- and post-instruction symbol support is to
use them in operands, so I ended up implementing that within the patch
as well. I can split out the operand support if folks really want but it
doesn't really seem worth it.

The functional implementation of pre- and post-instruction symbols is
now *completely trivial*. Two tiny bits of code in the (misnamed)
AsmPrinter. It should be completely target independent as well. We emit
these exactly the same way as we emit basic block labels. Most of the
code here is to give full dumping, MIR printing, and MIR parsing support
so that we can write useful tests.

The MIR parsing of MC symbol operands still isn't 100%, as it forces the
symbols to be non-temporary and non-local symbols with names. However,
those names often can encode most (if not all) of the special semantics
desired, and unnamed symbols seem especially annoying to serialize and
de-serialize. While this isn't perfect or full support, it seems plenty
to write tests that exercise usage of these kinds of operands.

The MIR support for pre-and post-instruction symbols was quite
straightforward. I chose to print them out in an as-if-operand syntax
similar to debug locations as this seemed the cleanest way and let me
use nice introducer tokens rather than inventing more magic punctuation
like we use for memoperands.

However, supporting MIR-based parsing of these symbols caused me to
change the design of the symbol support to allow setting arbitrary
symbols. Without this, I don't see any reasonable way to test things
with MIR.

Differential Revision: https://reviews.llvm.org/D50833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339962 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-16 23:11:05 +00:00
Francis Visoiu Mistrih 0ae89b8268 [DebugInfo][X86] Add start-after flags to MIR tests
These tests would fail with -verify-machineinstrs because the MI
generated from the IR would be merged with the one already in the MIR
files, and we get the following error:

```
*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function:    f
```

Differential Revision: https://reviews.llvm.org/D49191

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-12 14:36:48 +00:00
Mikael Holmen b16b4ba59a [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property
Summary:
In some cases, these operands lacked the IsDebug property, which is meant to signal that
they should not affect codegen. This patch adds a check for this property in the
MachineVerifier and adds it where it was missing.

This includes refactorings to use MachineInstrBuilder construction functions instead of
manually setting up the intrinsic everywhere.

Patch by: JesperAntonsson

Reviewers: aprantl, rnk, echristo, javed.absar

Reviewed By: aprantl

Subscribers: qcolombet, sdardis, nemanjai, JDevlieghere, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D48319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335214 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-21 10:03:34 +00:00
Matt Davis dfd20c4090 [MIRParser] Update a diagnostic message to use the correct register sigil. NFC
Summary:
Patch r323922 changed the sigil for physical registers to '$',  instead of '%'.
An error message was missed during this change, and reports the wrong sigil.
This patch corrects that diagnostic and the tests that check that error string.


Reviewers: zer0, bjope

Reviewed By: bjope

Subscribers: bjope, thegameg, plotfi, llvm-commits

Differential Revision: https://reviews.llvm.org/D48086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335066 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 18:39:40 +00:00
Amara Emerson b86b9032fd [MIRParser] Add parser support for 'true' and 'false' i1s.
We already output true and false in the printer, but the parser isn't able to
read it.

Differential Revision: https://reviews.llvm.org/D47424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333970 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 00:17:13 +00:00
Puyan Lotfi d8ca4dd711 [NFC] MIR-Canon: switching to a stable string sorting of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332191 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-13 06:07:20 +00:00
Shiva Chen a8a13bc662 [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
In order to set breakpoints on labels and list source code around
labels, we need collect debug information for labels, i.e., label
name, the function label belong, line number in the file, and the
address label located. In order to keep these information in LLVM
IR and to allow backend to generate debug information correctly.
We create a new kind of metadata for labels, DILabel. The format
of DILabel is

!DILabel(scope: !1, name: "foo", file: !2, line: 3)

We hope to keep debug information as much as possible even the
code is optimized. So, we create a new kind of intrinsic for label
metadata to avoid the metadata is eliminated with basic block.
The intrinsic will keep existing if we keep it from optimized out.
The format of the intrinsic is

llvm.dbg.label(metadata !1)

It has only one argument, that is the DILabel metadata. The
intrinsic will follow the label immediately. Backend could get the
label metadata through the intrinsic's parameter.

We also create DIBuilder API for labels to be used by Frontend.
Frontend could use createLabel() to allocate DILabel objects, and use
insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR.

Differential Revision: https://reviews.llvm.org/D45024

Patch by Hsiangkai Wang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331841 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-09 02:40:45 +00:00
Roman Tereshin 106d54d206 [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)
MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that.

Reviewers: qcolombet t.p.northover aditya_nandakumar

Reviewed By: qcolombet

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D46490


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331712 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-08 02:02:50 +00:00
Heejin Ahn b1f8c095b1 [MIRPraser] Improve error checking for typed immediate operands
Summary:
This improves error checks for typed immediate operands introduced in
D45948 (rL331586), and removes a code block copied by mistake.

Reviewers: rtereshin

Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D46491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331600 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-05 20:53:23 +00:00
Heejin Ahn 869a79511a [MIRParser] Allow register class names in the form of integer/scalar
Summary:
The current code cannot handle register class names like 'i32', which is
a valid register class name in WebAssembly. This patch removes special
handling for integer/scalar/pointer type parsing and treats them as
normal identifiers.

Reviewers: thegameg

Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D45948

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331586 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-05 07:05:51 +00:00
Michael Berg ecfd97d59f MachineInst support mapping SDNode fast math flags for support in Back End code generation
Summary:
Machine Instruction flags for fast math support and MIR print support


Reviewers: spatel, arsenm

Reviewed By: arsenm

Subscribers: wdng

Differential Revision: https://reviews.llvm.org/D45781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331417 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-03 00:07:56 +00:00
Roman Tereshin be8f7c9e0e [MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.

Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar

Reviewed By: qcolombet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46078


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331213 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-30 18:58:57 +00:00
Francis Visoiu Mistrih bea0f24e1c [MIR] Add support for debug metadata for fixed stack objects
Debug var, expr and loc were only supported for non-fixed stack objects.

This patch adds the following fields to the "fixedStack:" entries, and
renames the ones from "stack:" to:

* debug-info-variable
* debug-info-expression
* debug-info-location

Differential Revision: https://reviews.llvm.org/D46032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330859 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 18:58:06 +00:00
Krzysztof Parzyszek e21049990a [if-converter] Handle BBs that terminate in ret during diamond conversion
This fixes https://llvm.org/PR36825.

Original patch by Valentin Churavy (D45218).

Differential Revision: https://reviews.llvm.org/D45731


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330345 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-19 17:26:46 +00:00
Puyan Lotfi 10fa4a104d [MIR-Canon] Fixing a test failure caused by COPY Folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330115 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-16 09:31:49 +00:00
Puyan Lotfi f1f8a6d536 [MIR-Canon] Adding ISA-Agnostic COPY Folding.
Transforms the following:

    %vreg1234:gpr32 = COPY %42
    %vreg1235:gpr32 = COPY %vreg1234
    %vreg1236:gpr32 = COPY %vreg1235
    $w0 = COPY %vreg1236

into:

    $w0 = COPY %42

Assuming %42 is also a gpr32



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330113 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-16 09:03:03 +00:00