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155942 Commits

Author SHA1 Message Date
Simon Pilgrim
d077600b36 [X86][F16C] Regenerate F16C schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316324 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 14:15:24 +00:00
Artur Gainullin
9d639dd5bd Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316322 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 13:25:49 +00:00
George Rimar
2b3608434c [llvm-dwarfdump] - Teach tool about few GNU call_sites constants.
This teaches tool about following consants: 
DW_TAG_GNU_call_site,
DW_TAG_GNU_call_site_parameter,
DW_AT_GNU_call_site_value,
DW_AT_GNU_all_call_sites.

Constants documented here: https://sourceware.org/elfutils/DwarfExtensions

Differential revision: https://reviews.llvm.org/D39119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 11:24:14 +00:00
Ayman Musa
dffb166216 [X86] Add test for opportunity to use bzhi X86 instruction instead of load+and instructions.
Transformation uploaded for CR in https://reviews.llvm.org/D34141.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316320 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 10:24:19 +00:00
Andrew V. Tischenko
a81c79be2f Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue was in illegal segment register index.
Differential Revision: https://reviews.llvm.org/D38786


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316319 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 09:36:33 +00:00
Martin Storsjo
e893335ed8 [COFF] Improve the check for functions that should get an extra underscore
This fixes exporting functions starting with an underscore, and
fully decorated fastcall/vectorcall functions.

Tests will be added in the lld repo.

Differential Revision: https://reviews.llvm.org/D39168

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316316 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 09:08:13 +00:00
Haojian Wu
1d7dfd3aad Fix a -Wpedantic warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316315 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 09:02:59 +00:00
Sam Parker
dc1f81fb55 [ARM] Allow unrolling of multi-block loops.
Before, loop unrolling was only enabled for loops with a single
block. This restriction has been removed and replaced by:
- allow a maximum of two exiting blocks,
- a four basic block limit for cores with a branch predictor.

Differential Revision: https://reviews.llvm.org/D38952


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 08:05:14 +00:00
Craig Topper
d35a2569ff [X86] Update a doxygen comment in the disassembler tablegen code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316309 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 03:42:35 +00:00
Craig Topper
0f7dce5b5c [X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23 02:26:24 +00:00
Saleem Abdulrasool
05ea552595 ExecutionEngine: make COFF Thumb2 assertions non-tautological
The overflow detection assertions were tautological due to truncation.
Adjust them to no longer be tautological.

Patch by Alex Langford!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316303 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 20:51:25 +00:00
Yichao Yu
689fbe0109 Fix invalid ptrtoint in InstCombine
Summary:
It's unclear if this is the only thing we can do but at least this is consistent with the check
of address space agreement in `isBitCastable`.

The code is used at least in both instcombine and jumpthreading though
I could only find a way to trigger the invalid cast in instcombine.

Reviewers: loladiro, sanjoy, majnemer

Reviewed By: sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316302 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 20:28:17 +00:00
Benjamin Kramer
9982ea43e2 Create fewer copies of StringMaps. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316301 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 20:16:28 +00:00
Benjamin Kramer
5a236e2724 [X86] Add missing override. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316299 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 19:16:31 +00:00
Sanjay Patel
5882b22ad1 [SimplifyCFG] delay switch condition forwarding to -latesimplifycfg
As discussed in D39011:
https://reviews.llvm.org/D39011
...replacing constants with a variable is inverting the transform done
by other IR passes, so we definitely don't want to do this early. 
In fact, it's questionable whether this transform belongs in SimplifyCFG 
at all. I'll look at moving this to codegen as a follow-up step.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 19:10:07 +00:00
Fangrui Song
a6c26ffedc [utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.

Subscribers: nemanjai

Differential Revision: https://reviews.llvm.org/D39164

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316297 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 18:43:23 +00:00
Simon Pilgrim
832322f9c9 Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316296 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 18:38:57 +00:00
Marina Yatsina
b76f989d6b Add logic to greedy reg alloc to avoid bad eviction chains
This fixes bugzilla 26810
https://bugs.llvm.org/show_bug.cgi?id=26810

This is intended to prevent sequences like:
movl %ebp, 8(%esp) # 4-byte Spill
movl %ecx, %ebp
movl %ebx, %ecx
movl %edi, %ebx
movl %edx, %edi
cltd
idivl %esi
movl %edi, %edx
movl %ebx, %edi
movl %ecx, %ebx
movl %ebp, %ecx
movl 16(%esp), %ebp # 4 - byte Reload

Such sequences are created in 2 scenarios:

Scenario :
vreg0 is evicted from physreg0 by vreg1
Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from)
Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.)
one of the split intervals ends up evicting vreg2 from physreg1
Evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills

Scenario 
vreg0 is evicted from physreg0 by vreg1
vreg2 is evicted from physreg2 by vreg3 etc
Evictee vreg0 is intended for region splitting with split candidate physreg1
Region splitting creates a local interval because of interference with the evictor vreg1
one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from)
Another evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills

As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest).

Differential Revision: https://reviews.llvm.org/D35816

Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316295 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 17:59:38 +00:00
Craig Topper
3dbdbd2328 [X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.

More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316294 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 17:22:29 +00:00
Sanjay Patel
f7bb38ca4e [SimplifyCFG] try harder to forward switch condition to phi (PR34471)
The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen:

  int switcher(int x) {
      switch(x) {
      case 17: return 17;
      case 19: return 19;
      case 42: return 42;
      default: break;
      }
      return 0;
    }

  int comparator(int x) {
    if (x == 17) return 17;
    if (x == 19) return 19;
    if (x == 42) return 42;
    return 0;
  }

For the first example, we use a bit-test optimization to avoid a series of compare-and-branch:
https://godbolt.org/g/BivDsw

Differential Revision: https://reviews.llvm.org/D39011



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316293 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 16:51:03 +00:00
Momchil Velikov
0be7a36e81 [ARM] Dynamic stack alignment for 16-bit Thumb
This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When
targeting processors, which support only the 16-bit Thumb instruction set
the compiler ignores the alignment attributes of automatic variables and may
silently generate incorrect code.

Differential revision: https://reviews.llvm.org/D38143


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316289 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 11:56:35 +00:00
Guy Blank
5631544a09 [X86] Add a pass to convert instruction chains between domains.
The pass scans the function to find instruction chains that define
registers in the same domain (closures).
It then calculates the cost of converting the closure to another domain.
If found profitable, the instructions are converted to instructions in
the other domain and the register classes are changed accordingly.

This commit adds the pass infrastructure and a simple conversion from
the GPR domain to the Mask domain.

Differential Revision:
https://reviews.llvm.org/D37251

Change-Id: Ic2cf1d76598110401168326d411128ae2580a604

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316288 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 11:43:08 +00:00
Nitesh Jain
ce20559b07 [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.
Reviewers: sdardis

Subscribers: jaydeep, bhushan, llvm-commits

Differential Revision: https://reviews.llvm.org/D38314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316287 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 09:47:41 +00:00
Craig Topper
3ae8f2dc11 [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316285 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 06:18:26 +00:00
Craig Topper
7f31e4c275 [X86] Add VEX_WIG to applicable AVX512 instructions.
This should be NFC. Will be used in future patches to fix disassembler bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316284 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 06:18:23 +00:00
Craig Topper
e5126d5829 [X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316283 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 06:18:20 +00:00
Craig Topper
7447532596 [X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte.
Fixes PR34998.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316282 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22 04:32:30 +00:00
Simon Pilgrim
7f2ed03691 Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316277 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 20:40:49 +00:00
Aaron Ballman
51ff151ed5 Reverting r316270 due to failing build bots.
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316276 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 20:38:15 +00:00
Simon Pilgrim
8d6bf15df6 [X86][SSE] Add extractps/pextrd equivalence to domain tables
Differential Revision: https://reviews.llvm.org/D39135

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316274 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 20:19:48 +00:00
Craig Topper
e746b67d41 [X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.
This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB.

This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type.

This fixes PR32807.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 20:03:20 +00:00
Simon Pilgrim
3ef03332d0 Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316271 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 17:23:04 +00:00
Fangrui Song
ce228816d5 [PPC CodeGen] Fix the bitreverse.i64 intrinsic.
Summary: The two 32-bit words were swapped.

Subscribers: nemanjai, kbarton

Differential Revision: https://reviews.llvm.org/D38705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316270 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 16:59:40 +00:00
Craig Topper
698b76cb6e [ValueTracking] Remove unnecessary temporary APInt from computeNumSignBitsVectorConstant.
We can just use getNumSignBits instead of inverting negative numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316266 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 16:35:41 +00:00
Craig Topper
3afd582859 [ValueTracking] Simplify the known bits code for constant vectors a little.
Neither of these cases really require a temporary APInt outside the loop. For the ConstantDataSequential case the APInt will never be larger than 64-bits so its fine to just call getElementAsAPInt. For ConstantVector we can get the APInt by reference and only make a copy where the inversion is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316265 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 16:35:39 +00:00
Simon Pilgrim
3aad6fd98b [X86][SSE] Add missing extractps scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316262 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 14:35:09 +00:00
David Green
bbbf08b339 [LoopInterchange] Fix phi node ordering miscompile.
The way that splitInnerLoopHeader splits blocks requires that
the induction PHI will be the first PHI in the inner loop
header. This makes sure that is actually the case when there
are both IV and reduction phis.

Differential Revision: https://reviews.llvm.org/D38682



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316261 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 13:58:37 +00:00
Florian Hahn
449e890f29 [SelectionDAG] Use dyn_cast without cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316258 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 05:37:10 +00:00
Florian Hahn
34f57ff3e8 [SelectionDAG] Use isa to silence unused variable warning (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316257 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 04:57:03 +00:00
Craig Topper
ba5255623c [SelectionDAG] Don't subject ConstantSDNodes to the depth limit in computeKnownBits and ComputeNumSignBits.
We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316256 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 03:22:13 +00:00
Craig Topper
cbc06db950 [SelectionDAG] Don't subject ISD:Constant to the depth limit in TargetLowering::SimplifyDemandedBits.
Summary:
We shouldn't recurse any further but it doesn't mean we shouldn't be able to give the known bits for a constant. The caller would probably like that we always return the right answer for a constant RHS. This matches what InstCombine does in this case.

I don't have a test case because this showed up while trying to revive D31724.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: arsenm, llvm-commits

Differential Revision: https://reviews.llvm.org/D38967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316255 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 02:27:19 +00:00
Craig Topper
abd557f982 [X86] Do not generate __multi3 for mul i128 on X86
Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function.  This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test.

Patch by Riyaz V Puthiyapurayil

Reviewers: craig.topper, schweitz

Reviewed By: craig.topper, schweitz

Subscribers: RKSimon, llvm-commits

Differential Revision: https://reviews.llvm.org/D38668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316254 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 02:26:00 +00:00
Eugene Zelenko
cd986088c5 [Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316253 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21 00:57:46 +00:00
Krzysztof Parzyszek
26843fd82c [Packetizer] Add function to check for aliasing between instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 22:08:40 +00:00
Sanjay Patel
84aa0af495 [utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316242 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 21:55:23 +00:00
Eugene Zelenko
8b6784b39c [Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316241 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 21:47:29 +00:00
Sam Clegg
2b6b6ac523 [WebAssembly] MC: Fix crash when -g specified.
At this point we don't output any debug sections or thier
relocations.

Differential Revision: https://reviews.llvm.org/D39076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316240 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 21:28:38 +00:00
Daniel Sanders
d83b5d463d [globalisel][tablegen] Fix small spelling nits. NFC
ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 20:55:29 +00:00
Krzysztof Parzyszek
736ecc1636 [Hexagon] Report error instead of crashing on wrong inline-asm constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316236 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 20:24:44 +00:00
Peter Collingbourne
a29687c501 COFF: Add type server pdb files to linkrepro tar file.
Differential Revision: https://reviews.llvm.org/D38977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316233 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 19:48:26 +00:00