137822 Commits

Author SHA1 Message Date
Craig Topper
d844741822 [X86] Update fast-isel store test to have more 256 and 512-bit test cases. Add command lines for AVX and AVX512 feature sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280681 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 23:58:37 +00:00
Craig Topper
e4bd2be5c6 [X86] Update fast-isel vector load test to have more 256 and 512-bit test cases. Add a command line for SKX features too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280680 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 23:58:32 +00:00
Sanjay Patel
ea437ed14a fix FileCheck variables for test added with r280677
The script (utils/update_test_checks.py) seems to have problems 
with variable names that start with the same string. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280679 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 23:49:32 +00:00
Gor Nishanov
5b6d16cd6c [Coroutines] Part12: Handle alloca address-taken
Summary:
Move early uses of spilled variables after CoroBegin.

For example, if a parameter had address taken, we may end up with the code
like:
        define @f(i32 %n) {
          %n.addr = alloca i32
          store %n, %n.addr
          ...
          call @coro.begin

This patch fixes the problem by moving uses of spilled variables after CoroBegin.

Reviewers: majnemer

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D24234

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280678 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 23:45:45 +00:00
Sanjay Patel
47e6904fe1 [InstCombine] don't assert that division-by-constant has been folded (PR30281)
This is effectively a revert of:
https://reviews.llvm.org/rL280115

And this should fix
https://llvm.org/bugs/show_bug.cgi?id=30281:



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280677 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 23:38:22 +00:00
Sanjay Patel
6704841232 [InstCombine] revert r280637 because it causes test failures on an ARM bot
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/14952/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Aicmp.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280676 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 22:36:32 +00:00
Ahmed Bougacha
7c60fc0c62 [lit] Downgrade error to warning on gtest crashes during discovery.
Lots of unittests started failing under asan after r280455.  It seems
they've been failing for a long time, but lit silently ignored them.

Downgrade the error so we can figure out what is going on.
Filed http://llvm.org/PR30285.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280674 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 20:53:14 +00:00
Craig Topper
a8cbd72674 [AVX-512] Integrate mask register copying more completely into X86InstrInfo::copyPhysReg and simplify. No functional change intended.
The code is now written in terms of source and dest classes with feature checks inside each type of copy instead of having separate functions for each feature set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280673 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 20:34:50 +00:00
Simon Pilgrim
bf482f99dd [X86][SSE] Add test cases for PR29078
'Failure to recognise i64 sitofp/uitofp conversions that can be performed as i32'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280671 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 18:11:17 +00:00
Simon Pilgrim
70794a5363 [X86][SSE] Add test cases for PR29079
'Failure to recognise uitofp conversions that can be performed as sitofp'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280670 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 18:04:38 +00:00
whitequark
232532671e CODE_OWNERS: bring my entry up to date
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280667 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 17:42:46 +00:00
Simon Pilgrim
70de308288 [X86][SSE] Regenerate odd shuffle tests with common prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280661 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 14:15:38 +00:00
Oliver Stannard
bbe0f05199 [SimplifyCFG] Add test for sinking inline asm in if/else
This test code previously caused a failure in the module verifier,
because SimplifyCFG created this invalid instruction, which tries to
take the address of inline asm:
  %.sink = select i1 %1, i64 ()* asm "mov $0, #1", "=r", i64 ()* asm %"mov $0, #2", "=r"

This has been fixed recently, presumably by James Molloy's patches that
re-wrote and changed parts of SimplifyCFG, so this patch just adds a
regression test for it.

Differential Revision: https://reviews.llvm.org/D24231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280660 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 13:49:26 +00:00
Benjamin Kramer
7e3e982267 [WebAssembly] Unbreak the build.
Not sure why ADL isn't working here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280656 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 12:06:47 +00:00
Valery Pykhtin
b01d8d2aaa [AMDGPU] Refactor FLAT TD instructions
Differential revision: https://reviews.llvm.org/D24072

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280655 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 11:22:51 +00:00
James Molloy
af86df2b0f [Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}
These need to be mapped through to R_ARM_THM_JUMP{11,8} respectively.

Fixes PR30279.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280651 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 08:29:15 +00:00
Igor Breger
65e0a96325 [AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.
Differential Revision: http://reviews.llvm.org/D23983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280650 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 08:26:51 +00:00
Craig Topper
e8886131cc [X86] Make some static arrays of opcodes const and shrink to uint16_t. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280649 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 07:14:21 +00:00
Craig Topper
bda8c85789 [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX512, but not VLX. We should use the VEX opcodes and trust the register allocator to not use the extended XMM/YMM register space.
Previously we were extending to copying the whole ZMM register. The register allocator shouldn't use XMM16-31 or YMM16-31 in this configuration as the instructions to spill them aren't available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280648 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 06:43:06 +00:00
Craig Topper
481ecf26d0 [Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280647 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 06:43:00 +00:00
Gor Nishanov
ac396ea37f [Coroutines] Part11: Add final suspend handling.
Summary:
A frontend may designate a particular suspend to be final, by setting the second argument of the coro.suspend intrinsic to true. Such a suspend point has two properties:

* it is possible to check whether a suspended coroutine is at the final suspend point via coro.done intrinsic;
* a resumption of a coroutine stopped at the final suspend point leads to undefined behavior. The only possible action for a coroutine at a final suspend point is destroying it via coro.destroy intrinsic.

This patch adds final suspend handling logic to CoroEarly and CoroSplit passes.
Now, the final suspend point example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex5.ll).

Reviewers: majnemer

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D24068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280646 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 04:44:30 +00:00
Craig Topper
384a721ef9 [X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280645 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 02:20:53 +00:00
Craig Topper
bfa3e95442 [X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. Due to their placement in the td file they had lower precedence than (V)MOVSS/SD and could almost never be selected.
The only way to select them was in AVX512 mode because EVEX VMOVSS/SD was below them and the patterns weren't qualified properly for AVX only. So if you happened to have an aligned FR32/FR64 load in AVX512 you could get a VEX encoded VMOVAPS/VMOVAPD.

I tried to search back through history and it seems like these instructions were probably unselectable for at least 5 years, at least to the time the VEX versions were added. But I can't prove they ever were.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280644 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 02:20:49 +00:00
Peter Zotov
d02e8e5e5c [CMake] [OCaml] Allow building OCaml bindings out of tree.
That is, add build system support for building the OCaml bindings
against preinstalled LLVM libraries. This is important for package
managers such as OPAM, because OCaml libraries need to be built
against a specific OCaml compiler installation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280642 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 01:42:22 +00:00
NAKAMURA Takumi
2b9ec0812b lit/util.py: Another fix for py3.
'str' object has no attribute 'decode'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280641 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 00:00:40 +00:00
Sanjay Patel
7ae81d5c8b [InstCombine] allow icmp (and X, C2), C1 folds for splat constant vectors
The code to calculate 'UsesRemoved' could be simplified.
As-is, that code is a victim of PR30273:
https://llvm.org/bugs/show_bug.cgi?id=30273



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280637 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 20:58:27 +00:00
Craig Topper
2eb4a16416 [AVX-512] Add EVEX encoded scalar FMA intrinsic instructions to isNonFoldablePartialRegisterLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280636 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 19:33:47 +00:00
Simon Pilgrim
e330ad3884 [X86] Regenerate x64 mmx/f64 return value tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280634 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 18:14:45 +00:00
Craig Topper
3a32e24112 [AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div intrinsics and upgrade to native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280633 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 18:13:33 +00:00
Lang Hames
b80c6300c5 [ORC] Clone module flags metadata into the globals module in the
CompileOnDemandLayer.

Also contains a tweak to the orc-lazy jit in LLI to enable the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280632 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 17:53:30 +00:00
Simon Pilgrim
fa79defc96 [X86] Regenerate trunc-store legalization test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280631 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 17:50:03 +00:00
Simon Pilgrim
4668efbe49 [X86][SSE] Regenerate fcmp/uitofp combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280629 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 17:16:01 +00:00
Lang Hames
1af58786cf [ORC] Fix an unfinished comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280628 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 16:31:41 +00:00
Sanjay Patel
e57e8b4c4c [InstCombine] recode icmp fold in a vector-friendly way; NFC
The transform in question:
icmp (and (trunc W), C2), C1 -> icmp (and W, C2'), C1'

...is still not enabled for vectors, thus no functional change intended.
It's not clear to me if this is a good transform for vectors or even
scalars in general. Changing that behavior may be a follow-on patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280627 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 14:32:15 +00:00
Hal Finkel
f21bb8dcbd [PowerPC] During branch relaxation, recompute padding offsets before each iteration
We used to compute the padding contributions to the block sizes during branch
relaxation only at the start of the transformation. As we perform branch
relaxation, we change the sizes of the blocks, and so the amount of inter-block
padding might change. Accordingly, we need to recompute the (alignment-based)
padding in between every iteration on our way toward the fixed point.

Unfortunately, I don't have a test case (and none was provided in the bug
report), and while this obviously seems needed, algorithmically, I don't have
any way of generating a small and/or non-fragile regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280626 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 14:18:29 +00:00
Igor Breger
02eff5c342 revert r279960.
https://llvm.org/bugs/show_bug.cgi?id=30249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280625 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 14:03:52 +00:00
Simon Pilgrim
e1ae1c872e EOL fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280624 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 13:30:46 +00:00
Simon Pilgrim
1d5ab2bf73 Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280623 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 13:28:46 +00:00
Chandler Carruth
fcaf12c564 [PM] Revert r280447: Add a unittest for invalidating module analyses with an SCC pass.
This was mistakenly committed. The world isn't ready for this test, the
test code has horrible debugging code in it that should never have
landed in tree, it currently passes because of bugs elsewhere, and it
needs to be rewritten to not be susceptible to passing for the wrong
reasons.

I'll re-land this in a better form when the prerequisite patches land.

So sorry that I got this mixed into a series of commits that *were*
ready to land. I shouldn't have. =[ What's worse is that it stuck around
for so long and I discovered it while fixing the underlying bug that
caused it to pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280620 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 08:42:31 +00:00
Chandler Carruth
34a0f7afe3 [LCG] Clean up and make NDEBUG verify calls more rigorous with
make_scope_exit now that we have that utility.

This makes the code much more clear and readable by isolating the check.
It also makes it easy to go through and make sure all the interesting
update routines have a start and end verify so we don't slowly let the
graph drift into an invalid state.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280619 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 08:34:31 +00:00
Chandler Carruth
443069cec2 [LCG] A NFC refactoring to extract the logic for doing
a postorder-sequence based update after edge insertion into a generic
helper function.

This separates the SCC-specific logic into two fairly simple lambdas and
extracts the rest into a generic helper template function. I think this
is a net win on its own merits because it disentangles different pieces
of the algorithm. Now there is one place that does the two-step
partition to identify a set of newly connected components and at the
same time update the postorder sequence.

However, I'm also hoping to re-use this an upcoming patch to update
a cached post-order sequence of RefSCCs when doing the analogous update
to the RefSCC graph, and I don't want to have two copies.

The diff is quite messy but this really is just moving things around and
making types generic rather than specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280618 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 08:34:24 +00:00
Dorit Nuzman
cc6b354faf [InstCombine] Preserve llvm.mem.parallel_loop_access metadata when replacing
memcpy with ld/st.

When InstCombine replaces a memcpy with loads+stores it does not copy over the
llvm.mem.parallel_loop_access from the memcpy instruction. This patch fixes
that.

Differential Revision: https://reviews.llvm.org/D23499



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280617 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 07:49:39 +00:00
Lang Hames
c6f214bfea [ExecutionEngine] Move ObjectCache::anchor from MCJIT to ExecutionEngine.
ObjectCache is an ExecutionEngine utility, so its anchor belongs there. The
practical impact of this change is that ORC users no longer need to link MCJIT
to use ObjectCaches.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280616 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 07:24:11 +00:00
Dorit Nuzman
e99c574578 Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280615 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 07:06:00 +00:00
Hal Finkel
204ba881b8 [PowerPC] Zero-extend constants in FastISel
As it turns out, whether we zero-extend or sign-extend i8/i16 constants, which
are illegal types promoted to i32 on PowerPC, is a choice constrained by
assumptions within the infrastructure. Specifically, the logic in
FunctionLoweringInfo::ComputePHILiveOutRegInfo assumes that constant PHI
operands will be zero extended, and so, at least when materializing constants
that are PHI operands, we must do the same.

The rest of our fast-isel implementation does not appear to depend on the fact
that we were sign-extending i8/i16 constants, and all other targets also appear
to zero-extend small-bitwidth constants in fast-isel; we'll now do the same (we
had been doing this only for i1 constants, and sign-extending the others).

Fixes PR27721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280614 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 06:07:19 +00:00
Craig Topper
d88c98e923 [AVX-512] Remove masked integer add/sub/mull intrinsics and upgrade to native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280611 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 02:09:53 +00:00
Joseph Tremoulet
37c54c60a5 Fix inliner funclet unwind memoization
Summary:
The inliner may need to determine where a given funclet unwinds to,
and this determination may depend on other funclets throughout the
funclet tree.  The code that performs this walk in getUnwindDestToken
memoizes results to avoid redundant computations.  In the case that
a funclet's unwind destination is derived from its ancestor, there's
code to walk back down the tree from the ancestor updating the memo
map of its descendants to record the unwind destination.  This change
fixes that code to account for the case that some descendant has a
different unwind destination, which can happen if that unwind dest
is a descendant of the EHPad being queried and thus didn't determine
its unwind destination.

Also update test inline-funclets.ll, which is supposed to cover such
scenarios, to include a case that fails an assertion without this fix
but passes with it.

Fixes PR29151.


Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280610 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-04 01:23:20 +00:00
Craig Topper
1ce43697d1 [X86] Combine some of the strings in autoupgrade code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280603 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-03 23:55:13 +00:00
Xinliang David Li
1f44212e7e Cleanup : Use metadata preserving API for branch creation
Use the wrapper API in IRBuilder that does meta data copy
to create new branch in LoopUnswitch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280602 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-03 22:26:11 +00:00
Xinliang David Li
da48846879 [Profile] preserve branch metadata lowering select in CGP
CGP currently drops select's MD_prof profile data when
generating conditional branch which can lead to bad
code layout. The patch fixes the issue.

Differential Revision: http://reviews.llvm.org/D24169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280600 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-03 21:26:36 +00:00