Commit Graph

931 Commits

Author SHA1 Message Date
Simon Dardis 9331b2fae1 [mips] Mark microMIPS64 as being unsupported.
There are no provided instruction definitions for this architecture.

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D48320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335057 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 16:05:44 +00:00
Simon Dardis 58b1f43714 [mips] Fix the predicates of some aliases
Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D48321


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335053 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 15:25:01 +00:00
Simon Dardis a1847c760c [mips] Guard some floating point instructions correctly
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47636


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334491 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-12 10:28:06 +00:00
Simon Dardis f22b386635 [mips] Partially revert r334031
The test changes in r334031 give unstable pass/fail results on the
llvm-clang-x86_64-expensive-checks-win buildbot. Revert the test changes to
turn the bot green.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334084 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-06 10:54:30 +00:00
Simon Dardis 8499c1a397 [mips] Fix the predicates for arithmetic operations
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47635


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334031 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-05 17:53:22 +00:00
Simon Atanasyan d525a1e0b6 [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.

The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.

Differential Revision: https://reviews.llvm.org/D47316

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333774 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 16:37:53 +00:00
Simon Atanasyan 50fd0f624a [mips] Extend list of relocations supported by the .reloc directive
Supporting GOT and TLS related relocations by the `.reloc` directive is
useful for purpose of testing various tools like a linker, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333773 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 16:37:42 +00:00
Simon Dardis aa33e079d2 [mips] Guard 'nop' properly and add mips16's nop instruction
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47583


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333739 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-01 10:46:00 +00:00
Simon Dardis a2207057d9 [mips] Guard all short instructions correctly.
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333645 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-31 12:47:01 +00:00
Simon Dardis 056c0666f5 [mips] Correct the predicates of arithmetic and logic instructions.
As part of this effort, duplicate and correct the predicates of some
aliases. Also disable code generation of some short form instructions
for FastISel, as it would otherwise reject them.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D47075


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333530 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-30 11:33:35 +00:00
Simon Atanasyan fc06be5513 [mips] Process numeric register name in the .set assignment directive
Now LLVM assembler cannot process the following code and generates an
error. GNU tools support .set assignment directive with numeric register
name.

```
.set r4, 4

test.s:1:11: error: invalid token in expression
  .set r4, $4
           ^
```

This patch teach assembler to handle such directives correctly.
Unfortunately a numeric register name cannot be represented as an
expression. That's why we have to maintain a separate `StringMap`
in the `MipsAsmParser` to keep mapping between aliases names and
register numbers.

Differential revision: https://reviews.llvm.org/D47464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333428 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 15:58:06 +00:00
Simon Atanasyan cfb33a0de9 [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 relocations
Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and
R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of
relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel()))
expressions in case of microMIPS.

Differential Revision: http://reviews.llvm.org/D47220

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333409 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 11:33:54 +00:00
Simon Atanasyan 30edd11e20 [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations
Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher()
and %highest() expressions in case of microMIPS. These relocations do
exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for
consistency it's better to write microMIPS variants.

Differential Revision: http://reviews.llvm.org/D47219

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333407 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 10:27:44 +00:00
Simon Dardis 1b5b9b6170 [mips] Correct the predicates for a number of instructions.
Previously, their listed predicates were overridden at the scope level.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46947


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333405 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 09:56:19 +00:00
Simon Atanasyan 66039bf097 [mips] Stop parsing a .set assignment if the first argument is not an identifier
Before this fix the following code triggers two error messages. The
second one is at least useless:

  test.s:1:9: error: expected identifier after .set
    .set  123, $a0
          ^
  test-set.s:1:9: error: unexpected token, expected comma
    .set  123, $a0
          ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333402 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 09:51:22 +00:00
Simon Dardis 48f3050c47 [mips] Correct the predicates of the cache and pref instructions
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46949


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332970 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-22 10:55:05 +00:00
Simon Dardis e7c11b7093 [mips] Add microMIPSR6 ll/sc instructions.
Previously the compiler was using the microMIPSR3 variants, incorrectly.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46948


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332820 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-20 17:21:00 +00:00
Petar Jovanovic 6209d969a2 [mips] Add support for Global INValidate ASE
This includes

  Instructions: ginvi, ginvt,

  Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

  Attribute: ginv

  .MIPS.abiflags: GINV (0x20000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D46268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332624 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 16:30:32 +00:00
Simon Dardis 1cc744a2e5 [mips] Mark select instructions correctly
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46702


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332364 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-15 16:05:04 +00:00
Simon Dardis 3319b10cf9 [mips] Add disassembly support for comparison instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332340 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-15 11:18:24 +00:00
Simon Dardis e9a999eea8 [mips] Fix predicates of mfc1, mtc1 instructions
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46692


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332339 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-15 11:10:30 +00:00
Simon Dardis 08ef88f001 [mips] Fix the predicates of round, ceiling, floor and trunc.
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46691


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332258 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 16:26:50 +00:00
Simon Dardis 65e6faea89 [mips] Add missing test case from r332227
I did not commit this test from D46689.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332241 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 13:18:51 +00:00
Simon Dardis d91853e2c4 [mips] Correct the predicates of indexed floating point stores and loads.
Also, fix the register class for microMIPS.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46689


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332227 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 10:53:15 +00:00
Simon Dardis a884ad2442 [mips] Enable disassembly of fused (negative) multiply add/sub instructions
Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46392


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332097 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-11 15:21:40 +00:00
Simon Atanasyan 34b34574ba [mips] Accept 32-bit offsets for ld/sd/lld commands
This is a follow up to the rL330983. The patch teaches ld, sd, and lld
commands accept 32-bit memory offsets by replacing `mem_simm16` operand
to `mem_simmptr`. In fact, these commands should accept 64-bit offsets,
but so large offsets require another command expanding and will be
supported by a separate patch.

Differential Revision: https://reviews.llvm.org/D46629

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331997 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-10 16:01:36 +00:00
Simon Atanasyan 316c970285 [mips] Accept 32-bit offsets for lh and lhu commands
This is a follow up to the rL330983. The patch teaches lh and lhu
commands accepts 32-bit memory offsets by replacing `mem_simm16` operand
to `mem_simmptr`.

Differential Revision: https://reviews.llvm.org/D46513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331996 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-10 16:01:18 +00:00
Simon Dardis 0f6b0335f9 [mips] Correct the predicates of cvt.fmt.fmt instructions
Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46390


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331969 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-10 10:42:30 +00:00
Simon Dardis beccc07820 [mips] Move conditional moves out of isCodeGenOnly
Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46389


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331863 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-09 10:33:21 +00:00
Simon Dardis 5a886bf8e6 [mips] Mark various memory instructions as being in microMIPS (NFC)
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46388


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-08 10:16:21 +00:00
Simon Dardis f100a5dc31 [mips] Correct clo/clz predicates
Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46125


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331754 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-08 09:50:37 +00:00
Simon Dardis aff0c11ab4 [mips] Correct the predicates of sign extension instructions
And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331526 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-04 15:00:54 +00:00
Simon Dardis d0aace53a9 Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331348 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-02 12:35:29 +00:00
Simon Dardis b997056fc0 [mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331346 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-02 12:25:33 +00:00
Simon Dardis 112e4a35e6 [mips] Correct the predicates for shifts.
Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46123


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331341 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-02 09:55:49 +00:00
Simon Dardis 223197ab45 [mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.

Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46055


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331165 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-30 09:44:44 +00:00
Petar Jovanovic 0059657b9a [mips] Add support for Virtualization ASE
This includes

  Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
                mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,

  Assembler directives: .set virt, .set novirt, .module virt, .module novirt

  Attribute: virt

  .MIPS.abiflags: VZ (0x100)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44905


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331024 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-27 09:12:08 +00:00
Simon Atanasyan 5f68be89e4 [mips] Accept 32-bit offsets for lb and lbu commands
`lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts
larger offsets for these commands. If an offset does not fit in 16-bit
range, `lb` command is translated into lui/lb or lui/addu/lb series.
It's interesting that initially LLVM assembler supported this feature,
but later it was broken.

This patch restores support for 32-bit offsets. It replaces `mem_simm16`
operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand.
This operand is intended to check that offset fits to the same size as
using for pointers. Later we will be able to extend this rule and
accepts 64-bit offsets when it is possible.

Some issues remain:
- The regression also affects LD, SD, LH, LHU commands. I'm going
  to fix them by a separate patch.

- GAS accepts any 32-bit values as an offset. Now LLVM accepts signed
  16-bit values and this patch extends the range to signed 32-bit offsets.
  In other words, the following code accepted by GAS and still triggers
  an error by LLVM:
```
  lb      $4, 0x80000004

  # gas
  lui     a0, 0x8000
    lb      a0, 4(a0)
```

- In case of 64-bit pointers GAS accepts a 64-bit offset and translates
  it to the li/dsll/lb series of commands. LLVM still rejects it.
  Probably this feature has never been implemented in LLVM. This issue
  is for a separate patch.
```
  lb      $4, 0x800000001

  # gas
  li      a0, 0x8000
  dsll    a0, a0, 0x14
  lb      a0, 4(a0)
```

Differential Revision: https://reviews.llvm.org/D45020

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330983 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-26 19:55:28 +00:00
Simon Dardis 33005b401f [mips] Fix a test case which is keeping the expensive checks bot win red (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330956 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-26 16:22:47 +00:00
Simon Dardis ce17a9d46b [mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.

Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D45939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330952 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-26 16:06:34 +00:00
Simon Dardis 5ce6b66393 [mips] Fix the definition of sync, synci
Also, fix the disassembly of synci for microMIPS.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45870


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330810 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:19:22 +00:00
Simon Dardis f2df8a65f4 Reland "[mips] Guard traps for microMIPS correctly"
This is part of fixing the instruction predicates for MIPS.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44212


This patch relands r327409, hopefully without the problematic part of the
tests that cause FileCheck to assert on the windows expensive checks bot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330741 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 17:11:37 +00:00
Simon Atanasyan 6f8184d949 [mips] Show an error if register number is out of range
Current code does not check that a register number is in the 0-31 range.
Sometimes the parser checks that later for some kinds of instructions,
but that leads to unclear / incorrect error messages like that:

  % cat test.s
  .text
  lb $4, 8($32)

  % llvm-mc test.s -triple=mips64-unknown-linux
  test.s:2:10: error: expected memory with 16-bit signed offset
    lb $4, 8($32)
           ^

Sometimes the parser just crashes:

  % cat test.s
  .text
  lw  $4, 8($32)

  % llvm-mc test.s -triple=mips64-unknown-linux

This patch resolves the problem by checking that register number after
'$' sign is in the 0-31 range. If the number is out of the range the
parser shows the `invalid register number` error, but treats invalid
register number as a normal one to continue parsing and catch other
possible errors.

Differential Revision: https://reviews.llvm.org/D45919

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330732 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:14:00 +00:00
Simon Dardis 439126f10f [mips] Guard some macro expansions properly
Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D45565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330315 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-19 09:45:04 +00:00
Stefan Maksimovic 73e5c16fba [mips] Restrict certain trap instructions for micromipsr6
Instructions removed from micromipsr6:
teqi, tgei, tgeiu, tlti, tltiu, tnei

Differential Revision: https://reviews.llvm.org/D45318


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330114 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-16 09:22:20 +00:00
Simon Dardis 293041f690 [mips] Correct the predicates of the load/store (double)word for coprocessor 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329913 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 14:41:38 +00:00
Simon Dardis e671fc896b [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44436


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329905 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 12:37:02 +00:00
Krzysztof Parzyszek 9273bb3570 Use .set instead of = when printing assignment in assembly output
On Hexagon "x = y" is a syntax used in most instructions, and is not
treated as a directive.

Differential Revision: https://reviews.llvm.org/D44256


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328635 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-27 16:44:41 +00:00
Petar Jovanovic cad9f50df3 [mips] Add support for CRC ASE
This includes

  Instructions: crc32b, crc32h, crc32w, crc32d,
                crc32cb, crc32ch, crc32cw, crc32cd

  Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc

  Attribute: crc

  .MIPS.abiflags: CRC (0x8000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44176


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327511 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-14 14:13:31 +00:00
Simon Dardis 14d8d03fe2 Revert "[mips] Guard traps for microMIPS correctly"
This appears to have broken the expensive checks bot in
a strange fashion. Reverting until I can investigate.

This reverts r327409.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327427 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-13 17:31:11 +00:00