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Roman Lebedev c285223daf [CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case) 
Summary:
This implements an optimization described in Hacker's Delight 10-17:
when `C` is constant, the result of `X % C == 0` can be computed
more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

One huge caveat: this signed case is only valid for positive divisors.

While we can freely negate negative divisors, we can't negate `INT_MIN`,
so for now if `INT_MIN` is encountered, we bailout.
As a follow-up, it should be possible to handle that more gracefully
via extra `and`+`setcc`+`select`.

This passes llvm's test-suite, and from cursory(!) cross-examination
the folds (the assembly) match those of GCC, and manual checking via alive
did not reveal any issues (other than the `INT_MIN` case)

Reviewers: RKSimon, spatel, hermord, craig.topper, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: xbolva00, thakis, javed.absar, hiraditya, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368702 91177308-0d34-0410-b5e6-96231b3b80d8
2019-08-13 14:57:37 +00:00
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avx512-shuffles
[X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))
2019-07-03 14:34:16 +00:00
GC
[lit] Delete empty lines at the end of lit.local.cfg NFC
2019-06-17 09:51:07 +00:00
GlobalISel
[globalisel] Add G_SEXT_INREG
2019-08-09 21:11:20 +00:00
3addr-16bit.ll
[DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
2018-04-24 22:35:27 +00:00
3addr-or.ll
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
2019-03-27 19:54:41 +00:00
3dnow-intrinsics.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
4char-promote.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
8bit_cmov_of_trunc_promotion.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
2003-08-03-CallArgLiveRanges.ll
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[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
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Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
2019-03-25 18:51:57 +00:00
2006-11-27-SelectLegalize.ll
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2007-02-16-BranchFold.ll
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2007-02-25-FastCCStack.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-04-17-LiveIntervalAssert.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
[X86][MMX] Regenerate MMX MASKMOV test
2018-02-21 16:38:08 +00:00
2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
[X86] Regenerate GPR:XMM bitcast test
2018-02-21 15:05:47 +00:00
2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
2007-09-27-LDIntrinsics.ll
Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly"
2019-02-04 04:15:02 +00:00
2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-15-CoalescerCrash.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2007-10-16-CoalescerCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-31-SpillerFoldingBug.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2008-04-02-unnamedEH.ll
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Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2008-05-22-FoldUnalignedLoad.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug2.ll
[DAGCombiner] re-enable truncation of binops
2018-12-08 16:07:38 +00:00
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-29-ReMatBug.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
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2008-09-29-VolatileBug.ll
[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
2019-04-24 19:28:38 +00:00
2008-10-06-x87ld-nan-1.ll
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2008-10-16-VecUnaryOp.ll
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2008-12-23-crazy-address.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
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Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
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2009-04-12-FastIselOverflowCrash.ll
test/CodeGen/X86: Relax test case
2018-11-10 00:34:09 +00:00
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
Reapply ARM: Do not spill CSR to stack on entry to noreturn functions
2018-04-07 10:57:03 +00:00
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[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
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2010-04-06-SSEDomainFixCrash.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-04-08-CoalescerBug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-04-13-AnalyzeBranchCrash.ll
…
2010-04-21-CoalescerBug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-04-29-CoalescerCrash.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-04-30-LocalAlloc-LandingPad.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-05-03-CoalescerSubRegClobber.ll
…
2010-05-05-LocalAllocEarlyClobber.ll
…
2010-05-06-LocalInlineAsmClobber.ll
…
2010-05-07-ldconvert.ll
…
2010-05-10-DAGCombinerBug.ll
…
2010-05-12-FastAllocKills.ll
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
2018-02-09 00:10:31 +00:00
2010-05-16-nosseconversion.ll
…
2010-05-25-DotDebugLoc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-05-26-DotDebugLoc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-05-26-FP_TO_INT-crash.ll
…
2010-05-28-Crash.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-06-01-DeadArg-DbgInfo.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
2010-06-09-FastAllocRegisters.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-06-14-fast-isel-fs-load.ll
…
2010-06-15-FastAllocEarlyCLobber.ll
…
2010-06-24-g-constraint-crash.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-06-25-asm-RA-crash.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-06-25-CoalescerSubRegDefDead.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2010-06-28-FastAllocTiedOperand.ll
…
2010-06-28-matched-g-constraint.ll
…
2010-07-02-asm-alignstack.ll
…
2010-07-02-UnfoldBug.ll
…
2010-07-06-asm-RIP.ll
…
2010-07-06-DbgCrash.ll
…
2010-07-11-FPStackLoneUse.ll
…
2010-07-13-indirectXconstraint.ll
…
2010-07-15-Crash.ll
…
2010-07-29-SetccSimplify.ll
…
2010-08-04-MaskedSignedCompare.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
2010-08-04-MingWCrash.ll
…
2010-08-04-StackVariable.ll
…
2010-09-01-RemoveCopyByCommutingDef.ll
…
2010-09-16-asmcrash.ll
…
2010-09-16-EmptyFilename.ll
…
2010-09-17-SideEffectsInChain.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2010-09-30-CMOV-JumpTable-PHI.ll
…
2010-10-08-cmpxchg8b.ll
…
2010-11-02-DbgParameter.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2010-11-09-MOVLPS.ll
…
2010-11-18-SelectOfExtload.ll
…
2011-01-07-LegalizeTypesCrash.ll
…
2011-01-10-DagCombineHang.ll
…
2011-01-24-DbgValue-Before-Use.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
2011-02-04-FastRegallocNoFP.ll
…
2011-02-12-shuffle.ll
…
2011-02-21-VirtRegRewriter-KillSubReg.ll
…
2011-02-23-UnfoldBug.ll
…
2011-02-27-Fpextend.ll
…
2011-03-02-DAGCombiner.ll
…
2011-03-08-Sched-crash.ll
…
2011-03-09-Physreg-Coalescing.ll
…
2011-03-30-CreateFixedObjCrash.ll
…
2011-04-13-SchedCmpJmp.ll
…
2011-04-19-sclr-bb.ll
…
2011-05-09-loaduse.ll
[X86][SSE] Add x64 load use test case
2019-08-08 11:24:23 +00:00
2011-05-26-UnreachableBlockElim.ll
…
2011-05-27-CrossClassCoalescing.ll
…
2011-06-01-fildll.ll
…
2011-06-03-x87chain.ll
…
2011-06-06-fgetsign80bit.ll
…
2011-06-12-FastAllocSpill.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2011-06-14-mmx-inlineasm.ll
…
2011-06-14-PreschedRegalias.ll
…
2011-06-19-QuicksortCoalescerBug.ll
…
2011-07-13-BadFrameIndexDisplacement.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2011-08-23-PerformSubCombine128.ll
…
2011-08-23-Trampoline.ll
…
2011-08-29-BlockConstant.ll
…
2011-08-29-InitOrder.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
2011-09-14-valcoalesce.ll
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
2017-11-30 12:12:19 +00:00
2011-09-18-sse2cmp.ll
…
2011-09-21-setcc-bug.ll
…
2011-10-11-SpillDead.ll
…
2011-10-11-srl.ll
…
2011-10-12-MachineCSE.ll
…
2011-10-18-FastISel-VectorParams.ll
…
2011-10-19-LegelizeLoad.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2011-10-19-widen_vselect.ll
[X86] Fix some tests using fcmp with undef arguments
2019-03-29 17:20:27 +00:00
2011-10-21-widen-cmp.ll
[X86] Fix some tests using fcmp with undef arguments
2019-03-29 17:20:27 +00:00
2011-10-27-tstore.ll
…
2011-10-30-padd.ll
…
2011-11-07-LegalizeBuildVector.ll
…
2011-11-22-AVX2-Domains.ll
…
2011-11-30-or.ll
…
2011-12-8-bitcastintprom.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2011-12-06-AVXVectorExtractCombine.ll
…
2011-12-06-BitcastVectorGlobal.ll
…
2011-12-08-AVXISelBugs.ll
…
2011-12-15-vec_shift.ll
…
2011-12-26-extractelement-duplicate-load.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
2011-12-28-vselecti8.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2011-20-21-zext-ui2fp.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
2012-1-10-buildvector.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
2012-01-10-UndefExceptionEdge.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
2012-01-11-split-cv.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
2012-01-12-extract-sv.ll
[x86] allow vector load narrowing with multi-use values
2018-11-10 20:05:31 +00:00
2012-01-16-mfence-nosse-flags.ll
…
2012-01-18-vbitcast.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2012-02-12-dagco.ll
…
2012-02-14-scalar.ll
…
2012-02-23-mmx-inlineasm.ll
…
2012-02-29-CoalescerBug.ll
[X86][NFC] Replace "<%s" with "< %s" in run-lines.
2019-01-27 15:36:35 +00:00
2012-03-15-build_vector_wl.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2012-03-20-LargeConstantExpr.ll
…
2012-03-26-PostRALICMBug.ll
…
2012-04-09-TwoAddrPassBug.ll
…
2012-04-26-sdglue.ll
[DAGCombiner] narrow vector binops when extraction is cheap
2018-10-30 14:14:34 +00:00
2012-05-17-TwoAddressBug.ll
…
2012-05-19-CoalescerCrash.ll
…
2012-07-10-extload64.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
2012-07-10-shufnorm.ll
…
2012-07-15-broadcastfold.ll
…
2012-07-15-BuildVectorPromote.ll
…
2012-07-15-tconst_shl.ll
…
2012-07-15-vshl.ll
…
2012-07-16-fp2ui-i1.ll
…
2012-07-16-LeaUndef.ll
…
2012-07-17-vtrunc.ll
…
2012-07-23-select_cc.ll
…
2012-08-07-CmpISelBug.ll
[TargetLowering] Add SimplifyMultipleUseDemandedBits
2019-07-23 12:39:08 +00:00
2012-08-16-setcc.ll
[X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching
2018-02-01 17:08:39 +00:00
2012-08-17-legalizer-crash.ll
…
2012-08-28-UnsafeMathCrash.ll
…
2012-09-13-dagco-fneg.ll
…
2012-09-28-CGPBug.ll
…
2012-10-02-DAGCycle.ll
…
2012-10-03-DAGCycle.ll
…
2012-10-18-crash-dagco.ll
…
2012-11-28-merge-store-alias.ll
…
2012-12-1-merge-multiple.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
2012-12-12-DAGCombineCrash.ll
…
2012-12-14-v8fp80-crash.ll
…
2012-12-19-NoImplicitFloat.ll
…
2013-01-09-DAGCombineBug.ll
…
2013-03-13-VEX-DestReg.ll
…
2013-05-06-ConactVectorCrash.ll
…
2013-10-14-FastISel-incorrect-vreg.ll
…
2014-05-29-factorial.ll
…
2014-08-29-CompactUnwind.ll
…
9601.ll
…
20090313-signext.ll
…
abi-isel.ll
[X86] Fix linux32 pic tests to use correct relocation model (PR39684)
2019-01-29 10:41:48 +00:00
absolute-bit-mask-fastisel.ll
[X86] FastISel fall back on !absolute_symbol GVs
2018-08-01 17:44:37 +00:00
absolute-bit-mask.ll
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
2017-10-01 23:53:53 +00:00
absolute-bt.ll
…
absolute-cmp.ll
…
absolute-constant.ll
…
absolute-rotate.ll
[X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
2019-03-18 20:43:15 +00:00
add32ri8.ll
…
add_shl_constant.ll
…
add-ext.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
add-i64.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
add-of-carry.ll
[DAGCombiner] Don't combine (addcarry (uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry) if the Carry comes from the uaddo.
2019-07-04 18:18:46 +00:00
add-sub-nsw-nuw.ll
[DAGCombiner] re-enable truncation of binops
2018-12-08 16:07:38 +00:00
add.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
addcarry2.ll
[X86] Extend load-op-store fusion merge to ADC/SBB.
2018-01-19 15:37:57 +00:00
addcarry.ll
[DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
2019-07-16 15:17:00 +00:00
addr-label-difference.ll
…
addr-mode-matcher-2.ll
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
2019-06-25 17:29:18 +00:00
addr-mode-matcher.ll
…
addr-of-ret-addr.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
address-type-promotion-constantexpr.ll
…
addrsig.ll
CodeGen: Add two more conditions for adding symbols to the address-significance table.
2018-08-24 20:37:09 +00:00
addsub-constant-folding.ll
[NFC][Codegen] Add/sub constant-folding: add scalar tests too
2019-05-31 08:23:48 +00:00
adx-commute.mir
[X86] Merge addcarryx/addcarry intrinsic into a single addcarry intrinsic.
2018-12-10 06:07:50 +00:00
adx-intrinsics-upgrade.ll
[X86] Simplify X86ISD::ADD/SUB if we don't use the result flag
2019-01-25 15:58:28 +00:00
adx-intrinsics.ll
[X86] Simplify X86ISD::ADD/SUB if we don't use the result flag
2019-01-25 15:58:28 +00:00
aes_intrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
alias-gep.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
alias-static-alloca.ll
[X86] Regenerate alias-static-alloca test checks to make D65354 diff easier
2019-07-31 12:27:47 +00:00
aliases.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
aligned-comm.ll
…
aligned-variadic.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
alignment-2.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
alignment.ll
…
all-ones-vector.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
alldiv-divdi3.ll
…
alloca-align-rounding-32.ll
…
alloca-align-rounding.ll
…
alloca-overaligned.ll
[Tests] Add a test showing how we handle overaligned allocas w/ no-realign-stack
2019-07-18 00:26:03 +00:00
allrem-moddi3.ll
…
and-encoding.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
and-load-fold.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
and-or-fold.ll
…
and-sink.ll
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
2018-02-23 11:50:42 +00:00
and-su.ll
[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st.
2019-02-04 17:28:18 +00:00
andimm8.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
anyext.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
anyregcc-crash.ll
RegAlloc: try to fail more gracefully when out of registers
2019-05-15 17:29:58 +00:00
anyregcc.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
apm.ll
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
2019-04-03 23:28:30 +00:00
AppendingLinkage.ll
…
arg_returned_bitcast.ll
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
2019-06-04 20:34:43 +00:00
arg-cast.ll
…
arg-copy-elide-win64.ll
[X86] Disable argument copy elision for arguments passed via pointers
2019-04-20 15:26:44 +00:00
arg-copy-elide.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
asm-invalid-register-class-crasher.ll
…
asm-label2.ll
…
asm-label.ll
…
asm-mismatched-types.ll
…
asm-modifier-P.ll
…
asm-modifier.ll
…
asm-reg-type-mismatch-avx512.ll
[X86] Add test case that was supposed to go with r360102.
2019-05-24 04:46:56 +00:00
asm-reg-type-mismatch.ll
…
asm-reject-reg-type-mismatch.ll
…
asm-reject-rex.ll
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
2018-03-06 18:56:33 +00:00
asm-reject-vk32-vk64.ll
[X86] Block i32/i64 for 'k' and 'Yk' in getRegForInlineAsmConstraint without avx512bw.
2019-04-15 18:39:45 +00:00
asm-reject-xmm16.ll
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
2018-03-06 18:56:33 +00:00
atom-call-reg-indirect-foldedreload32.ll
…
atom-call-reg-indirect-foldedreload64.ll
…
atom-call-reg-indirect.ll
…
atom-cmpb.ll
…
atom-fixup-lea1.ll
…
atom-fixup-lea2.ll
[X86] Stop accidentally running the Bonnell LEA fixup path on Goldmont.
2018-07-31 00:43:54 +00:00
atom-fixup-lea3.ll
…
atom-fixup-lea4.ll
…
atom-lea-addw-bug.ll
…
atom-lea-sp.ll
…
atom-pad-short-functions.ll
…
atom-sched.ll
[X86][NFC] Replace "<%s" with "< %s" in run-lines.
2019-01-27 15:36:35 +00:00
atom-shuf.ll
[X86] Regenerate atom pshufb test
2018-04-07 19:50:09 +00:00
atomic8.ll
…
atomic16.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
atomic32.ll
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
2019-05-03 19:06:57 +00:00
atomic64.ll
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
2019-05-03 19:06:57 +00:00
atomic128.ll
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
2019-03-13 18:48:50 +00:00
atomic6432.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
atomic-add.ll
[Tests] Auto update a test
2019-02-13 17:30:03 +00:00
atomic-dagsched.ll
…
atomic-eflags-reuse.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
atomic-flags.ll
…
atomic-fp.ll
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
2019-04-27 03:38:15 +00:00
atomic-idempotent.ll
Use an offset from TOS for idempotent rmw locked op lowering
2019-05-14 22:32:42 +00:00
atomic-load-store-wide.ll
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
2019-05-14 04:43:37 +00:00
atomic-load-store.ll
…
atomic-mi.ll
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
2019-04-11 19:19:42 +00:00
atomic-minmax-i6432.ll
[X86] Add FeatureCMOV explicitly to all CPUs that support it. Remove FeatureCMOV implication from Feature64Bit and FeatureSSE1
2018-08-26 18:29:33 +00:00
atomic-monotonic.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
atomic-non-integer.ll
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
2019-05-14 04:43:37 +00:00
atomic-op.ll
[Tests] Rename some test files for consistency
2019-02-13 17:23:11 +00:00
atomic-ops-ancient-64.ll
…
atomic-or.ll
…
atomic-pointer.ll
IR: Support parsing numeric block ids, and emit them in textual output.
2019-03-22 18:27:13 +00:00
atomic-unordered.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
atomicf128.ll
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
2019-03-13 18:48:50 +00:00
Atomics-64.ll
…
attribute-sections.ll
…
avg-mask.ll
[X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the default of promoting to v32i8.
2018-01-23 14:25:39 +00:00
avg.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avoid_complex_am.ll
…
avoid-lea-scale2.ll
…
avoid-loop-align-2.ll
…
avoid-loop-align.ll
…
avoid-sfb-g-no-change2.mir
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
2019-07-01 18:28:21 +00:00
avoid-sfb-g-no-change3.mir
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
2019-07-01 18:28:21 +00:00
avoid-sfb-g-no-change.mir
Resubmit r360436 "[X86] Avoid SFB - Fix inconsistent codegen with/without debug info"
2019-05-23 18:15:12 +00:00
avoid-sfb-kill-flags.mir
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
2018-04-26 13:16:11 +00:00
avoid-sfb-offset.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
avoid-sfb-overlaps.ll
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
2018-04-26 13:16:11 +00:00
avoid-sfb.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx1-logical-load-folding.ll
[x86] scalarize extract element 0 of FP math
2019-02-28 19:47:04 +00:00
avx2-arith.ll
[X86] Attempt to improve v32i8/v64i8 multiply lowering by applying the v16i8 non-avx2 algorithm to each 128-bit lane.
2018-11-19 18:32:53 +00:00
avx2-cmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx2-conversions.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx2-fma-fneg-combine.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
avx2-gather.ll
[X86] Lower avx2/avx512f gather intrinsics to X86MaskedGatherSDNode instead of going directly to MachineSDNode.:
2019-01-18 18:22:26 +00:00
avx2-intrinsics-canonical.ll
[X86] Regenerate tests. NFCI.
2019-07-10 17:22:31 +00:00
avx2-intrinsics-fast-isel.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
avx2-intrinsics-x86-upgrade.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
avx2-intrinsics-x86.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
avx2-logic.ll
[X86] Call SimplifyDemandedBits on conditions of X86ISD::SHRUNKBLEND
2019-01-10 19:05:34 +00:00
avx2-masked-gather.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx2-nontemporal.ll
[X86] Modify Nontemporal tests to avoid deadstore optimization.
2017-12-11 15:35:40 +00:00
avx2-phaddsub.ll
[X86][SSE] Fold add(shuffle(),shuffle()) to hadd on 'slow' targets (PR39920)
2019-05-09 17:45:01 +00:00
avx2-pmovxrm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx2-shift.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx2-vbroadcast.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx2-vbroadcasti128.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
avx2-vector-shifts.ll
[x86] split more v8f32/v8i32 shuffles in lowering
2019-02-18 16:46:12 +00:00
avx2-vperm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-adc-sbb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-any_extend_load.ll
[X86] Remove some code from combineShuffle that seems largely unnecessary with widening legalization.
2019-08-11 02:08:38 +00:00
avx512-arith.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
avx512-bugfix-23634.ll
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.
2017-12-08 09:48:44 +00:00
avx512-bugfix-25270.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
avx512-bugfix-26264.ll
[SelectionDAGBuilder] Add masked loads to PendingLoads rather than calling DAG.setRoot.
2018-07-26 23:22:11 +00:00
avx512-build-vector.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-calling-conv.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx512-cmp-kor-sequence.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512-cmp.ll
[x86] limit transform for select-of-fp-constants
2018-11-25 17:27:02 +00:00
avx512-cvt.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-cvttp2i.ll
[x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x86-specific nodes and isel patterns (PR37551)
2018-06-14 03:16:58 +00:00
avx512-ext.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-extract-subvector-load-store.ll
[X86] When lowering v1i1/v2i1/v4i1/v8i1 load/store with avx512f, but not avx512dq, use v16i1 as the intermediate mask type instead of v8i1.
2019-01-12 02:22:10 +00:00
avx512-extract-subvector.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-fma-commute.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-fma-intrinsics-upgrade.ll
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
2019-03-10 17:20:45 +00:00
avx512-fma-intrinsics.ll
[X86] Add the rounding control operand to the printing for some scalar FMA instructions.
2019-04-21 07:12:56 +00:00
avx512-fma.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
avx512-fsel.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
avx512-gather-scatter-intrin-deprecated.ll
[X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1 vector instead of a scalar
2019-01-15 20:12:33 +00:00
avx512-gather-scatter-intrin.ll
[X86] Lower avx2/avx512f gather intrinsics to X86MaskedGatherSDNode instead of going directly to MachineSDNode.:
2019-01-18 18:22:26 +00:00
avx512-gfni-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512-hadd-hsub.ll
[X86][AVX] Fold extract_subvector(broadcast(x)) -> broadcast(x) iff x has one use
2019-04-26 18:02:14 +00:00
avx512-i1test.ll
[MBP] Don't move bottom block before header if it can't reduce taken branches
2019-01-25 19:45:13 +00:00
avx512-inc-dec.ll
…
avx512-insert-extract_i1.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512-insert-extract.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
avx512-intel-ocl.ll
[WinEH] Allocate space in funclets stack to save XMM CSRs
2019-07-26 07:33:15 +00:00
avx512-intrinsics-canonical.ll
[X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nodes with an fneg input.
2018-07-05 02:52:56 +00:00
avx512-intrinsics-fast-isel.ll
[X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
2019-08-13 10:51:39 +00:00
avx512-intrinsics-upgrade.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-intrinsics-x86_64.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
avx512-intrinsics.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
avx512-load-store.ll
[X86] Add new patterns for masked scalar load/store to match clang's codegen from r331958.
2018-05-10 21:49:16 +00:00
avx512-load-trunc-store-i1.ll
[X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> (store (i8 X)).
2018-03-04 01:48:02 +00:00
avx512-logic.ll
[X86] Stop promoting vector and/or/xor/andn to vXi64.
2018-10-26 17:21:26 +00:00
avx512-mask-op.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-mask-spills.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-mask-zext-bugfix.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
avx512-masked_memop-16-8.ll
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches.
2019-07-31 22:58:15 +00:00
avx512-masked-memop-64-32.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
avx512-memfold.ll
[X86] In getScalarMaskingNode, replace scalar_to_vector with a bitcast to v8i1 and an extract_subvector to convert i8 to v1i1.
2018-11-21 07:01:22 +00:00
avx512-mov.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512-nontemporal.ll
[X86] Modify Nontemporal tests to avoid deadstore optimization.
2017-12-11 15:35:40 +00:00
avx512-pmovxrm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-regcall-Mask.ll
[X86] Fix register resizings for inline assembly register operands.
2018-09-13 20:33:56 +00:00
avx512-regcall-NoMask.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
avx512-rndscale.ll
[X86] Add full set of patterns for turning ceil/floor/trunc/rint/nearbyint into rndscale with loads, broadcast, and masking.
2018-07-17 05:48:48 +00:00
avx512-rotate.ll
[X86] Remove masking from avx512 rotate intrinsics. Use select in IR instead.
2018-06-30 01:32:04 +00:00
avx512-scalar_mask.ll
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
2018-07-12 00:29:56 +00:00
avx512-scalar.ll
[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.
2018-02-13 04:19:26 +00:00
avx512-scalarIntrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-select.ll
[x86] remove whitespace; NFC
2019-06-27 20:37:12 +00:00
avx512-shift.ll
[X86] Split immediate shifts tests. NFCI.
2019-01-04 14:56:10 +00:00
avx512-skx-insert-subvec.ll
[DAGCombiner] narrow vector binops when extraction is cheap
2018-10-30 14:14:34 +00:00
avx512-trunc.ll
[X86] Allow combineTruncateWithSat to use pack instructions for i16->i8 without AVX512BW.
2019-08-12 22:18:23 +00:00
avx512-unsafe-fp-math.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-vbroadcast.ll
[X86] Fix some tests using fcmp with undef arguments
2019-03-29 17:20:27 +00:00
avx512-vbroadcasti128.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512-vbroadcasti256.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-vec3-crash.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-vec-cmp.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512-vpclmulqdq.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512-vpermv3-commute.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-vpternlog-commute.ll
[X86] Remove masking from vpternlog intrinsics. Use a select in IR instead.
2018-05-21 20:58:09 +00:00
avx512-vselect-crash.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512-vselect.ll
[X86] Use vpmovq2m/vpmovd2m for truncate to vXi1 when possible.
2018-02-19 22:07:31 +00:00
avx512bf16-intrinsics.ll
[X86] Regenerate intrinsics tests. NFCI.
2019-07-11 10:40:23 +00:00
avx512bf16-vl-intrinsics.ll
[CodeGen] Move X86 tests under the X86 directory
2019-05-06 10:21:17 +00:00
avx512bw-arith.ll
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
2018-06-03 14:31:30 +00:00
avx512bw-intrinsics-canonical.ll
[X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (llvm)
2018-12-20 11:53:54 +00:00
avx512bw-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512bw-intrinsics-upgrade.ll
[X86] Remove and autoupgrade vpmovqd/vpmovwb intrinsics using trunc+select.
2019-01-21 08:16:59 +00:00
avx512bw-intrinsics.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
avx512bw-mask-op.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx512bw-mov.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx512bw-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512bw-vec-test-testn.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
avx512bwvl-arith.ll
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
2018-06-03 14:31:30 +00:00
avx512bwvl-intrinsics-canonical.ll
[X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (llvm)
2018-12-20 11:53:54 +00:00
avx512bwvl-intrinsics-fast-isel.ll
[X86] Fast-isel tests for lowered truncation intrinsics
2018-07-10 08:26:54 +00:00
avx512bwvl-intrinsics-upgrade.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512bwvl-intrinsics.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
avx512bwvl-mov.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
avx512bwvl-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512bwvl-vec-test-testn.ll
[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.
2018-10-25 18:23:48 +00:00
avx512cd-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512cd-intrinsics-upgrade.ll
[X86] Remove and autoupgrade vpconflict intrinsics that take a mask and passthru argument.
2019-01-26 06:27:01 +00:00
avx512cd-intrinsics.ll
[X86] Remove and autoupgrade vpconflict intrinsics that take a mask and passthru argument.
2019-01-26 06:27:01 +00:00
avx512cdvl-intrinsics-upgrade.ll
[X86] Remove and autoupgrade vpconflict intrinsics that take a mask and passthru argument.
2019-01-26 06:27:01 +00:00
avx512cdvl-intrinsics.ll
[X86] Remove and autoupgrade vpconflict intrinsics that take a mask and passthru argument.
2019-01-26 06:27:01 +00:00
avx512dq-intrinsics-fast-isel.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512dq-intrinsics-upgrade.ll
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
2019-03-10 17:20:45 +00:00
avx512dq-intrinsics.ll
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly
2019-03-10 17:20:45 +00:00
avx512dq-mask-op.ll
[DAGCombiner] don't hoist logic op if operands have other uses
2018-12-06 18:16:32 +00:00
avx512dqvl-intrinsics-fast-isel.ll
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
2018-06-27 15:57:53 +00:00
avx512dqvl-intrinsics-upgrade.ll
[X86][AVX] concat_vectors(scalar_to_vector(x),scalar_to_vector(x)) --> broadcast(x)
2019-02-23 18:34:05 +00:00
avx512dqvl-intrinsics.ll
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
2019-07-01 19:01:37 +00:00
avx512er-intrinsics.ll
[X86] In getScalarMaskingNode, replace scalar_to_vector with a bitcast to v8i1 and an extract_subvector to convert i8 to v1i1.
2018-11-21 07:01:22 +00:00
avx512f-256-set0.mir
[X86] Fix machineverifier error on avx512f-256-set0.mir
2019-05-29 17:02:27 +00:00
avx512f-vec-test-testn.ll
[X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching.
2018-02-19 19:23:31 +00:00
avx512ifma-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifma-intrinsics-upgrade.ll
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
2019-02-19 15:57:09 +00:00
avx512ifma-intrinsics.ll
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
2019-02-19 15:57:09 +00:00
avx512ifmavl-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifmavl-intrinsics-upgrade.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512ifmavl-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vbmi2-intrinsics-fast-isel.ll
Recommit r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target independent funnel shift intrinsics."
2019-01-07 21:00:32 +00:00
avx512vbmi2-intrinsics-upgrade.ll
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument.
2019-01-28 07:03:03 +00:00
avx512vbmi2-intrinsics.ll
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument.
2019-01-28 07:03:03 +00:00
avx512vbmi2vl-intrinsics-fast-isel.ll
Recommit r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target independent funnel shift intrinsics."
2019-01-07 21:00:32 +00:00
avx512vbmi2vl-intrinsics-upgrade.ll
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument.
2019-01-28 07:03:03 +00:00
avx512vbmi2vl-intrinsics.ll
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument.
2019-01-28 07:03:03 +00:00
avx512vbmi-intrinsics-fast-isel.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vbmi-intrinsics-upgrade.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vbmi-intrinsics.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vbmivl-intrinsics-fast-isel.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vbmivl-intrinsics-upgrade.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vbmivl-intrinsics.ll
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead.
2019-01-14 08:46:45 +00:00
avx512vl_vnni-intrinsics-upgrade.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vl_vnni-intrinsics.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vl-arith.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx512vl-intrinsics-canonical.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vl-intrinsics-fast-isel.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512vl-intrinsics-upgrade.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx512vl-intrinsics.ll
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument.
2019-01-28 07:03:03 +00:00
avx512vl-logic.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx512vl-mov.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
avx512vl-nontemporal.ll
[X86] Modify Nontemporal tests to avoid deadstore optimization.
2017-12-11 15:35:40 +00:00
avx512vl-vbroadcast.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
avx512vl-vec-cmp.ll
[X86] Stop swapping the operands of AVX512 setge.
2018-02-19 19:23:35 +00:00
avx512vl-vec-masked-cmp.ll
[X86] Move promotion of vector and/or/xor from legalization to DAG combine
2018-10-15 01:51:58 +00:00
avx512vl-vec-test-testn.ll
[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.
2018-10-25 18:23:48 +00:00
avx512vl-vpclmulqdq.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vlcd-intrinsics-fast-isel.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx512vlvp2intersect-intrinsics.ll
[X86] Regenerate intrinsics tests. NFCI.
2019-07-11 10:40:23 +00:00
avx512vnni-intrinsics-upgrade.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vnni-intrinsics.ll
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
2018-06-03 23:24:17 +00:00
avx512vp2intersect-intrinsics.ll
[X86] Regenerate intrinsics tests. NFCI.
2019-07-11 10:40:23 +00:00
avx512vpopcntdq-intrinsics.ll
[X86][AVX512] Cleanup intrinsics tests
2018-06-03 14:56:04 +00:00
avx-arith.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-basic.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
avx-bitcast.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-brcond.ll
Regenrate test results for avx-brcond.ll . NFC
2018-01-27 16:44:00 +00:00
avx-cast.ll
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
2018-07-12 13:29:41 +00:00
avx-cmp.ll
[X86] Fix some tests using fcmp with undef arguments
2019-03-29 17:20:27 +00:00
avx-cvt-2.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx-cvt-3.ll
Recommit r354363 "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
2019-02-23 21:41:42 +00:00
avx-cvt.ll
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.
2018-06-12 00:48:57 +00:00
avx-cvttp2si.ll
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
2018-06-27 18:16:40 +00:00
avx-fp2int.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
avx-gfni-intrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-insertelt.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
avx-intel-ocl.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx-intrinsics-fast-isel.ll
[x86] add movddup specialization for build vector lowering (PR37502)
2018-12-21 18:48:32 +00:00
avx-intrinsics-x86_64.ll
[X86][SSE] Cleanup AVX1 intrinsics tests
2018-06-02 21:35:48 +00:00
avx-intrinsics-x86-upgrade.ll
[x86] split 256-bit store of concatenated vectors
2019-06-04 16:40:04 +00:00
avx-intrinsics-x86.ll
[x86] split 256-bit store of concatenated vectors
2019-06-04 16:40:04 +00:00
avx-isa-check.ll
…
avx-load-store.ll
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
2019-06-21 19:10:21 +00:00
avx-logic.ll
[DAGCombiner] narrow vector binops when extraction is cheap
2018-10-30 14:14:34 +00:00
avx-minmax.ll
…
avx-select.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-shift.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-shuffle-x86_32.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-splat.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
avx-trunc.ll
[X86] Lower v16i16->v8i16 truncate using an 'and' with 255, an extract_subvector, and a packuswb instruction.
2018-11-18 17:59:28 +00:00
avx-unpack.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-varargs-x86_64.ll
…
avx-vbroadcast.ll
[X86][AVX] Add test case showing failure to fold broadcast load if its also used as a scalar
2019-04-02 10:31:00 +00:00
avx-vbroadcastf128.ll
[x86] fix uses check in broadcast transform (PR38949)
2018-09-16 15:41:56 +00:00
avx-vextractf128.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-vinsertf128.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
avx-vpclmulqdq.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
avx-vperm2x128.ll
[DAGCombiner] look through bitcasts when trying to narrow vector binops
2018-11-20 22:26:35 +00:00
avx-vzeroupper.ll
[x86] allow vector load narrowing with multi-use values
2018-11-10 20:05:31 +00:00
avx-win64-args.ll
…
avx-win64.ll
…
avx.ll
…
backpropmask.ll
[x86] restore test comment; NFC
2018-06-08 13:53:13 +00:00
bad-tls-fold.mir
[x86] Fix nasty bug in the x86 backend that is essentially impossible to
2018-02-07 23:59:14 +00:00
barrier-sse.ll
…
barrier.ll
[X86] Fix an old FIXME about folding the zero constant into the OR instruction we use for sequentially consistent fence in 32-bit mode without SSE2.
2018-12-23 01:54:43 +00:00
base-pointer-and-cmpxchg.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
basic-promote-integers.ll
…
bb_rotate.ll
[MBP] Factor out function hasViableTopFallthrough and enhancement
2019-02-22 18:04:37 +00:00
bc-extract.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
bigstructret2.ll
…
bigstructret.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bit-piece-comment.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
bit-test-shift.ll
…
bitcast2.ll
…
bitcast-and-setcc-128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
bitcast-and-setcc-256.ll
[X86][AVX] combineBitcastvxi1 - peek through bitops to determine size of original vector
2019-05-26 10:54:23 +00:00
bitcast-and-setcc-512.ll
[X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support
2019-04-07 10:40:01 +00:00
bitcast-i256.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bitcast-int-to-vector-bool-sext.ll
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
2019-07-04 10:17:10 +00:00
bitcast-int-to-vector-bool-zext.ll
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
2019-07-04 10:17:10 +00:00
bitcast-int-to-vector-bool.ll
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
2019-07-04 10:17:10 +00:00
bitcast-int-to-vector.ll
[X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
2018-10-11 20:36:06 +00:00
bitcast-mmx.ll
[X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead.
2018-01-05 20:55:12 +00:00
bitcast-setcc-128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
bitcast-setcc-256.ll
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
2019-05-13 04:03:35 +00:00
bitcast-setcc-512.ll
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
2019-06-26 09:50:11 +00:00
bitcast-vector-bool.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::TRUNCATE
2019-08-12 10:56:05 +00:00
bitcast.ll
…
bitcnt-false-dep.ll
[X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.
2018-04-19 19:25:24 +00:00
bitreverse.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
block-placement.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
block-placement.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
bmi2-x86_64.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
bmi2.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
bmi-intrinsics-fast-isel-x86_64.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
bmi-intrinsics-fast-isel.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
bmi-x86_64.ll
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR
2018-09-30 03:01:46 +00:00
bmi.ll
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
2019-07-10 22:44:32 +00:00
bool-ext-inc.ll
[DAGCombiner] sub X, 0/1 --> add X, 0/-1
2019-01-30 22:41:35 +00:00
bool-math.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
bool-simplify.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bool-vector.ll
[X86][SSE] Extract i1 elements from vXi1 bool vectors
2019-05-01 10:02:22 +00:00
bool-zext.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
br-fold.ll
[MinGW] [X86] Add stubs for references to data variables that might end up imported from a dll
2018-08-29 17:28:34 +00:00
branchfolding-catchpads.ll
…
branchfolding-debugloc.ll
[CodeGen] Add a new pass for PostRA sink
2018-03-22 20:06:47 +00:00
branchfolding-landingpads.ll
…
branchfolding-undef.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
brcond.ll
Regenrate brcond.ll test results. NFC
2018-01-27 16:57:15 +00:00
break-anti-dependencies.ll
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break-false-dep.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
broadcast-elm-cross-splat-vec.ll
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
2019-04-16 19:18:53 +00:00
broadcastm-lowering.ll
[X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input is a truncate from v16i8/v32i8.
2019-01-05 21:40:07 +00:00
bss_pagealigned.ll
[X86][NFC] Replace "<%s" with "< %s" in run-lines.
2019-01-27 15:36:35 +00:00
bswap_tree2.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
bswap_tree.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bswap-inline-asm.ll
…
bswap-rotate.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bswap-vector.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
bswap-wide-int.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bswap.ll
[DAGCombiner] don't hoist logic op if operands have other uses
2018-12-06 18:16:32 +00:00
bt.ll
[x86] make 8-bit shl undesirable
2019-04-08 13:58:50 +00:00
btc_bts_btr.ll
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
2019-04-12 06:49:28 +00:00
btq.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
bug26810.ll
Take into account the cost of local intervals when selecting split candidate.
2018-01-31 13:31:08 +00:00
bug37521.ll
DAG: Fix crash on shift with large shift amounts
2018-05-18 21:54:16 +00:00
build-vector-128.ll
[x86] add load fold patterns for movddup with vzext_load
2018-12-22 16:59:02 +00:00
build-vector-256.ll
[X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
2017-12-31 17:07:47 +00:00
build-vector-512.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
buildvec-extract.ll
[X86][SSE] Use PSLLDQ/PSRLDQ to mask out zeroable ends of a shuffle
2019-02-01 16:02:12 +00:00
buildvec-insertvec.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
bypass-slow-division-32.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
bypass-slow-division-64.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
bypass-slow-division-tune.ll
[X86] Autogenerate complete checks. NFC
2018-12-24 01:59:31 +00:00
byval2.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval3.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval4.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval5.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval6.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval7.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
byval-align.ll
…
byval-callee-cleanup.ll
…
byval.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
cache-intrinsic.ll
…
call-imm.ll
…
call-push.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
call-site-info-output.ll
[ISEL][X86] Tracking of registers that forward call arguments
2019-06-27 10:51:15 +00:00
callbr-asm-bb-exports.ll
[X86] Add test case for r361177.
2019-05-20 17:37:52 +00:00
callbr-asm-blockplacement.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm-branch-folding.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm-destinations.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm-errors.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm-label-addr.ll
[MC] Don't recreate a label if it's already used
2019-08-09 20:16:31 +00:00
callbr-asm-obj-file.ll
[CodeGen] Require a name for a block addr target
2019-08-09 20:18:30 +00:00
callbr-asm-outputs.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm.ll
[MC] Don't recreate a label if it's already used
2019-08-09 20:16:31 +00:00
cas.ll
…
cast-vsel.ll
[x86] split 256-bit vector selects if operands are vector concats
2019-06-16 14:04:49 +00:00
catch.ll
Align stubs for external and common global variables to pointer size.
2018-04-02 23:20:30 +00:00
catchpad-dynamic-alloca.ll
…
catchpad-lifetime.ll
…
catchpad-realign-savexmm.ll
[WinEH] Allocate space in funclets stack to save XMM CSRs
2019-07-26 07:33:15 +00:00
catchpad-regmask.ll
…
catchpad-reuse.ll
…
catchpad-weight.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
catchret-empty-fallthrough.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
catchret-fallthrough.ll
…
catchret-regmask.ll
…
cfi-inserter-cfg-with-merge.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-inserter-check-order.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
cfi-inserter-noreturnblock.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-inserter-verify-inconsistent-offset.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-inserter-verify-inconsistent-register.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-xmm.ll
[X86] Output cfi directives for saved XMM registers even if no GPRs are saved
2017-11-18 06:23:48 +00:00
cfi.ll
…
cfstring.ll
…
cgp-usubo.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
chain_order.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
change-compare-stride-1.ll
…
change-compare-stride-trickiness-0.ll
…
change-compare-stride-trickiness-1.ll
…
change-compare-stride-trickiness-2.ll
…
change-unsafe-fp-math.ll
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cldemote-intrinsic.ll
[X86] Introduce cldemote instruction
2018-04-13 07:35:08 +00:00
cleanuppad-inalloca.ll
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cleanuppad-large-codemodel.ll
Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models"
2018-07-23 21:14:35 +00:00
cleanuppad-realign.ll
…
clear_upper_vector_element_bits.ll
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED)
2019-07-22 12:44:10 +00:00
clear-highbits.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
clear-lowbits.ll
[DAGCombiner] re-enable truncation of binops
2018-12-08 16:07:38 +00:00
clflushopt.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
clwb.ll
[X86] Split up -march=icelake to -client & -server
2018-04-10 18:59:13 +00:00
clz.ll
[x86] regenerate checks; NFC
2019-02-21 15:30:28 +00:00
clzero.ll
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
2019-04-03 23:28:30 +00:00
cmov-double.ll
[x86] auto-generate complete checks for test; NFC
2019-03-22 15:33:47 +00:00
cmov-fp.ll
…
cmov-into-branch.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
cmov-promotion.ll
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
2019-06-26 05:12:53 +00:00
cmov.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
cmovcmov.ll
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cmp-fast-isel.ll
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cmp.ll
[X86] When promoting i16 compare with immediate to i32, try to use sign_extend for eq/ne if the input is truncated from a type with enough sign its.
2019-06-10 04:50:12 +00:00
cmpxchg8b_alloca_regalloc_handling.ll
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cmpxchg8b.ll
[X86] Make CMPXCHG16B feature imply CMPXCHG8B feature.
2019-08-08 18:11:17 +00:00
cmpxchg16b.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
cmpxchg-clobber-flags.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
cmpxchg-i1.ll
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cmpxchg-i128-i1.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
coal-sections.ll
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coalesce_commute_movsd.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
coalesce_commute_subreg.ll
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coalesce-dbg-value-subreg-rewrite.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
coalesce-dead-lanes.mir
[RegisterCoalescer] Do not assert when trying to remat dead values
2018-08-21 07:49:05 +00:00
coalesce-esp.ll
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coalesce-implicitdef.ll
…
coalescer-commute1.ll
…
coalescer-commute2.ll
…
coalescer-commute3.ll
…
coalescer-commute4.ll
…
coalescer-commute5.ll
…
coalescer-cross.ll
…
coalescer-dce2.ll
…
coalescer-dce.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
coalescer-identity.ll
…
coalescer-remat.ll
…
coalescer-subreg.ll
…
coalescer-win64.ll
…
code_placement_align_all.ll
…
code_placement_cold_loop_blocks.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
code_placement_eh.ll
…
code_placement_ignore_succ_in_inner_loop.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
code_placement_loop_rotation2.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
code_placement_loop_rotation3.ll
…
code_placement_loop_rotation.ll
…
code_placement_no_header_change.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
code_placement.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
code-model-elf-memset.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
code-model-elf.ll
[X86] Fix tls variable lowering issue with large code model
2019-02-24 19:33:37 +00:00
code-model-kernel.ll
Restore correct x86_64 EH encodings in kernel code model
2018-08-13 06:06:53 +00:00
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-cast.ll
…
codegen-prepare-crash.ll
…
codegen-prepare-extload.ll
…
codegen-prepare-replacephi.mir
test/CodeGen/X86/codegen-prepare-replacephi.mir requires a default triple
2019-03-27 20:43:47 +00:00
codegen-prepare-uaddo.ll
[CGP] add special-cases to form unsigned add with overflow (PR40486)
2019-02-24 15:31:27 +00:00
codegen-prepare.ll
…
codemodel.ll
[X86] Use PC-relative mode for the kernel code model
2019-04-13 21:39:28 +00:00
coff-comdat2.ll
…
coff-comdat3.ll
…
coff-comdat.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
coff-feat00.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
coff-no-dead-strip.ll
[CodeGen] Ignore private symbols in llvm.used for COFF
2018-01-26 00:15:25 +00:00
coff-weak.ll
…
coldcc64.ll
…
combine-64bit-vec-binop.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
combine-abs.ll
[X86] Improve vXi64 ISD::ABS codegen with SSE41+
2019-01-12 10:28:12 +00:00
combine-adc.ll
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483)
2019-02-25 11:19:37 +00:00
combine-add-ssat.ll
[DAGCombiner] Add add/sub saturation undef handling
2019-01-14 14:16:24 +00:00
combine-add-usat.ll
[X86] Lower ISD::UADDO to use the Z flag instead of C flag when the RHS is a constant 1 to encourage INC formation.
2019-02-03 07:25:06 +00:00
combine-add.ll
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
2019-05-30 20:36:54 +00:00
combine-addo.ll
[DAGCombiner] Enable UADDO/USUBO vector combine support
2019-03-06 16:11:03 +00:00
combine-adx.ll
[X86] Simplify X86ISD::ADD/SUB if we don't use the result flag
2019-01-25 15:58:28 +00:00
combine-and.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
combine-avx2-intrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
combine-avx-intrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
combine-bitreverse.ll
[SelectionDAG] computeKnownBits - support constant pool values from target
2019-05-24 10:03:11 +00:00
combine-bitselect.ll
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
2019-04-10 16:24:47 +00:00
combine-bswap.ll
[X86] Add basic bitreverse/bswap combine tests
2019-02-10 18:07:03 +00:00
combine-concatvectors.ll
[DAGCombiner] Simplify test case from r348759
2018-12-10 16:04:56 +00:00
combine-fabs.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll X86/combine-fabs.ll"
2019-06-13 19:24:34 +00:00
combine-fcopysign.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
2019-06-13 19:24:38 +00:00
combine-lds.ll
…
combine-mul.ll
[DAGCombine] visitMUL - allow shift by zero in MulByConstant.
2019-06-24 12:47:17 +00:00
combine-mulo.ll
[DAGCombiner] Enable SMULO/UMULO vector combine support (PR40442)
2019-03-06 11:04:21 +00:00
combine-multiplies.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
combine-or.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
combine-pmuldq.ll
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
2019-06-25 12:57:43 +00:00
combine-rotates.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
combine-sbb.ll
[x86] try harder to form LEA from ADD to avoid flag conflicts (PR40483)
2019-07-18 12:48:01 +00:00
combine-sdiv.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
combine-select.ll
[X86] Fix a potential crash that occur after r333419.
2018-05-29 20:04:10 +00:00
combine-sext-in-reg.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
combine-shl.ll
[DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds.
2019-06-20 14:42:27 +00:00
combine-smax.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-smin.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-sra.ll
[x86] split more v8f32/v8i32 shuffles in lowering
2019-02-18 16:46:12 +00:00
combine-srem.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
combine-srl.ll
[x86] split more v8f32/v8i32 shuffles in lowering
2019-02-18 16:46:12 +00:00
combine-sse41-intrinsics.ll
[X86][SSE] Swap X86ISD::BLENDV inputs with an inverted selection mask (PR42825)
2019-08-09 12:44:20 +00:00
combine-sub-ssat.ll
[DAGCombiner] Add (sub_sat x, x) -> 0 combine
2019-01-14 15:43:34 +00:00
combine-sub-usat.ll
[DAGCombiner] Add (sub_sat x, x) -> 0 combine
2019-01-14 15:43:34 +00:00
combine-sub.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
combine-subo.ll
[DAGCombiner] Enable UADDO/USUBO vector combine support
2019-03-06 16:11:03 +00:00
combine-testm-and.ll
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
2018-02-04 01:43:48 +00:00
combine-udiv.ll
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
2019-06-27 14:25:54 +00:00
combine-umax.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-umin.ll
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
2018-02-11 10:52:37 +00:00
combine-urem.ll
[DAGCombiner] Fold 0 div/rem X to 0
2018-10-31 14:18:57 +00:00
commandline-metadata.ll
Implement -frecord-command-line (-frecord-gcc-switches)
2018-12-14 15:38:15 +00:00
commute-3dnow.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
commute-blend-avx2.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
commute-blend-sse41.ll
[X86][SSE] Use pblendw for v4i32/v2i64 during isel.
2019-02-24 19:23:41 +00:00
commute-clmul.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
commute-fcmp.ll
[X86] Add a DAG combine to combine (sext (setcc)) with VLX
2018-01-09 18:14:22 +00:00
commute-intrinsic.ll
…
commute-two-addr.ll
…
commute-vpclmulqdq-avx512.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
commute-vpclmulqdq-avx.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
commute-xop.ll
[X86] Auto upgrade VPCOM/VPCOMU intrinsics to generic integer comparisons
2019-01-20 19:27:40 +00:00
commuted-blend-mask.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
compact-unwind.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
compare_folding.ll
…
compare-add.ll
…
compare-global.ll
…
compare-inf.ll
…
compiler_used.ll
…
complex-asm.ll
…
complex-fastmath.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
complex-fca.ll
…
computeKnownBits_urem.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
condbr_if.ll
[X86] Disable Condbr_merge pass
2018-11-16 19:35:00 +00:00
condbr_switch.ll
[X86] Disable Condbr_merge pass
2018-11-16 19:35:00 +00:00
conditional-indecrement.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
conditional-tailcall-samedest.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
conditional-tailcall.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
consecutive-load-shuffle.ll
[SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or
2018-11-26 20:16:33 +00:00
const-base-addr.ll
…
const-shift-of-constmasked.ll
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
2019-05-14 20:17:04 +00:00
constant-combines.ll
[DAGCombine] Prune unnused nodes.
2019-03-29 17:35:56 +00:00
constant-hoisting-and.ll
…
constant-hoisting-bfi.ll
…
constant-hoisting-cmp.ll
…
constant-hoisting-optnone.ll
…
constant-hoisting-shift-immediate.ll
…
constant-pool-remat-0.ll
…
constant-pool-sharing.ll
…
constpool.ll
…
constrained-fp80-trunc-ext.ll
[FPEnv] Lower STRICT_FP_EXTEND and STRICT_FP_ROUND nodes in preprocess phase of ISelLowering to mirror non-strict nodes on x86.
2019-06-14 16:28:55 +00:00
constructor.ll
[COFF] Implement constructor priorities
2017-11-28 08:07:18 +00:00
convert-2-addr-3-addr-inc64.ll
…
copy-eflags.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
copy-propagation.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
copysign-constant-magnitude.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
cpus-amd-no-x86_64.ll
Further split cpus test
2018-10-26 23:50:23 +00:00
cpus-amd.ll
[X86] AMD znver2 enablement
2019-02-26 16:55:10 +00:00
cpus-intel-no-x86_64.ll
Further split cpus test
2018-10-26 23:50:23 +00:00
cpus-intel.ll
[X86] Support -march=tigerlake
2019-08-12 01:29:46 +00:00
cpus-no-x86_64.ll
Further split cpus test
2018-10-26 23:50:23 +00:00
cpus-other.ll
Split invocations in CodeGen/X86/cpus.ll among multiple tests. (NFC)
2018-09-28 12:08:51 +00:00
crash-lre-eliminate-dead-def.ll
…
crash-nosse.ll
…
crash-O0.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
crash.ll
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
2017-11-30 12:12:19 +00:00
critical-anti-dep-breaker.ll
…
critical-edge-split-2.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cse-add-with-overflow.ll
…
cstring.ll
…
ctor-priority-coff.ll
[COFF] Implement llvm.global_ctors priorities for MSVC COFF targets
2018-09-07 23:07:55 +00:00
ctpop-combine.ll
[SDAG] expand ctpop != 1
2019-06-25 14:46:52 +00:00
cvt16.ll
…
cvtv2f32.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
cxx_tlscc64.ll
…
dag-fmf-cse.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
2019-06-13 19:24:38 +00:00
dag-merge-fast-accesses.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
dag-optnone.ll
…
dag-rauw-cse.ll
…
dag-update-nodetomatch.ll
…
dagcombine-and-setcc.ll
…
dagcombine-buildvector.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
dagcombine-cse.ll
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
2019-05-13 04:03:35 +00:00
dagcombine-select.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
dagcombine-shifts.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
dagcombine-tokenfactor-limit-crash.ll
Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
2019-06-03 01:30:19 +00:00
dagcombine-unsafe-math.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
darwin-bzero.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
darwin-no-dead-strip.ll
…
darwin-preemption.ll
Represent runtime preemption in the IR.
2017-10-26 15:00:26 +00:00
darwin-quote.ll
…
darwin-tls.ll
…
dbg-baseptr.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-changes-codegen-branch-folding2.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
dbg-changes-codegen-branch-folding.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
dbg-changes-codegen.ll
…
dbg-combine.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-line-0-no-discriminator.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
dbg-value-superreg-copy.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
DbgValueOtherTargets.test
…
debug-loclists.ll
[DWARF v5] Fix DWARF emitter and consumer to produce/expect a uleb for a location description's length.
2019-02-01 17:11:58 +00:00
debug-nodebug-crash.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debuginfo-locations-dce.ll
Fix line endings. NFCI.
2018-09-15 14:20:53 +00:00
debugloc-argsize.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debugloc-no-line-0.ll
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
deopt-bundles.ll
…
deopt-intrinsic-cconv.ll
[Debugify] Don't insert debug values after terminating deopts
2018-06-05 00:56:07 +00:00
deopt-intrinsic.ll
[MC] Suppress .Lcfi labels when emitting textual assembly
2017-10-10 00:57:36 +00:00
disable-tail-calls.ll
…
discontiguous-loops.ll
…
discriminate-mem-ops-missing-info.ll
[llvm] X86DiscriminateMemOps: insert debug info when missing
2019-05-10 00:12:51 +00:00
discriminate-mem-ops-skip-pfetch.ll
Skip over prefetches
2019-05-10 21:27:55 +00:00
discriminate-mem-ops.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
div8.ll
…
div-rem-pair-recomposition-signed.ll
[NFC][CodeGen][X86][AArch64] div-rem pair reconstruction tests (PR42673)
2019-07-25 16:39:57 +00:00
div-rem-pair-recomposition-unsigned.ll
[NFC][CodeGen][X86][AArch64] div-rem pair reconstruction tests (PR42673)
2019-07-25 16:39:57 +00:00
div-rem-simplify.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
divide-by-constant.ll
[DAGCombiner] After performing the division by constant optimization for a DIV or REM node, replace the users of the corresponding REM or DIV node if it exists.
2019-01-02 18:19:07 +00:00
divide-windows-itanium.ll
…
divrem8_ext.ll
Fixes removal of dead elements from PressureDiff (PR37252).
2018-09-26 10:42:41 +00:00
divrem.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
dllexport-x86_64.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
dllexport.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
dllimport-x86_64.ll
…
dllimport.ll
…
dollar-name.ll
…
domain-reassignment-implicit-def.ll
[X86DomainReassignment] Don't delete IMPLICIT_DEF nodes
2018-05-18 00:40:52 +00:00
domain-reassignment-test.ll
[X86DomainReassignment] Hopefully fix buildbot failure
2018-05-18 04:36:38 +00:00
domain-reassignment.mir
[X86] Regenerate checks for domain-reassignment.mir
2019-04-15 05:22:47 +00:00
dont-trunc-store-double-to-float.ll
…
dropped_constructor.ll
…
dwarf-comp-dir.ll
[DebugInfo] Support DWARF v5 source code embedding extension
2018-02-23 23:01:06 +00:00
dwarf-eh-prepare.ll
…
dwarf-headers.ll
[DWARFv5] Emit split type units in .debug_info.dwo.
2018-11-12 16:55:11 +00:00
dwarf-split-line-1.ll
[DWARFv5] Emit split type units in .debug_info.dwo.
2018-11-12 16:55:11 +00:00
dwarf-split-line-2.ll
[DWARFv5] Emit split type units in .debug_info.dwo.
2018-11-12 16:55:11 +00:00
dyn_alloca_aligned.ll
…
dyn-stackalloc.ll
…
dynamic-alloca-in-entry.ll
…
dynamic-alloca-lifetime.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
dynamic-allocas-VLAs.ll
…
dynamic-regmask.ll
[X86] Add phony registers for high halves of regs with low halves
2018-07-02 19:05:09 +00:00
DynamicCalleeSavedRegisters.ll
[X86] Regenerate callee-saved test checks to make D65354 diff easier
2019-07-31 12:29:07 +00:00
early-cfi-sections.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
early-ifcvt-crash.ll
[X86] Make Feature64Bit useful
2018-08-30 06:01:05 +00:00
early-ifcvt.ll
…
eh_frame.ll
…
eh-frame-unreachable.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
eh-label.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
eh-nolandingpads.ll
…
eh-null-personality.ll
…
eh-unknown.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
eip-addressing-i386.ll
[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.
2018-09-06 02:03:14 +00:00
element-wise-atomic-memory-intrinsics.ll
[Tests] Yet more combination of tests for unordered.atomic memset
2019-05-07 17:45:52 +00:00
elf-associated.ll
Revert r367501 "Create unique, but identically-named ELF sections..."
2019-08-07 20:45:23 +00:00
elf-comdat2.ll
…
elf-comdat.ll
…
emit-big-cst.ll
…
empty-function.ll
…
empty-functions.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
empty-struct-return-type.ll
…
emutls_generic.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
emutls-pic.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
emutls-pie.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
emutls.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
enqcmd-intrinsics.ll
[X86] Add ENQCMD instructions
2019-05-30 03:59:16 +00:00
epilogue-cfi-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
epilogue-cfi-no-fp.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
epilogue.ll
…
equiv_with_fndef.ll
…
equiv_with_vardef.ll
…
evex-to-vex-compress.mir
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.
2019-06-18 03:23:15 +00:00
exception-label.ll
…
exedeps-movq.ll
[x86] scalarize extract element 0 of FP math
2019-02-28 19:47:04 +00:00
exedepsfix-broadcast.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
expand-integer-x86_64-intrinsic-error.ll
[X86] Add test case for report_fatal_error added in r352699.
2019-02-04 21:24:15 +00:00
expand-opaque-const.ll
…
expand-post-ra-pseudo.mir
ExpandPostRAPseudos: Fix alldefsAreDead() not removing operands
2018-10-09 00:07:34 +00:00
expand-vr64-gr64-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
extend-set-cc-uses-dbg.ll
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
2019-03-19 19:01:34 +00:00
extend.ll
…
extended-fma-contraction.ll
…
extern_weak.ll
[COFF] Use COFF stubs for extern_weak functions
2019-05-07 23:06:21 +00:00
extmul64.ll
…
extmul128.ll
…
extract-bits.ll
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
2019-06-26 12:19:47 +00:00
extract-combine.ll
…
extract-concat.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
extract-extract.ll
…
extract-fp.ll
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
2019-05-25 16:44:29 +00:00
extract-insert.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
extract-lowbits.ll
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
2019-06-26 12:19:47 +00:00
extract-store.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
extractelement-fp.ll
[DAGCombiner] try to move bitcast after extract_subvector
2019-05-12 14:43:20 +00:00
extractelement-from-arg.ll
…
extractelement-index.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
extractelement-legalization-cycle.ll
…
extractelement-legalization-store-ordering.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
extractelement-load.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
extractelement-shuffle.ll
…
extractps.ll
…
f16c-intrinsics-fast-isel.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
f16c-intrinsics.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
fabs.ll
[SelectionDAG] Removing FABS folding from DAGCombiner
2018-03-30 15:42:52 +00:00
fadd-combines.ll
[DAGCombiner] exclude x*2.0 from normal negation profitability rules
2019-08-09 21:37:32 +00:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll
…
fast-cc-pass-in-regs.ll
…
fast-isel-abort-warm.ll
…
fast-isel-agg-constant.ll
…
fast-isel-args-fail2.ll
…
fast-isel-args-fail.ll
…
fast-isel-args.ll
…
fast-isel-atomic.ll
…
fast-isel-avoid-unnecessary-pic-base.ll
…
fast-isel-bail.ll
…
fast-isel-bc.ll
[X86][MMX] Improve handling of 64-bit MMX constants
2018-03-01 22:22:31 +00:00
fast-isel-bitcasts-avx512.ll
…
fast-isel-bitcasts-avx.ll
…
fast-isel-bitcasts.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-bool.ll
…
fast-isel-call-cleanup.ll
Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models"
2018-07-23 21:14:35 +00:00
fast-isel-call.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-cmp-branch2.ll
…
fast-isel-cmp-branch3.ll
…
fast-isel-cmp-branch.ll
…
fast-isel-cmp.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fast-isel-constant.ll
…
fast-isel-constpool.ll
Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models""
2018-06-28 17:56:43 +00:00
fast-isel-constrain-store-indexreg.ll
…
fast-isel-deadcode.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-divrem-x86-64.ll
…
fast-isel-divrem.ll
…
fast-isel-double-half-convertion.ll
…
fast-isel-emutls.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
fast-isel-expect.ll
…
fast-isel-extract.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
fast-isel-float-half-convertion.ll
…
fast-isel-fneg-kill.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
fast-isel-fneg.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
2019-06-13 19:24:38 +00:00
fast-isel-fold-mem.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
fast-isel-fptrunc-fpext.ll
[X86] Add more instructions to the memory folding tables using the autogenerated table as a guide.
2018-06-15 05:49:19 +00:00
fast-isel-gc-intrinsics.ll
[FastISel] Fix crash for gc.relocate lowring
2019-04-05 05:41:08 +00:00
fast-isel-gep.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
fast-isel-gv.ll
…
fast-isel-i1.ll
…
fast-isel-int-float-conversion-x86-64.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
fast-isel-int-float-conversion.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
fast-isel-load-i1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-mem.ll
…
fast-isel-movsbl-indexreg.ll
…
fast-isel-nontemporal.ll
[X86] Don't emit MOVNTDQA loads from fast-isel without SSE4.1.
2019-05-11 04:19:33 +00:00
fast-isel-noplt-pic.ll
FastISel: support no-PLT PIC calls on ELF x86_64
2017-12-15 00:32:09 +00:00
fast-isel-ret-ext.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
fast-isel-select-cmov2.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
fast-isel-select-cmov.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
fast-isel-select-cmp.ll
…
fast-isel-select-pseudo-cmov.ll
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
2019-05-11 16:00:28 +00:00
fast-isel-select-sse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-select.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
fast-isel-sext-zext.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
fast-isel-sext.ll
…
fast-isel-shift.ll
[X86] Enable 8-bit SHL to convert to LEA
2019-03-05 18:37:41 +00:00
fast-isel-sse12-fptoint.ll
…
fast-isel-stackcheck.ll
…
fast-isel-store.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fast-isel-tailcall.ll
…
fast-isel-tls.ll
…
fast-isel-trunc-kill-subreg.ll
…
fast-isel-uint-float-conversion-x86-64.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
fast-isel-uint-float-conversion.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
fast-isel-vecload.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-x32.ll
…
fast-isel-x86-64.ll
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
2019-03-19 19:01:34 +00:00
fast-isel-x86.ll
…
fast-isel.ll
…
fastcall-correct-mangling.ll
…
fastcc3struct.ll
…
fastcc-2.ll
…
fastcc-byval.ll
…
fastcc-sret.ll
…
fastcc.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-softfloat.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fastmath-float-half-conversion.ll
…
fcmove.ll
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction.
2019-02-04 04:15:10 +00:00
fcmp-constant.ll
[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC
2019-04-05 14:56:21 +00:00
fdiv-combine-vec.ll
[DAGCombiner] try repeated fdiv divisor transform before building estimate (2nd try)
2019-05-02 15:02:08 +00:00
fdiv-combine.ll
adding more fmf propagation for selects plus updated tests
2019-06-15 04:53:51 +00:00
fdiv.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
2019-06-13 19:24:38 +00:00
fentry-insertion.ll
[CodeGen] Remove operands from FENTRY_CALL
2018-10-25 21:12:15 +00:00
field-extract-use-trunc.ll
…
fildll.ll
…
file-directive.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
file-source-filename.ll
…
finite-libcalls.ll
Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly"
2019-02-04 04:15:02 +00:00
fixed-stack-di-mir.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
fixup-bw-copy.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
fixup-bw-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fixup-bw-inst.ll
…
fixup-bw-inst.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
fixup-lea.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
flags-copy-lowering.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
float-asmprint.ll
…
float-conv-elim.ll
…
floor-soft-float.ll
…
fltused_function_pointer.ll
Fix emission of _fltused for MSVC.
2019-01-24 18:34:00 +00:00
fltused_math.ll
Fix emission of _fltused for MSVC.
2019-01-24 18:34:00 +00:00
fltused.ll
Fix emission of _fltused for MSVC.
2019-01-24 18:34:00 +00:00
fma4-commute-x86.ll
[X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.
2018-07-06 07:14:41 +00:00
fma4-fneg-combine.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-fneg-combine.ll"
2019-06-13 19:25:03 +00:00
fma4-intrinsics-x86_64-folded-load.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fma4-intrinsics-x86-upgrade.ll
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
2018-07-05 18:43:58 +00:00
fma4-intrinsics-x86.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-intrinsics-x86.ll"
2019-06-13 19:24:54 +00:00
fma4-scalar-memfold.ll
[X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.
2018-07-06 07:14:41 +00:00
fma_patterns_wide.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns_wide.ll"
2019-06-13 19:25:09 +00:00
fma_patterns.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns.ll"
2019-06-13 19:25:06 +00:00
fma-commute-x86.ll
[X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart independent FMA and extractelement/insertelement.
2018-07-05 06:52:55 +00:00
fma-do-not-commute.ll
…
fma-fneg-combine.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-fneg-combine.ll"
2019-06-13 19:24:41 +00:00
fma-intrinsics-canonical.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/fma-intrinsics-canonical.ll"
2019-06-13 19:24:47 +00:00
fma-intrinsics-fast-isel.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
2019-06-13 19:24:51 +00:00
fma-intrinsics-phi-213-to-231.ll
…
fma-intrinsics-x86-upgrade.ll
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
2018-07-05 18:43:58 +00:00
fma-intrinsics-x86.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-intrinsics-x86.ll"
2019-06-13 19:24:57 +00:00
fma-phi-213-to-231.ll
…
fma-scalar-combine.ll
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-scalar-combine.ll"
2019-06-13 19:25:00 +00:00
fma-scalar-memfold.ll
[X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart independent FMA and extractelement/insertelement.
2018-07-05 06:52:55 +00:00
fma.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
fmaddsub-combine.ll
[X86] Add support for matching FMSUBADD from build_vector.
2018-03-15 06:14:55 +00:00
fmaxnum.ll
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
2019-05-25 16:44:29 +00:00
fmf-flags.ll
[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st.
2019-02-04 17:28:18 +00:00
fmf-propagation.ll
Propagate fmf for setcc in SDAG for select folds
2019-06-03 21:53:26 +00:00
fminnum.ll
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
2019-05-25 16:44:29 +00:00
fmsubadd-combine.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
fmul-combines.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
fnabs.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fmul-combines.ll fnabs.ll"
2019-06-13 19:25:12 +00:00
fold-add.ll
…
fold-and-shift-x86_64.ll
[X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl
2019-04-10 21:42:08 +00:00
fold-and-shift.ll
[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
2019-04-24 19:28:38 +00:00
fold-call-2.ll
…
fold-call-3.ll
[X86] If PreprocessISelDAG reorders a load before a call, make sure we remove dead nodes from the graph
2019-04-30 17:56:47 +00:00
fold-call-oper.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load-binops.ll
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
2019-06-11 04:30:53 +00:00
fold-load-unops.ll
[X86] Teach selectScalarSSELoad to not narrow volatile loads.
2019-06-27 05:51:56 +00:00
fold-load-vec.ll
[X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
2018-10-11 20:36:06 +00:00
fold-load.ll
[X86] Autogenerate complete checks. NFC
2018-12-16 18:35:54 +00:00
fold-mul-lohi.ll
…
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
fold-push.ll
…
fold-rmw-ops.ll
[X86] Teach isel for RMW binops to handle negate
2019-03-30 18:59:17 +00:00
fold-sext-trunc.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
fold-tied-op.ll
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
2019-04-10 18:00:41 +00:00
fold-vector-bv-crash.ll
…
fold-vector-sext-crash2.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
fold-vector-sext-crash.ll
[X86] Turn selects with constant condition into vector shuffles during DAG combine
2018-02-17 00:30:30 +00:00
fold-vector-sext-zext.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
fold-vector-shl-crash.ll
…
fold-vector-shuffle-crash.ll
…
fold-vector-trunc-sitofp.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
fold-vex.ll
[X86] Autogenerate checks. NFC
2018-10-15 05:31:24 +00:00
fold-xmm-zero.ll
…
fold-zext-trunc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
fops-windows-itanium.ll
…
force-align-stack-alloca.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
force-align-stack.ll
…
fp2sint.ll
…
fp128-calling-conv.ll
…
fp128-cast.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
fp128-compare.ll
[X86] Regenerate test checks in preparation for a patch. NFC
2018-11-05 19:45:37 +00:00
fp128-extract.ll
[X86] Regenerate fp128 test
2018-01-14 19:07:41 +00:00
fp128-g.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
fp128-i128.ll
[DAGCombiner] Reduce load widths of shifted masks
2018-08-21 10:26:59 +00:00
fp128-libcalls.ll
…
fp128-load.ll
…
fp128-select.ll
[X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned.
2018-07-02 17:01:54 +00:00
fp128-store.ll
…
fp_constant_op.ll
…
fp_load_cast_fold.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
fp_load_fold.ll
…
fp-arith.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
fp-cvt.ll
[X86] Mark FP32_TO_INT16_IN_MEM/FP32_TO_INT32_IN_MEM/FP32_TO_INT64_IN_MEM as clobbering EFLAGS to prevent mis-scheduling during conversion from SelectionDAG to MIR.
2019-02-19 22:37:00 +00:00
fp-double-rounding.ll
…
fp-elim-and-no-fp-elim.ll
…
fp-elim.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
fp-fast.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
fp-fold.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
fp-immediate-shorten.ll
…
fp-in-intregs.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
2019-06-13 19:25:16 +00:00
fp-intrinsics.ll
Add constrained fptrunc and fpext intrinsics.
2019-05-13 13:23:30 +00:00
fp-load-trunc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fp-logic-replace.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fp-logic.ll
[DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops
2018-10-09 23:20:11 +00:00
fp-select-cmp-and.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fp-stack-2results.ll
[NFC] This is a test for the commit access.
2019-05-06 08:31:18 +00:00
fp-stack-compare-cmov.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
2019-06-13 19:25:16 +00:00
fp-stack-compare.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
2019-06-13 19:25:16 +00:00
fp-stack-direct-ret.ll
…
fp-stack-O0-crash.ll
…
fp-stack-O0.ll
…
fp-stack-ret-conv.ll
…
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
…
fp-stack-set-st1.ll
…
fp-stack.ll
…
fp-trunc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fp-undef.ll
[SelectionDAG] fold constant with undef vector per element
2018-12-02 13:48:42 +00:00
fp-une-cmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fpcmp-soft-fp.ll
…
fpstack-debuginstr-kill.ll
Remove irrelevant references to legacy git repositories from
2019-01-15 16:18:52 +00:00
fptosi-constant.ll
[x86] add tests for convert-FP-to-integer with constants; NFC
2018-04-03 18:34:56 +00:00
frame-base.ll
…
frame-lowering-debug-intrinsic-2.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
frame-lowering-debug-intrinsic.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
frame-order.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
frameaddr.ll
…
frameregister.ll
…
frem-msvc32.ll
…
fsgsbase.ll
[X86] Regenerate fsgsbase intrinsic tests. NFCI.
2017-12-11 12:22:15 +00:00
fshl.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
fshr.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
fsxor-alignment.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
2019-06-13 19:25:16 +00:00
ftrunc.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
full-lsr.ll
…
funclet-layout.ll
…
function-alias.ll
…
function-subtarget-features-2.ll
…
function-subtarget-features.ll
…
funnel-shift-rot.ll
[X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
2019-03-14 16:53:24 +00:00
funnel-shift.ll
[DAGCombine] Simplify funnel shifts with undef/zero args to bitshifts
2019-02-10 17:04:00 +00:00
ga-offset2.ll
…
ga-offset.ll
…
gather-addresses.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
gcc_except_table_functions.ll
…
gcc_except_table.ll
…
gep-expanded-vector.ll
…
getelementptr.ll
[CGP] Fix GEP issue with out of range APInt constant values not fitting in int64_t
2018-08-13 12:10:09 +00:00
gfni-intrinsics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ghc-cc64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
ghc-cc.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
global-access-pie-copyrelocs.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
global-access-pie.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
global-fill.ll
…
global-sections-comdat.ll
…
global-sections-tls.ll
…
global-sections.ll
[MachO] Emit Weak ReadOnlyWithRel to ConstDataSection
2018-04-10 20:16:35 +00:00
gnu-seh-nolpads.ll
…
gpr-to-mask.ll
[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to guarantee zeroes in the upper bits of return.
2018-02-28 08:14:28 +00:00
greedy_regalloc_bad_eviction_sequence.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
gs-fold.ll
…
h-register-addressing-32.ll
…
h-register-addressing-64.ll
…
h-register-store.ll
…
h-registers-0.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
h-registers-1.ll
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
2018-05-01 19:51:15 +00:00
h-registers-2.ll
…
h-registers-3.ll
…
haddsub-2.ll
[x86] use 'nounwind' to remove test noise; NFC
2019-01-09 17:29:18 +00:00
haddsub-3.ll
[x86] make sure horizontal op and broadcast types match to simplify (PR41414)
2019-04-24 14:05:08 +00:00
haddsub-shuf.ll
[X86][AVX] Add broadcast(v4f64 hadd) test
2019-06-13 11:42:32 +00:00
haddsub-undef.ll
[X86][SSE] Relax use limits for lowerAddSubToHorizontalOp (PR32433)
2019-05-13 16:02:45 +00:00
haddsub.ll
[x86] add tests for reductions that might be better with more horizontal ops; NFC
2019-07-15 16:59:38 +00:00
half.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
handle-move.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
hhvm-cc.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
Use a got to access a hidden weak undefined on MachO.
2018-01-17 19:19:55 +00:00
hidden-vis-4.ll
…
hidden-vis-pic.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
hidden-vis.ll
…
hipe-cc64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
hipe-cc.ll
…
hipe-prologue.ll
…
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
2019-07-24 22:57:22 +00:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
2019-07-24 22:57:22 +00:00
hoist-common.ll
…
hoist-invariant-load.ll
Allow unordered loads to be considered invariant in CodeGen
2019-03-19 18:27:18 +00:00
hoist-spill-lpad.ll
…
hoist-spill.ll
[X86] Remove icmp undef from reduced tests
2019-03-24 17:02:08 +00:00
horizontal-reduce-smax.ll
[X86][SSE] Enable min/max partial reduction
2019-08-06 11:00:34 +00:00
horizontal-reduce-smin.ll
[X86][SSE] Enable min/max partial reduction
2019-08-06 11:00:34 +00:00
horizontal-reduce-umax.ll
[X86][SSE] Enable min/max partial reduction
2019-08-06 11:00:34 +00:00
horizontal-reduce-umin.ll
[X86][SSE] Enable min/max partial reduction
2019-08-06 11:00:34 +00:00
horizontal-shuffle-demanded.ll
[X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW SimplifyDemandedVectorElts as well.
2019-05-11 21:35:50 +00:00
horizontal-shuffle.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
huge-stack-offset2.ll
…
huge-stack-offset.ll
…
i1narrowfail.ll
…
i2k.ll
…
i16lshr8pat.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
i64-mem-copy.ll
[X86][AVX] EltsFromConsecutiveLoads - Add BROADCAST lowering support
2019-02-19 15:57:09 +00:00
i64-to-float.ll
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
2019-04-16 19:18:53 +00:00
i128-add.ll
[X86] getTargetConstantBitsFromNode - remove unnecessary getZExtValue() (PR42486)
2019-07-02 18:20:38 +00:00
i128-and-beyond.ll
…
i128-immediate.ll
…
i128-mul.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
i128-ret.ll
…
i128-sdiv.ll
…
i256-add.ll
Regenerate test
2018-10-26 12:33:56 +00:00
i386-setjmp-pic.ll
…
i386-shrink-wrapping.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
i386-tlscall-fastregalloc.ll
…
i486-fence-loop.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
i686-win-shrink-wrapping.ll
…
iabs.ll
[X86] Promote i16 SRA instructions to i32
2019-04-05 06:32:50 +00:00
icall-branch-funnel.ll
[CodeGen] Make branch funnels pass the machine verifier
2019-07-03 17:16:45 +00:00
icmp-opt.ll
[DagCombiner] Not all 'andn''s work with immediates.
2018-05-07 21:52:11 +00:00
ident-metadata.ll
…
ifunc-asm.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
illegal-bitfield-loadstore.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
illegal-insert.ll
…
illegal-vector-args-return.ll
…
immediate_merging64.ll
Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize."
2019-03-25 01:25:32 +00:00
immediate_merging.ll
Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize."
2019-03-25 01:25:32 +00:00
implicit-faultmap.ll
For faulting ops, include a comment w/the fault destination
2019-03-12 21:05:31 +00:00
implicit-null-check-negative.ll
Fix implicit null check with negative offset
2017-10-17 11:47:36 +00:00
implicit-null-check.ll
[ImplicitNullChecks] Support unordered atomic accesses
2019-03-13 03:25:20 +00:00
implicit-null-checks.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
implicit-null-chk-reg-rewrite.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
implicit-use-spill.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
imul-lea-2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
imul-lea.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
imul.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
inalloca-ctor.ll
…
inalloca-invoke.ll
…
inalloca-regparm.ll
…
inalloca-stdcall.ll
…
inalloca.ll
…
inc-of-add.ll
[NFC][Codegen][X86][AArch64][ARM][PowerPC] Recommit: Add test coverage for "add-of-inc" vs "sub-of-not"
2019-07-02 16:48:49 +00:00
inconsistent_landingpad.ll
[X86][NFC] Replace "<%s" with "< %s" in run-lines.
2019-01-27 15:36:35 +00:00
indirect-branch-tracking-r2.ll
[X86] [CET] Deal with return-twice function such as vfork, setjmp when
2019-05-22 00:50:21 +00:00
indirect-branch-tracking.ll
[X86] Enable the MachineVerifier by default
2018-10-29 16:57:43 +00:00
indirect-hidden.ll
…
init-priority.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
inline-0bh.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
inline-asm-2addr.ll
…
inline-asm-A-constraint.ll
Allow usage of X86-prefixes as separate instrs.
2018-01-17 10:12:06 +00:00
inline-asm-avx512f-v-constraint.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-avx512f-x-constraint.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
inline-asm-avx512vl-v-constraint-32bit.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-avx512vl-v-constraint.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-avx-v-constraint-32bit.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-avx-v-constraint.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-bad-constraint-n.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm-bad-modifier.ll
[X86] Don't crash on bad operand modifiers in inline assembly
2018-04-18 05:15:24 +00:00
inline-asm-default-clobbers.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
inline-asm-duplicated-constraint.ll
…
inline-asm-e-constraint.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm-error.ll
…
inline-asm-flag-clobber.ll
…
inline-asm-flag-output.ll
[X86] Fix copy-paste error in @ccz flag.
2019-02-21 15:28:31 +00:00
inline-asm-fpstack.ll
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
2019-02-15 21:59:33 +00:00
inline-asm-h.ll
…
inline-asm-i-constraint-i1.ll
[X86] Extend boolean arguments to inline-asm according to getBooleanType
2019-04-03 17:43:14 +00:00
inline-asm-imm-out-of-range.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm-modifier-c.ll
[AsmPrinter] refactor to support %c w/ GlobalAddress'
2019-04-26 18:45:04 +00:00
inline-asm-modifier-n.ll
…
inline-asm-modifier-q.ll
…
inline-asm-modifier-V.ll
[X86] Support 'V' register operand modifier
2018-02-08 20:06:05 +00:00
inline-asm-mrv.ll
…
inline-asm-multilevel-gep.ll
[TargetLowering] Handle multi depth GEPs w/ inline asm constraints
2019-05-13 17:27:44 +00:00
inline-asm-n-constraint.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm-out-regs.ll
…
inline-asm-pic.ll
…
inline-asm-ptr-cast.ll
[X86][NFC] Replace "<%s" with "< %s" in run-lines.
2019-01-27 15:36:35 +00:00
inline-asm-q-regs.ll
…
inline-asm-R-constraint.ll
…
inline-asm-sp-clobber-memcpy.ll
…
inline-asm-stack-realign2.ll
…
inline-asm-stack-realign3.ll
…
inline-asm-stack-realign.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-tied.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-x-scalar.ll
…
inline-asm.ll
…
inline-sse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
inlineasm-sched-bug.ll
Stricter check for the memory access.
2019-07-27 18:57:59 +00:00
inreg.ll
[FastISel] Disable local value sinking by default
2018-04-11 16:03:07 +00:00
ins_split_regalloc.ll
…
ins_subreg_coalesce-1.ll
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred.
2018-06-20 22:01:04 +00:00
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insert-into-constant-vector.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
insert-loaded-scalar.ll
[X86][AVX] Add VMOVDDUP-VPBROADCASTQ execution domain mapping
2019-02-01 21:41:30 +00:00
insert-positions.ll
…
insert-prefetch-inline.afdo
Revert "Revert r347596 "Support for inserting profile-directed cache prefetches""
2018-11-30 01:01:52 +00:00
insert-prefetch-inline.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
insert-prefetch-invalid-instr.afdo
Revert "Revert r347596 "Support for inserting profile-directed cache prefetches""
2018-11-30 01:01:52 +00:00
insert-prefetch-invalid-instr.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
insert-prefetch-other.afdo
Revert "Revert r347596 "Support for inserting profile-directed cache prefetches""
2018-11-30 01:01:52 +00:00
insert-prefetch.afdo
Revert "Revert r347596 "Support for inserting profile-directed cache prefetches""
2018-11-30 01:01:52 +00:00
insert-prefetch.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
insertelement-copytoregs.ll
…
insertelement-duplicates.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
insertelement-legalize.ll
…
insertelement-ones.ll
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
2019-07-06 17:59:51 +00:00
insertelement-shuffle.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
insertelement-var-index.ll
[X86][AVX] Add VMOVDDUP-VPBROADCASTQ execution domain mapping
2019-02-01 21:41:30 +00:00
insertelement-zero.ll
[X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.
2019-05-12 15:16:29 +00:00
insertps-combine.ll
[X86] XFormVExtractWithShuffleIntoLoad - handle shuffle mask scaling
2019-08-13 11:11:42 +00:00
insertps-from-constantpool.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
insertps-O0-bug.ll
…
insertps-unfold-load-bug.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
instr-symbols.mir
[x86] Fix test breaking on Darwin after r339962
2018-08-17 14:47:01 +00:00
int-intrinsic.ll
…
intersect-fma-fmf.ll
Guard FMF context by excluding some FP operators from FPMathOperator
2018-09-12 21:09:59 +00:00
interval-update-remat.ll
…
invalid-liveness.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
invalid-shift-immediate.ll
…
invpcid-intrinsic.ll
[x86] invpcid LLVM intrinsic
2018-05-25 06:32:05 +00:00
ipra-inline-asm.ll
RegUsageInfoCollector: Skip AMDGPU entry point functions
2019-07-05 23:33:43 +00:00
ipra-local-linkage.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
ipra-reg-alias.ll
[x86] promote all multiply i8 by constant to i32
2018-11-26 15:22:30 +00:00
ipra-reg-usage.ll
RegUsageInfoCollector: Skip AMDGPU entry point functions
2019-07-05 23:33:43 +00:00
ipra-transform.ll
…
is-constant.ll
Add a 'dynamic' parameter to the objectsize intrinsic
2019-01-30 20:34:35 +00:00
isel-optnone.ll
…
isel-sink2.ll
…
isel-sink3.ll
…
isel-sink.ll
…
isint.ll
…
isnan2.ll
…
isnan.ll
…
ispositive.ll
…
jump_sign.ll
[X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)
2019-07-11 15:56:33 +00:00
known-bits-vector.ll
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs
2019-07-15 18:17:23 +00:00
known-bits.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
known-signbits-vector.ll
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs
2019-07-15 18:17:23 +00:00
kshift.ll
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
2019-06-26 14:40:49 +00:00
label-annotation.ll
[codeview] Fix SDNode representation of annotation labels
2019-05-15 21:46:05 +00:00
label-heapallocsite.ll
Recommit "[MS] Emit S_HEAPALLOCSITE debug info in Selection DAG"
2019-08-07 22:49:40 +00:00
label-redefinition.ll
…
lack-of-signed-truncation-check.ll
[X86] Suppress load folding for add/sub with 128 immediate.
2019-03-06 07:36:36 +00:00
lakemont.ll
…
large-code-model-isel.ll
…
large-constants.ll
…
large-gep-chain.ll
…
large-gep-scale.ll
…
large-global.ll
…
large-pic-string.ll
[ELF] Fix large code model MIR verifier errors
2018-10-24 22:57:28 +00:00
late-address-taken.ll
[ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
2018-06-05 00:27:24 +00:00
late-remat-update-2.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
late-remat-update.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
ldzero.ll
…
lea-2.ll
[x86] update test checks; NFC
2019-04-15 17:38:47 +00:00
lea-3.ll
[x86] update test checks; NFC
2019-04-15 17:38:47 +00:00
lea-4.ll
[x86] update test checks; NFC
2019-04-15 17:38:47 +00:00
lea-5.ll
…
lea-dagdag.ll
[x86] try to widen 'shl' as part of LEA formation
2019-04-17 22:38:51 +00:00
lea-opt-cse1.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse2.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse3.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-cse4.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
lea-opt-memop-check-1.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
lea-opt-memop-check-2.ll
…
lea-opt-with-debug.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
lea-opt.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
lea-recursion.ll
…
lea.ll
[X86] Regenerate LEA codegen tests
2019-04-03 12:33:16 +00:00
leaf-fp-elim.ll
…
leaFixup32.mir
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
leaFixup64.mir
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
legalize-fmp-oeq-vector-select.ll
…
legalize-libcalls.ll
…
legalize-shift-64.ll
[DAGCombine] Prune unnused nodes.
2019-03-29 17:35:56 +00:00
legalize-shift.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
legalize-shl-vec.ll
[x86] make test immune to oversized shift simplification
2018-11-23 19:45:29 +00:00
legalize-sub-zero-2.ll
…
legalize-sub-zero.ll
…
legalize-types-remapid.ll
[DAG] Don't map a TableId to itself in the ReplacedValues map
2018-06-20 16:06:09 +00:00
legalize-vaarg.ll
[SelectionDAG] Legalize vaargs that require vector splitting
2019-06-18 12:24:02 +00:00
legalizedag_vec.ll
…
libcall-sret.ll
[X86] Do not generate __multi3 for mul i128 on X86
2017-10-21 02:26:00 +00:00
licm-dominance.ll
…
licm-nested.ll
[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.
2018-08-11 05:33:00 +00:00
licm-regpressure.ll
…
licm-symbol.ll
…
lifetime-alias.ll
[DAGCombiner] Fix invalid alias analysis.
2019-05-13 09:07:37 +00:00
limit-split-cost.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
limited-prec.ll
…
linux-preemption.ll
Represent runtime preemption in the IR.
2017-10-26 15:00:26 +00:00
lit.local.cfg
[lit] Delete empty lines at the end of lit.local.cfg NFC
2019-06-17 09:51:07 +00:00
live-out-reg-info.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
live-range-nosubreg.ll
…
liveness-local-regalloc.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
llc-override-mcpu-mattr.ll
…
llc-print-machineinstrs.mir
[llc] Error out when -print-machineinstrs is used with an unknown pass
2018-10-30 12:07:18 +00:00
llc-start-stop-instance.ll
Move llc-start-stop-instance to x86
2018-12-04 18:19:08 +00:00
llrint-conv-i32.ll
[CodeGen] Add lrint/llrint builtins
2019-05-28 20:47:44 +00:00
llrint-conv.ll
[CodeGen] Add lrint/llrint builtins
2019-05-28 20:47:44 +00:00
llround-conv-i32.ll
[CodeGen] Add lround/llround builtins
2019-05-16 13:15:27 +00:00
llround-conv.ll
[CodeGen] Add lround/llround builtins
2019-05-16 13:15:27 +00:00
load-combine-dbg.ll
Debug Info: Fix the SDLoc propagation for a DAGCombiner rule
2017-10-10 18:08:32 +00:00
load-combine.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
load-local-v3i1.ll
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
2019-03-27 20:35:56 +00:00
load-partial.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
load-scalar-as-vector.ll
[X86] Promote i16 SRA instructions to i32
2019-04-05 06:32:50 +00:00
load-slice.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
loadStore_vectorizer.ll
Reapply "[LSV] Refactoring + supporting bitcasts to a type of different size"
2018-07-20 20:10:04 +00:00
loc-remat.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
local_stack_symbol_ordering.ll
…
localescape.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
log2_not_readnone.ll
…
logical-load-fold.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
long-setcc.ll
…
longlong-deadload.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
loop-blocks.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
loop-hoist.ll
…
loop-rotate.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
loop-search.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
loop-strength-reduce2.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
…
loop-strength-reduce8.ll
…
loop-strength-reduce-2.ll
…
loop-strength-reduce-3.ll
…
loop-strength-reduce-crash.ll
…
loop-strength-reduce.ll
…
lower-bitcast.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
lower-vec-shift-2.ll
[X86][SSE] Avoid vector extraction/insertion for non-constant uniform shifts
2018-08-28 10:14:09 +00:00
lower-vec-shift.ll
[X86] Prefer VPBLENDD for v2i64/v4i64 blends with AVX2.
2019-03-03 00:18:07 +00:00
lower-vec-shuffle-bug.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
lrint-conv-i32.ll
[CodeGen] Add lrint/llrint builtins
2019-05-28 20:47:44 +00:00
lrint-conv.ll
[CodeGen] Add lrint/llrint builtins
2019-05-28 20:47:44 +00:00
lround-conv-i32.ll
[CodeGen] Add lround/llround builtins
2019-05-16 13:15:27 +00:00
lround-conv.ll
[CodeGen] Add lround/llround builtins
2019-05-16 13:15:27 +00:00
lrshrink.ll
[X86] Regenerate lrshrink test checks to make D65354 diff easier
2019-07-31 12:30:24 +00:00
lsr-crash-empty-uses.ll
Add a CHECK line for r337072.
2018-07-13 23:48:59 +00:00
lsr-delayed-fold.ll
…
lsr-i386.ll
…
lsr-interesting-step.ll
…
lsr-loop-exit-cond.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
lsr-negative-stride.ll
…
lsr-nonaffine.ll
…
lsr-normalization.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lsr-overflow.ll
…
lsr-quadratic-expand.ll
…
lsr-redundant-addressing.ll
…
lsr-reuse-trunc.ll
…
lsr-reuse.ll
…
lsr-sort.ll
…
lsr-static-addr.ll
[X86] Initial cleanups on the FixupLEAs pass. Separate Atom LEA creation from other LEA optimizations.
2019-04-30 17:56:28 +00:00
lsr-wrap.ll
…
lwp-intrinsics-x86_64.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
lwp-intrinsics.ll
[X86] Add a non-ambiguous check prefix to lwp-intrinsics.ll for the case when only the feature is specified and not the CPUs.
2019-05-08 19:20:53 +00:00
lzcnt-tzcnt.ll
[X86] Auto-generate checks. NFC
2018-02-06 18:18:49 +00:00
lzcnt-zext-cmp.ll
[X86] AMD znver2 enablement
2019-02-26 16:55:10 +00:00
lzcnt.ll
[X86] Regenerate LZCNT tests on x86/x32/x64 targets
2019-05-23 13:30:10 +00:00
macCatalyst.ll
[macCatalyst] Use macCatalyst pretty name in .build_version darwin
2019-07-12 22:06:08 +00:00
machine-combiner-int-vec.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
machine-combiner-int.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
machine-combiner.ll
[X86] Add avx512 command lines and test cases to machine-combiner.ll
2019-06-02 00:07:48 +00:00
machine-copy-prop.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-cp-debug.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
machine-cp.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
machine-cse.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
machine-outliner-debuginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
machine-outliner-disubprogram.ll
[MachineOutliner] Check the last instruction from the sequence when updating liveness
2018-07-14 09:40:01 +00:00
machine-outliner-noredzone.ll
[MachineOutliner] Test for X86FI->getUsesRedZone() as well as Attribute::NoRedZone
2018-04-03 23:32:41 +00:00
machine-outliner-tailcalls.ll
[MachineOutliner][X86] Use TAILJMPd64 instead of JMP_1 for TailCall construction
2018-07-30 09:59:33 +00:00
machine-outliner.ll
[MachineOutliner][NFC] Make outlined functions have internal linkage
2018-04-03 21:36:00 +00:00
machine-region-info.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
machine-sink-and-implicit-null-checks.ll
…
machine-sink.ll
…
machine-trace-metrics-crash.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
MachineBranchProb.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
MachineSink-CritEdge.ll
…
MachineSink-DbgValue.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
MachineSink-eflags.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
machinesink-merge-debuginfo.ll
[debug-info] Make a couple of tests more robust.
2019-06-27 15:53:07 +00:00
machinesink-null-debuginfo.ll
[debug-info] Make a couple of tests more robust.
2019-06-27 15:53:07 +00:00
MachineSink-PHIUse.ll
…
MachineSink-SubReg.ll
…
macho-comdat.ll
…
macho-trap.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
madd.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
mangle-question-mark.ll
[IR] Avoid the need to prefix MS C++ symbols with '\01'
2018-03-16 20:13:32 +00:00
mask-negated-bool.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
masked_compressstore.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
masked_expandload.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
masked_gather_scatter_widen.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
masked_gather_scatter.ll
[SelectionDAG][X86] Move setcc mask splitting for mload/mstore/mgather/mscatter from DAGCombiner to the type legalizer.
2019-08-08 21:14:08 +00:00
masked_gather.ll
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches.
2019-07-31 22:58:15 +00:00
masked_load.ll
[SelectionDAG][X86] Move setcc mask splitting for mload/mstore/mgather/mscatter from DAGCombiner to the type legalizer.
2019-08-08 21:14:08 +00:00
masked_store_trunc_ssat.ll
[X86] Allow combineTruncateWithSat to use pack instructions for i16->i8 without AVX512BW.
2019-08-12 22:18:23 +00:00
masked_store_trunc_usat.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
masked_store_trunc.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
masked_store.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
masked-iv-safe.ll
…
masked-iv-unsafe.ll
…
maskmovdqu.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
materialize.ll
…
mature-mc-support.ll
…
mbp-false-cfg-break.ll
…
mcinst-avx-lowering.ll
…
mcinst-lowering.ll
…
mcu-abi.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
mem-intrin-base-reg.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mem-promote-integers.ll
…
membarrier.ll
…
memcmp-mergeexpand.ll
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
2019-06-26 12:13:13 +00:00
memcmp-minsize.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
memcmp-optsize.ll
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
2019-06-26 12:13:13 +00:00
memcmp.ll
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
2019-06-26 12:13:13 +00:00
memcpy-2.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
memcpy-from-string.ll
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
2018-12-13 09:56:19 +00:00
memcpy-struct-by-value.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
memcpy.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
mempcpy-32.ll
…
mempcpy.ll
…
memset64-on-x86-32.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-2.ll
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
2018-12-13 09:56:19 +00:00
memset-3.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-nonzero.ll
[x86] split more 256-bit stores of concatenated vectors
2019-06-05 16:40:57 +00:00
memset-sse-stack-realignment.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-zero.ll
[Tests] Expand coverage of small memset zero idioms
2019-05-07 23:48:42 +00:00
memset.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
merge_store_duplicated_loads.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
merge_store.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
merge-consecutive-loads-128.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
merge-consecutive-loads-256.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
merge-consecutive-loads-512.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
merge-consecutive-stores-i1.ll
…
merge-consecutive-stores-nt.ll
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
2019-07-09 19:55:28 +00:00
merge-consecutive-stores.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
merge-sp-update-lea.ll
…
merge-sp-updates-cfi.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
merge-store-constants.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
merge-store-partially-alias-loads.ll
[CodeGen] Use MIR syntax for MachineMemOperand printing
2018-03-14 21:52:13 +00:00
merge-vector-stores-scale-idx-crash.ll
Revert "Revert r342183 "[DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.""
2018-09-17 14:40:13 +00:00
MergeConsecutiveStores.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
mfence.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
midpoint-int-vec-128.ll
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
2019-07-23 15:35:55 +00:00
midpoint-int-vec-256.ll
[x86] narrow extract subvector of vector select
2019-06-07 13:17:46 +00:00
midpoint-int-vec-512.ll
[NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)
2019-03-05 20:18:47 +00:00
midpoint-int.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
min-legal-vector-width.ll
[X86] Improve codegen of v8i64->v8i16 and v16i32->v16i8 truncate with avx512vl, avx512bw, min-legal-vector-width<=256 and prefer-vector-width=256
2019-08-08 21:36:47 +00:00
mingw-alloca.ll
…
mingw-comdats-xdata.ll
[COFF] Fix assembly output of comdat sections without an attached symbol
2018-07-23 22:15:19 +00:00
mingw-comdats.ll
[mingw] Use unmangled name after the $ in the section name
2018-11-21 22:01:10 +00:00
mingw-refptr.ll
[MinGW] [X86] Add stubs for references to data variables that might end up imported from a dll
2018-08-29 17:28:34 +00:00
misaligned-memset.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
misched_phys_reg_assign_order.ll
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
2019-04-11 19:19:42 +00:00
misched-aa-colored.ll
…
misched-aa-mmos.ll
…
misched-balance.ll
…
misched-code-difference-with-debug.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
misched-copy.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
misched-crash.ll
…
misched-fusion.ll
…
misched-ilp.ll
…
misched-matmul.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
misched-matrix.ll
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
2018-04-05 20:04:06 +00:00
misched-new.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mmx-arg-passing-x86-64.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
mmx-arg-passing.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
mmx-arith.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
mmx-bitcast-fold.ll
…
mmx-bitcast.ll
[X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead.
2018-01-05 20:55:12 +00:00
mmx-build-vector.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
mmx-coalescing.ll
[DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016)
2018-10-21 20:13:29 +00:00
mmx-copy-gprs.ll
…
mmx-cvt.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
mmx-fold-load.ll
[X86][MMX] Improve MMX constant generation
2018-01-16 14:21:28 +00:00
mmx-fold-zero.ll
[X86][MMX] Add support for MMX zero vector creation
2018-01-15 22:32:40 +00:00
mmx-intrinsics.ll
…
mmx-only.ll
…
mod128.ll
…
movbe.ll
…
movddup-load-fold.ll
[x86] add load fold patterns for movddup with vzext_load
2018-12-22 16:59:02 +00:00
movdir-intrinsic-x86_64.ll
[X86] movdiri and movdir64b instructions
2018-05-01 10:01:16 +00:00
movdir-intrinsic-x86.ll
[X86] movdiri and movdir64b instructions
2018-05-01 10:01:16 +00:00
move_latch_to_loop_top.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
movfs.ll
…
movgs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
movmsk-cmp.ll
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
2019-06-26 09:50:11 +00:00
movmsk.ll
[DAGCombine] Prune unnused nodes.
2019-03-29 17:35:56 +00:00
movntdq-no-avx.ll
…
movpc32-check.ll
Remove irrelevant references to legacy git repositories from
2019-01-15 16:18:52 +00:00
movtopush64.ll
X86CallFrameOptimization: Recognize 'store 0/-1 using and/or' idioms
2017-10-24 12:13:05 +00:00
movtopush.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
movtopush.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
ms-inline-asm-avx512.ll
…
ms-inline-asm-redundant-clobber.ll
[MachineInstr] In addRegisterKilled and addRegisterDead, don't remove operands from inline assembly instructions if they have an associated flag operand.
2018-09-13 20:51:27 +00:00
ms-inline-asm.ll
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mul64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
mul128_sext_loop.ll
…
mul128.ll
[X86] Add PR13897 test case (i128 mul on i686)
2019-03-22 17:52:21 +00:00
mul-constant-i8.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
mul-constant-i16.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
mul-constant-i32.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
mul-constant-i64.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
mul-constant-result.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
mul-i256.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
mul-i512.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
mul-i1024.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
mul-legalize.ll
…
mul-remat.ll
…
mul-shift-reassoc.ll
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mulo-pow2.ll
[SDAG] Recursively legalize both vector mulo results
2019-05-10 20:42:48 +00:00
muloti.ll
[SelectionDAG] Improve the legalisation lowering of UMULO.
2018-08-16 18:39:39 +00:00
mult-alt-generic-i686.ll
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mult-alt-generic-x86_64.ll
…
mult-alt-x86.ll
…
multiple-loop-post-inc.ll
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multiple-return-values-cross-block.ll
…
mulvi32.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
mulx32.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
mulx64.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
musttail-fastcall.ll
[X86] Disable use of zmm registers for varargs musttail calls under prefer-vector-width=256 and min-legal-vector-width=256.
2019-08-12 17:43:26 +00:00
musttail-indirect.ll
[X86] Add *SP to tailcall register class to fix verifier error
2018-10-24 21:09:34 +00:00
musttail-thiscall.ll
[X86] Add *SP to tailcall register class to fix verifier error
2018-10-24 21:09:34 +00:00
musttail-varargs.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
musttail.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
mwaitx.ll
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
2019-04-03 23:28:30 +00:00
named-reg-alloc.ll
…
named-reg-notareg.ll
…
nancvt.ll
…
narrow_op-1.ll
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narrow-shl-cst.ll
[X86] Don't turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the original AND can represented by MOVZX.
2019-04-20 04:38:53 +00:00
narrow-shl-load.ll
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neg_cmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
neg_fp.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
2019-06-13 19:24:51 +00:00
neg-of-3ops-lea.ll
[X86][Codegen] Add missed pattern that may be a lea+neg
2019-06-08 19:38:14 +00:00
neg-shl-add.ll
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negate-add-zero.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
negate-i1.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
negate-shift.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
negate.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
negative_zero.ll
…
negative-offset.ll
[NFC][X86] Autogenerate negative-offset.ll test
2019-05-22 15:34:43 +00:00
negative-sin.ll
Go back to sometimes assuming intristics are local.
2018-03-10 02:42:14 +00:00
negative-stride-fptosi-user.ll
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negative-subscript.ll
…
new-remat.ll
…
newline-and-quote.ll
…
no-and8ri8.ll
…
no-cmov.ll
…
no-plt-libcalls.ll
Add, and infer, a nofree function attribute
2019-07-08 15:57:56 +00:00
no-plt.ll
GOTPCREL references must always use RIP.
2018-04-10 22:50:05 +00:00
no-prolog-kill.ll
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no-sse2-avg.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
no-stack-arg-probe.ll
Support for the mno-stack-arg-probe flag
2018-02-23 13:46:25 +00:00
nobt.ll
…
nocf_check.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
nocx16.ll
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nomovtopush.ll
[X86] Fix stack probe issue on windows32.
2019-08-10 02:49:02 +00:00
non-lazy-bind.ll
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non-unique-sections.ll
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non-value-mem-operand.mir
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
2019-06-18 03:23:11 +00:00
nonconst-static-ev.ll
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nonconst-static-iv.ll
…
nontemporal-2.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
nontemporal-3.ll
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)
2019-06-17 18:20:04 +00:00
nontemporal-loads-2.ll
[X86][SSE] Add tests for underaligned nt loads
2019-06-17 14:38:17 +00:00
nontemporal-loads.ll
[X86][SSE] Swap X86ISD::BLENDV inputs with an inverted selection mask (PR42825)
2019-08-09 12:44:20 +00:00
nontemporal.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
noreturn-call.ll
…
norex-subreg.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
nosse-error1.ll
…
nosse-error2.ll
…
nosse-varargs.ll
…
nosse-vector.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
not-and-simplify.ll
[DAGCombine] Prune unnused nodes.
2019-03-29 17:35:56 +00:00
note-cet-property.ll
Update the pr_datasz of .note.gnu.property section.
2019-01-04 21:25:01 +00:00
note-sections.ll
…
null-streamer.ll
[X86] Fix MCNullStreamer support for modules with a CodeView flag
2018-11-15 15:17:15 +00:00
O0-pipeline.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
O3-pipeline.ll
[MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.
2019-07-19 12:58:16 +00:00
objc-gc-module-flags.ll
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object-size.ll
…
oddshuffles.ll
[X86][SSE] matchBinaryPermuteShuffle - split INSERTPS combines
2019-08-08 13:23:53 +00:00
oddsubvector.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
2019-06-27 21:52:10 +00:00
opaque-constant-asm.ll
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opt_phis2.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
opt_phis.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
opt-ext-uses.ll
…
opt-shuff-tstore.ll
…
optimize-max-0.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
optimize-max-1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
optimize-max-2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
optimize-max-3.ll
…
or-address.ll
…
or-branch.ll
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
2019-06-25 17:29:18 +00:00
or-lea.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
osx-private-labels.ll
…
overflow-intrinsic-setcc-fold.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
overflow.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
overlap-shift.ll
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packed_struct.ll
…
packss.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
paddus.ll
[X86] Add DAG combine to fold any_extend_vector_inreg+truncstore to an extractelement+store
2019-07-31 22:43:08 +00:00
palignr.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
parity.ll
[X86] Add a DAG combine for the __builtin_parity idiom used by clang to enable better codegen
2018-08-03 18:00:29 +00:00
partial-fold32.ll
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partial-fold64.ll
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partition.ll
Add IR support, ELF section and user documentation for partitioning feature.
2019-05-29 03:29:01 +00:00
pass-three.ll
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patchable-prologue.ll
[CodeGen] Remove out operands from PATCHABLE_OP
2018-10-26 13:37:25 +00:00
patchpoint-invoke.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
patchpoint-verifiable.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
patchpoint-webkit_jscc.ll
[MC] Suppress .Lcfi labels when emitting textual assembly
2017-10-10 00:57:36 +00:00
patchpoint.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
pause.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
peep-setb.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
peep-test-0.ll
…
peep-test-1.ll
…
peep-test-2.ll
…
peep-test-3.ll
…
peep-test-4.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
peephole-cvt-sse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
peephole-fold-movsd.ll
[X86] Regenerate load fold peephole test.
2019-07-04 12:33:37 +00:00
peephole-fold-testrr.mir
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
2019-06-25 17:29:18 +00:00
peephole-multiple-folds.ll
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peephole-na-phys-copy-folding.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
peephole-recurrence.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
peephole.mir
Revert r359392 and r358887
2019-05-06 19:29:24 +00:00
personality_size.ll
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personality.ll
…
phaddsub-extract.ll
[DAGCombine] matchBinOpReduction - add partial reduction matching
2019-07-24 17:29:56 +00:00
phaddsub-undef.ll
[X86][SSE] LowerBuildVectorv4x32 - don't insert MOVQ for undef elts
2019-05-13 16:10:11 +00:00
phaddsub.ll
[X86] isHorizontalBinOp - add extract_subvector(shuffle(x)) handling (PR39921)
2019-06-02 15:47:49 +00:00
phi-bit-propagation.ll
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phi-immediate-factoring.ll
…
phielim-split.ll
…
phys_subreg_coalesce-2.ll
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phys_subreg_coalesce-3.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
phys_subreg_coalesce.ll
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phys-reg-local-regalloc.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
physreg-pairs-error.ll
[X86] Fix register resizings for inline assembly register operands.
2018-09-13 20:33:56 +00:00
physreg-pairs.ll
[X86] Fix register resizings for inline assembly register operands.
2018-09-13 20:33:56 +00:00
pic_jumptable.ll
…
pic-load-remat.ll
[X86] Update PADDSW/PSUBSW intrinsic usage with generic saturated intrinsics.
2018-12-20 11:14:56 +00:00
pic.ll
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pie.ll
…
pku.ll
[X86] Remove CustomInserters for RDPKRU/WRPKRU. Use some custom lowering and new ISD opcodes instead.
2019-04-04 00:28:49 +00:00
pmaddubsw.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
pmovext.ll
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pmovsx-inreg.ll
[x86] split 256-bit store of concatenated vectors
2019-06-04 16:40:04 +00:00
pmul.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
pmulh.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
pmulld.ll
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pointer-vector.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
pop-stack-cleanup-msvc.ll
[X86] Don't clobber reserved registers with stack adjustments
2017-11-07 08:50:21 +00:00
pop-stack-cleanup.ll
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popcnt.ll
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
2019-07-04 22:53:57 +00:00
post-ra-sched-with-debug.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
post-ra-sched.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
postalloc-coalescing.ll
…
postra-ignore-dbg-instrs.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
postra-licm.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
pow.75.ll
[DAGCombine] Optimize pow(X, 0.75) to sqrt(X) * sqrt(sqrt(X))
2019-02-08 19:50:58 +00:00
pow.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
powi.ll
[X86] Regenerate powi tests to include i686 x87/sse targets
2019-03-22 18:04:28 +00:00
pr1462.ll
…
pr1489.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
pr1505.ll
…
pr1505b.ll
…
pr2177.ll
…
pr2182.ll
…
pr2326.ll
…
pr2585.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr2656.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
pr2659.ll
…
pr2849.ll
…
pr2924.ll
…
pr2982.ll
…
pr3154.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
pr3216.ll
…
pr3241.ll
…
pr3243.ll
…
pr3244.ll
…
pr3250.ll
…
pr3317.ll
…
pr3366.ll
…
pr3457.ll
…
pr3522.ll
…
pr5145.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
pr7882.ll
…
pr9127.ll
…
pr9517.ll
Add inline asm aliasing test.
2018-07-23 20:19:10 +00:00
pr9743.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
pr10068.ll
…
pr10475.ll
…
pr10499.ll
…
pr10523.ll
…
pr10524.ll
…
pr10525.ll
…
pr10526.ll
…
pr11202.ll
…
pr11334.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
pr11415.ll
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
2019-05-03 19:06:57 +00:00
pr11468.ll
…
pr11985.ll
[X86] Make Feature64Bit useful
2018-08-30 06:01:05 +00:00
pr11998.ll
…
pr12360.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
pr12889.ll
…
pr13209.ll
…
pr13220.ll
…
pr13458.ll
…
pr13577.ll
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction.
2019-02-04 04:15:10 +00:00
pr13859.ll
…
pr13899.ll
…
pr14088.ll
[X86] Regenerate PR14088 test. NFCI.
2018-07-07 20:08:27 +00:00
pr14098.ll
…
pr14161.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
pr14204.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr14314.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr14333.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
pr14562.ll
…
pr15267.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr15296.ll
…
pr15309.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr15705.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
pr15981.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
pr16031.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr16360.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr16807.ll
…
pr17546.ll
…
pr17631.ll
…
pr17764.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr18014.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr18054.ll
…
pr18162.ll
…
pr18344.ll
[X86][SSE] Don't colaesce v4i32 extracts
2018-01-26 17:11:34 +00:00
pr18846.ll
…
pr19049.ll
…
pr20011.ll
[SelectionDAG] Fix codegen of vector stores with non byte-sized elements.
2018-01-20 16:05:10 +00:00
pr20012.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr20020.ll
…
pr20088.ll
…
pr21099.ll
…
pr21792.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr22019.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
pr22103.ll
…
pr22338.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
pr22473.ll
[X86] Add test case for PR22473
2019-03-08 19:16:26 +00:00
pr22774.ll
[x86] allow vector load narrowing with multi-use values
2018-11-10 20:05:31 +00:00
pr22970.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr23103.ll
Revert "Regenerate expected test results for test/CodeGen/X86/pr23103.ll . NFC"
2018-06-04 21:49:23 +00:00
pr23246.ll
[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
2018-06-05 06:20:06 +00:00
pr23273.ll
…
pr23603.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr23664.ll
[x86] allow 8-bit adds to be promoted by convertToThreeAddress() to form LEA
2018-12-12 17:58:27 +00:00
pr24139.ll
…
pr24374.ll
…
pr24602.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr25828.ll
…
pr26350.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr26625.ll
…
pr26652.ll
…
pr26757.ll
…
pr26835.ll
…
pr26870.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
pr27071.ll
…
pr27202.ll
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
2019-07-04 22:53:57 +00:00
pr27501.ll
…
pr27591.ll
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
2019-03-19 19:01:34 +00:00
pr27681.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
pr28129.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr28173.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
pr28444.ll
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
2019-04-10 18:00:41 +00:00
pr28472.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr28489.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
pr28515.ll
…
pr28560.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr28824.ll
…
pr29010.ll
[NFC] fix trivial typos in comments
2018-04-13 11:37:06 +00:00
pr29022.ll
…
pr29061.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr29112.ll
[X86][SSE] matchBinaryPermuteShuffle - split INSERTPS combines
2019-08-08 13:23:53 +00:00
pr29170.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr29222.ll
[X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222)
2018-03-11 19:22:13 +00:00
pr30284.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
pr30290.ll
[X86] Mark all byval parameters as aliased
2018-05-08 09:18:01 +00:00
pr30430.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
pr30511.ll
[DAGCombiner][x86] scalarize binop followed by extractelement
2019-01-03 21:31:16 +00:00
pr30562.ll
[SelectionDAG] Add SimplifyDemandedBits handling for ISD::SCALAR_TO_VECTOR
2019-03-15 17:00:55 +00:00
pr30813.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
pr30821.mir
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
2019-06-18 03:23:11 +00:00
pr31045.ll
DAG combiner: fold (select, C, X, undef) -> X
2018-11-16 23:13:38 +00:00
pr31088.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr31143.ll
…
pr31242.ll
…
pr31271.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
pr31323.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr31593.ll
Added a testcase for PR31593. A patch (r291535) that fixed this bug didn't have a testcase.
2018-05-24 08:45:15 +00:00
pr31773.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr31956.ll
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
2018-01-15 22:18:45 +00:00
pr32108.ll
[DAGCombine] Improve Load-Store Forwarding
2018-10-10 14:15:52 +00:00
pr32241.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr32256.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr32278.ll
…
pr32282.ll
[SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry
2019-04-15 07:19:11 +00:00
pr32284.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr32329.ll
[X86] Remove dead nodes left after ReplaceAllUsesWith calls during address matching
2019-04-24 18:02:07 +00:00
pr32340.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr32345.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr32368.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr32420.ll
[X86] Promote i16 SRA instructions to i32
2019-04-05 06:32:50 +00:00
pr32451.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr32484.ll
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
2019-05-03 19:06:57 +00:00
pr32515.ll
…
pr32588.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
pr32610.ll
[x86] auto-generate complete test checks; NFC
2019-03-22 15:33:55 +00:00
pr32659.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr32907.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr33010.ll
Fix pr33010, a 2 year old crashing regression
2019-05-06 22:09:31 +00:00
pr33290.ll
[DAGCombiner] allow narrowing of add followed by truncate
2018-12-22 17:10:31 +00:00
pr33349.ll
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction.
2019-02-04 04:15:10 +00:00
pr33396.ll
…
pr33715.ll
…
pr33747.ll
[X86] Add PR33747 test case
2018-02-11 13:12:50 +00:00
pr33828.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
pr33954.ll
…
pr33960.ll
[DAG] make binops with undef operands consistent with IR
2018-02-12 21:37:27 +00:00
pr34080-2.ll
[X86] Remove hasSideEffects=1 from the X87 pseudos with folded load.
2019-02-21 22:00:15 +00:00
pr34080.ll
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
2019-02-15 21:59:33 +00:00
pr34088.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
pr34137.ll
[X86] Remove truncation handling from EmitTest. Replace it with a DAG combine.
2018-12-16 18:35:55 +00:00
pr34139.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr34149.ll
[DAG] propagate FMF for all FPMathOperators
2018-05-15 14:16:24 +00:00
pr34177.ll
[X86][SSE] Constant fold PEXTRB/PEXTRW/EXTRACT_VECTOR_ELT nodes.
2019-03-16 15:02:00 +00:00
pr34271-1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr34271.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr34292.ll
[X86] Add test case from PR34292
2019-01-26 13:56:53 +00:00
pr34381.ll
[DAGCombiner] allow narrowing of add followed by truncate
2018-12-22 17:10:31 +00:00
pr34397.ll
…
pr34421.ll
MachO: trap unreachable instructions
2018-04-13 22:25:20 +00:00
pr34592.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr34605.ll
[X86] Use DAG.getConstant instead of getZeroVector.
2018-11-11 07:24:36 +00:00
pr34629.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr34634.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr34653.ll
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
2019-05-03 19:06:57 +00:00
pr34657.ll
[X86][AVX] Add combineConcatVectors support to improve subvector handling
2019-03-13 16:37:30 +00:00
pr34855.ll
[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.
2017-12-11 08:33:20 +00:00
pr35272.ll
[X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector.
2018-01-27 20:19:09 +00:00
pr35316.ll
[X86] Rename function main->foo in CodeGen/X86/pr35316.ll. NFC
2018-02-13 10:58:19 +00:00
pr35399.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr35443.ll
[X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors
2018-10-08 18:40:50 +00:00
pr35636.ll
[X86] Don't emit MULX by default with BMI2
2018-12-12 21:21:31 +00:00
pr35761.ll
[DAGCombine] Fix for PR35761
2018-01-08 13:21:24 +00:00
pr35763.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
pr35765.ll
[DAGCombiner] allow narrowing of add followed by truncate
2018-12-22 17:10:31 +00:00
pr35918.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
pr35972.ll
[X86] Emit SBB instead of SETCC_CARRY from LowerSELECT. Break false dependency on the SBB input.
2018-12-12 19:20:21 +00:00
pr35982.ll
Recommit r352660 "[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7."
2019-02-04 04:44:20 +00:00
pr36199.ll
[DAGCombiner] look through bitcasts when trying to narrow vector binops
2018-11-20 22:26:35 +00:00
pr36274.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
pr36312.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
pr36553.ll
[X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific node when there are no FMA instructions.
2018-03-01 00:08:38 +00:00
pr36602.ll
[DAG] Avoid using deleted node in rebuildSetCC
2018-05-10 14:28:54 +00:00
pr36865.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
pr37063.ll
[X86] Prevent folding loads with 64-bit ANDs with immediates that fit in 32-bits.
2018-04-10 03:44:15 +00:00
pr37264.ll
Follow-up to rL332176 by adding a test case for PR37264.
2018-05-13 14:32:23 +00:00
pr37359.ll
[SelectionDAG] Don't crash on inline assembly errors when the inline assembly return type is a struct.
2018-06-20 04:32:05 +00:00
pr37499.ll
[X86] Add ISD nodes for masked truncate so we can properly represent when the output has more elements than the input due to needing to be 128 bits.
2019-01-12 00:55:27 +00:00
pr37820.ll
[DAG] Fix and-mask folding when narrowing loads.
2018-06-20 15:36:29 +00:00
pr37826.ll
[DAG] Fix Memory ordering check in ReduceLoadOpStore.
2018-07-20 15:20:50 +00:00
pr37879.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
pr37916.ll
[ScheduleDAG] Fix unfolding of SUnits to already existent nodes.
2018-07-18 18:01:03 +00:00
pr38038.ll
Add x86_64-unkown triple to llc for x86 test.
2018-07-20 03:50:55 +00:00
pr38185.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
pr38217.ll
[DAGCombiner] After performing the division by constant optimization for a DIV or REM node, replace the users of the corresponding REM or DIV node if it exists.
2019-01-02 18:19:07 +00:00
pr38533.ll
[DAGCombine] Improve Load-Store Forwarding
2018-10-10 14:15:52 +00:00
pr38539.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
pr38639.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
pr38738.ll
[X86] Correctly use SSE registers if no-x87 is selected.
2018-10-03 14:13:30 +00:00
pr38743.ll
This reverts r365061 and r365062 (test update)
2019-07-05 12:42:06 +00:00
pr38762.ll
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
2018-10-25 09:58:59 +00:00
pr38763.ll
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
2018-10-25 09:58:59 +00:00
pr38795.ll
[RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers
2018-12-14 14:07:57 +00:00
pr38803.ll
[X86] Stop X86DomainReassignment from creating copies between GR8/GR16 physical registers and k-registers.
2018-10-01 07:08:41 +00:00
pr38819.ll
[X86] Don't create FILD ISD nodes when X87 is disabled.
2018-09-25 00:16:57 +00:00
pr38865-2.ll
[X86] Teach X86FastISel::X86SelectRet to use EAX for the sret pointer in GNUX32
2018-09-11 17:57:23 +00:00
pr38865-3.ll
[X86] Fix inline expansion for memset in x32
2018-09-22 05:16:35 +00:00
pr38865.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
pr38952.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
pr39098.ll
[DAGCombine] Avoid CombineZExtLogicopShiftLoad if there is free ZEXT
2019-01-31 20:46:42 +00:00
pr39187-g.ll
[DebugInfo] Remove un-necessary logic from HoistThenElseCodeToIf
2019-01-14 12:13:12 +00:00
pr39243.ll
[DebugInfo] Combine Trivial and NonTrivial flags
2019-04-11 20:25:10 +00:00
pr39666.ll
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches for expandload/compressstore.
2019-08-02 23:43:53 +00:00
pr39733.ll
[X86] Correct 256 vpmovzx/vpmovsx isel patterns to check HasAVX2 instead of HasAVX to prevent fast-isel from using them incorrectly.
2018-11-21 01:39:38 +00:00
pr39896.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
pr39926.ll
[X86] Fix AvoidStoreForwardingBlocks pass for negative displacements
2018-12-10 10:16:50 +00:00
pr40090.ll
[X86] Add BSR to isUseDefConvertible.
2018-12-18 20:03:54 +00:00
pr40289-64bit.ll
[X86] Avoid clobbering ESP/RSP in the epilogue.
2019-01-15 01:24:18 +00:00
pr40289.ll
[X86] Avoid clobbering ESP/RSP in the epilogue.
2019-01-15 01:24:18 +00:00
pr40529.ll
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
2019-02-15 21:59:33 +00:00
pr40539.ll
[X86] Add ST0 as an implicit def/use of x87 load/store instructions during FP stackifying.
2019-02-04 18:43:55 +00:00
pr40631_deadstore_elision.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
pr40730.ll
[X86][AVX] lowerShuffleAsLanePermuteAndPermute - fully populate the lane shuffle mask (PR40730)
2019-02-15 11:39:21 +00:00
pr40737.ll
[X86] Fix LowerAsmOutputForConstraint.
2019-02-15 20:01:55 +00:00
pr40811.ll
Recommit r354363 "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
2019-02-23 21:41:42 +00:00
pr40891.ll
[X86] Add test case that was supposed to go with r355116.
2019-02-28 18:50:16 +00:00
pr40994.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
pr41619.ll
[X86] Add test case for mask register variant of PR41619 which should be fixed after r360552
2019-05-13 15:45:20 +00:00
pr41678.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
pr41748.ll
[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.
2019-05-06 19:50:14 +00:00
pr42452.ll
[X86] Improve the type checking fast-isel handling of vector bitcasts.
2019-07-01 07:09:34 +00:00
pr42565.ll
[X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
2019-07-11 01:01:39 +00:00
pr42616.ll
[X86] Remove offset of 8 from the call to FuseInst for UNPCKLPDrr folding added in r365287.
2019-07-14 04:13:33 +00:00
pr42727.ll
[SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727)
2019-07-24 16:53:14 +00:00
pr42870.ll
[X86] Match the IR pattern form movmsk on SSE1 only targets where v4i32 isn't legal
2019-08-10 07:51:13 +00:00
pr42905.ll
[X86] Don't allow combineSIntToFP to create v2i32 vectors after type legalization.
2019-08-06 21:43:15 +00:00
pr42909.ll
[X86] Remove -x86-experimental-vector-widening-legalization command line option and all its uses.
2019-08-08 06:48:22 +00:00
PR34565.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
PR37310.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
PR40322.ll
[X86] Run CFIInstrInserter on Windows if Dwarf is used
2019-04-29 20:25:51 +00:00
pre-coalesce-2.ll
…
pre-coalesce.ll
…
pre-coalesce.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
pre-ra-sched.ll
…
prefer-avx256-lzcnt.ll
[X86][SSE] Remove unnecessary bit-and in pshufb vector ctlz (PR39703)
2018-11-19 18:40:59 +00:00
prefer-avx256-mask-extend.ll
[X86] Move VPTESTM matching from the isel table to custom code in X86ISelDAGToDAG.
2019-04-14 18:26:11 +00:00
prefer-avx256-mask-shuffle.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
prefer-avx256-popcnt.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
prefer-avx256-shift.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
prefer-avx256-trunc.ll
[X86] Lower v16i16->v8i16 truncate using an 'and' with 255, an extract_subvector, and a packuswb instruction.
2018-11-18 17:59:28 +00:00
prefer-avx256-wide-mul.ll
[X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS.
2018-12-03 18:26:27 +00:00
prefetch.ll
[X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions.
2017-12-22 02:30:30 +00:00
prefixdata.ll
…
preserve_allcc64.ll
…
preserve_mostcc64.ll
…
private-2.ll
…
private.ll
…
probe-stack-x32.ll
[X86] Fix stack probing on x32 (PR41477)
2019-04-20 07:25:46 +00:00
prolog-push-seq.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
prologepilog_deref_size.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
prologue-epilogue-remarks.mir
[PEI] Fix failing test caused by r324283
2018-02-05 23:06:47 +00:00
prologuedata.ll
…
promote-assert-zext.ll
…
promote-i16.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
promote-trunc.ll
…
promote-vec3.ll
Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT"
2019-08-13 09:33:25 +00:00
promote.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
ps4-noreturn.ll
…
ps4-ssp-nop.ll
[PS4] Emit a trap after a stack-protector fail call.
2019-03-06 19:57:43 +00:00
psadbw.ll
[X86][SSE] Add test showing missing demanded elts PSADBW handling
2019-08-12 14:01:16 +00:00
pseudo_cmov_lower1.ll
…
pseudo_cmov_lower2.ll
[X86] Avoid codegen changes when DBG_VALUE appears between lowered selects
2019-03-04 10:56:02 +00:00
pseudo_cmov_lower.ll
…
pshufb-mask-comments.ll
Recommit r344877 "[X86] Stop promoting integer loads to vXi64"
2018-10-22 22:14:05 +00:00
pshufd-combine-crash.ll
…
psubus.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
ptest.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
ptr-rotate.ll
…
ptrtoint-constexpr.ll
…
ptrtoint-narrow.ll
[AsmPrinter] Treat a narrowing PtrToInt like Trunc
2019-05-23 16:29:09 +00:00
ptwrite32-intrinsic.ll
[X86] ptwrite intrinsic
2018-05-10 07:26:05 +00:00
ptwrite64-intrinsic.ll
[X86] ptwrite intrinsic
2018-05-10 07:26:05 +00:00
pull-binop-through-shift.ll
[DAGCombiner] visitShiftByConstant(): drop bogus signbit check
2019-05-17 15:52:58 +00:00
pull-conditional-binop-through-shift.ll
[NFC] Fixup FileCheck option name in tests added in rL360881
2019-05-16 12:39:34 +00:00
push-cfi-debug.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
push-cfi-obj.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
push-cfi.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
ragreedy-bug.ll
Codegen: Fixed perf branch_weights in couple of tests. NFC.
2019-04-15 09:30:31 +00:00
ragreedy-hoist-spill.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
ragreedy-last-chance-recoloring.ll
…
rd-mod-wr-eflags.ll
[CGP] add special-cases to form unsigned add with overflow (PR40486)
2019-02-24 15:31:27 +00:00
rdpid.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
rdpmc.ll
[X86] Regenerate RDPMC intrinsic test
2018-01-19 12:05:58 +00:00
rdrand-x86_64.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
rdrand.ll
[X86] Remove FeatureSlowIncDec from Sandy Bridge and later Intel Core CPUs
2019-02-20 05:39:11 +00:00
rdseed-x86_64.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
rdseed.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
rdtsc-upgrade.ll
[X86] Modify the the rdtscp intrinsic to return values instead of taking a pointer argument
2018-09-07 19:14:15 +00:00
rdtsc.ll
[X86] Modify the the rdtscp intrinsic to return values instead of taking a pointer argument
2018-09-07 19:14:15 +00:00
read-fp-no-frame-pointer.ll
…
recip-fastmath2.ll
[AsmPrinter] Remove hidden flag -print-schedule.
2019-02-04 12:51:26 +00:00
recip-fastmath.ll
[AsmPrinter] Remove hidden flag -print-schedule.
2019-02-04 12:51:26 +00:00
recip-pic.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
red-zone2.ll
…
red-zone.ll
…
reduce-trunc-shl.ll
[x86] split more v8f32/v8i32 shuffles in lowering
2019-02-18 16:46:12 +00:00
regalloc-advanced-split-cost.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regalloc-copy-hints.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
regalloc-fast-missing-live-out-spill.mir
RegAllocFast: Set MayLiveAcrossBlocks when allocating uses
2019-05-27 20:37:31 +00:00
regalloc-reconcile-broken-hints.ll
…
regalloc-spill-at-ehpad.ll
…
regcall-no-plt.ll
…
reghinting.ll
…
regparm.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
regpressure.ll
…
relptr-rodata.ll
IR: Teach Constant::needsRelocation() that relative pointers don't need to be relocated.
2019-07-18 20:56:21 +00:00
rem_crash.ll
…
rem.ll
[DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)
2018-07-28 00:27:25 +00:00
remarks-section.ll
Reland: [Remarks] Add support for serializing metadata for every remark streamer
2019-07-26 01:33:30 +00:00
remat-constant.ll
…
remat-fold-load.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
remat-mov-0.ll
…
remat-phys-dead.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
remat-scalar-zero.ll
…
replace_unsupported_masked_mem_intrin.ll
[CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.
2018-04-24 09:24:29 +00:00
replace-load-and-with-bzhi.ll
[X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction.
2017-12-12 14:13:51 +00:00
ret-addr.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
ret-i64-0.ll
…
ret-mmx.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
retpoline-external.ll
[Spectre] Fix MIR verifier errors in retpoline thunks
2018-10-26 20:26:36 +00:00
retpoline-regparm.ll
[Spectre] Fix MIR verifier errors in retpoline thunks
2018-10-26 20:26:36 +00:00
retpoline.ll
[Spectre] Fix MIR verifier errors in retpoline thunks
2018-10-26 20:26:36 +00:00
return_zeroext_i2.ll
…
return-ext.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
returned-trunc-tail-calls.ll
…
reverse_branches.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
rip-rel-address.ll
…
rip-rel-lea.ll
…
rodata-relocs.ll
…
rot16.ll
[X86] CombineOr - fold to generic funnel shifts
2019-02-09 20:34:59 +00:00
rot32.ll
[X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD
2019-03-27 17:29:34 +00:00
rot64.ll
[X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD
2019-03-27 17:29:34 +00:00
rotate2.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
rotate4.ll
[x86] make 8-bit shl undesirable
2019-04-08 13:58:50 +00:00
rotate_vec.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
rotate-extract-vector.ll
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
2019-05-25 18:02:17 +00:00
rotate-extract.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
rotate-multi.ll
Add more rotate tests, including ORs of rotates
2019-03-21 17:14:22 +00:00
rotate.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
rounding-ops.ll
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.
2018-06-12 00:48:57 +00:00
rrlist-livereg-corrutpion.ll
…
rtm.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
sad_variations.ll
[X86][AVX] Add AVX1 PSAD tests
2018-02-26 15:55:25 +00:00
sad.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
sadd_sat_vec.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
sadd_sat.ll
[X86] Promote i8 CMOV's (PR40965)
2019-03-15 21:17:53 +00:00
saddo-redundant-add.ll
…
safestack_inline.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
safestack_ssp.ll
…
safestack.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
sandybridge-loads.ll
[x86] avoid vector load narrowing with extracted store uses (PR42305)
2019-06-19 18:13:47 +00:00
sar_fold64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sar_fold.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sat-add.ll
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
2019-07-23 15:35:55 +00:00
sbb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
scalar_sse_minmax.ll
…
scalar_widen_div.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
scalar-extract.ll
…
scalar-fp-to-i64.ll
[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.
2019-06-10 00:41:07 +00:00
scalar-int-to-fp.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
scalar-min-max-fill-operand.ll
…
scalarize-bitcast.ll
…
scalarize-fp.ll
[DAGCombiner] generalize binop-of-splats scalarization
2019-04-23 13:16:41 +00:00
scatter-schedule.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
scavenger.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
scev-interchange.ll
…
scheduler-backtracking.ll
[DAGCombiner] Combine OR as ADD when no common bits are set
2019-04-23 10:01:08 +00:00
sdiv-exact.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
sdiv-pow2.ll
…
section_mergeable_size.ll
[MC][ELF] fix newly added test
2018-10-12 16:35:44 +00:00
segmented-stacks-dynamic.ll
[X86] improve split-stack machine BB placement
2018-11-07 17:41:57 +00:00
segmented-stacks-standalone.ll
Notify the linker when a TU compiled with split-stack has a function without a prologue.
2018-11-26 23:26:31 +00:00
segmented-stacks.ll
[X86] for split stack, not save/restore nested arg if unused
2019-07-19 12:54:44 +00:00
seh-catch-all-win32.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
seh-catch-all.ll
…
seh-catchpad.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-except-finally.ll
…
seh-exception-code.ll
…
seh-filter-no-personality.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
seh-finally.ll
Use .set instead of = when printing assignment in assembly output
2018-03-27 16:44:41 +00:00
seh-localaddress.ll
Fix the lowering issue of intrinsics llvm.localaddress on X86
2019-02-08 01:14:12 +00:00
seh-no-invokes.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
seh-safe-div-win32.ll
…
seh-safe-div.ll
…
seh-stack-realign.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
select_const.ll
[x86] make 8-bit shl undesirable
2019-04-08 13:58:50 +00:00
select_meta.ll
…
select-1-or-neg1.ll
[x86] add select test to show there's no single right answer (PR28968); NFC
2018-02-12 22:19:24 +00:00
select-mmx.ll
[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.
2018-08-11 05:33:00 +00:00
select-of-fp-constants.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
select-with-and-or.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
select.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
selectcc-to-shiftand.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
selectiondag-crash.ll
…
selectiondag-cse.ll
…
selectiondag-debug-loc.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
selectiondag-dominator.ll
…
selectiondag-order.ll
…
setcc-combine.ll
[TargetLowering] refactor setcc folds to fix another miscompile (PR40657)
2019-02-10 14:29:57 +00:00
setcc-logic.ll
[DAGCombiner] convert logic-of-setcc into bit magic (PR40611)
2019-02-12 17:07:47 +00:00
setcc-lowering.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
setcc-narrowing.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
setcc-wide-types.ll
[X86] Don't compare i128 through vector if construction not cheap (PR41971)
2019-05-22 06:47:06 +00:00
setcc.ll
[X86] Don't promote i16 compares to i32 if the immediate will fit in 8 bits.
2018-10-05 18:13:36 +00:00
setjmp-spills.ll
…
setoeq.ll
…
setuge.ll
…
sext-i1.ll
[DAGCombiner] fold sext into decrement
2019-03-29 13:49:08 +00:00
sext-load.ll
…
sext-ret-val.ll
…
sext-setcc-self.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sext-subreg.ll
…
sext-trunc.ll
…
sha.ll
[X86] When post-processing the DAG to remove zero extending moves for YMM/ZMM, make sure the producing instruction is VEX/XOP/EVEX encoded.
2018-08-03 04:49:42 +00:00
shadow-stack.ll
SelectionDAGBuilder, mach-o: Skip trap after noreturn call (for Mach-O)
2018-06-28 17:00:45 +00:00
shift_minsize.ll
[SelectionDAG] Codesize: don't expand SHIFT to SHIFT_PARTS
2019-01-31 08:07:30 +00:00
shift-amount-mod.ll
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
2019-06-04 11:06:21 +00:00
shift-and-x86_64.ll
[X86] Add test cases for PR36721 (unnecessary andl for %cl when shifting)
2019-01-27 18:31:33 +00:00
shift-and.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
shift-avx2-crash.ll
…
shift-bmi2.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
shift-coalesce.ll
…
shift-codegen.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shift-combine-crash.ll
…
shift-combine.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shift-double-x86_64.ll
[X86] Improve use of SHLD/SHRD
2019-03-02 02:44:16 +00:00
shift-double.ll
[X86] Improve use of SHLD/SHRD
2019-03-02 02:44:16 +00:00
shift-folding.ll
[DAG] consolidate shift simplifications
2018-11-23 20:05:12 +00:00
shift-i128.ll
…
shift-i256.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
shift-mask.ll
[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
2019-05-14 15:21:28 +00:00
shift-one.ll
…
shift-pair.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
shift-parts.ll
…
shift-pcmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shl_elim.ll
…
shl_undef.ll
…
shl-anyext.ll
…
shl-crash-on-legalize.ll
[X86] Emit SBB instead of SETCC_CARRY from LowerSELECT. Break false dependency on the SBB input.
2018-12-12 19:20:21 +00:00
shl-i64.ll
…
shrink_vmul_sse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shrink_vmul.ll
[X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
2019-08-13 10:51:39 +00:00
shrink_wrap_dbg_value.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
shrink-compare.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
shrink-fp-const1.ll
…
shrink-fp-const2.ll
…
shrink-wrap-chkstk-x86_64.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
shrink-wrap-chkstk.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
shrink-wrapping-vla.ll
Add tests for shrink wrapping and VLAs
2018-04-18 13:37:12 +00:00
shrinkwrap-hang.ll
…
shuffle-combine-crash-2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shuffle-combine-crash.ll
…
shuffle-extract-subvector.ll
[DAGCombine] Fix a miscompile when reducing BUILD_VECTORs to a shuffle
2019-03-19 16:52:00 +00:00
shuffle-of-insert.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
shuffle-of-splat-multiuses.ll
[x86] try to form broadcast before widening shuffle elements
2018-11-09 14:54:58 +00:00
shuffle-strided-with-offset-128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shuffle-strided-with-offset-256.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shuffle-strided-with-offset-512.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shuffle-vs-trunc-128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shuffle-vs-trunc-256.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
shuffle-vs-trunc-512.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
sibcall-2.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
sibcall-3.ll
…
sibcall-4.ll
…
sibcall-5.ll
…
sibcall-6.ll
…
sibcall-byval.ll
…
sibcall-win64.ll
…
sibcall.ll
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
2019-06-25 17:29:18 +00:00
signbit-shift.ll
[DAGCombiner] Combine OR as ADD when no common bits are set
2019-04-23 10:01:08 +00:00
signed-truncation-check.ll
[X86] Suppress load folding for add/sub with 128 immediate.
2019-03-06 07:36:36 +00:00
simple-register-allocation-read-undef.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
simple-zext.ll
…
sincos-opt.ll
[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st.
2019-02-04 17:28:18 +00:00
sincos.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sink-addsub-of-const.ll
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
2019-06-04 11:06:21 +00:00
sink-blockfreq.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sink-cheap-instructions.ll
…
sink-gep-before-mem-inst.ll
…
sink-hoist.ll
…
sink-local-value.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
sink-out-of-loop.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sitofp.ll
[X86] Fix missing cfi from sitofp checks
2018-04-24 13:24:56 +00:00
sjlj-baseptr.ll
…
sjlj-eh.ll
[X86] Enable the MachineVerifier by default
2018-10-29 16:57:43 +00:00
sjlj-shadow-stack-liveness.mir
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
sjlj.ll
…
slow-incdec.ll
[X86] Lower ISD::UADDO to use the Z flag instead of C flag when the RHS is a constant 1 to encourage INC formation.
2019-02-03 07:25:06 +00:00
slow-pmulld.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
slow-unaligned-mem.ll
[X86] AMD znver2 enablement
2019-02-26 16:55:10 +00:00
small-byval-memcpy.ll
AMD BdVer2 (Piledriver) Initial Scheduler model
2018-10-27 20:46:30 +00:00
smul_fix_sat_constants.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
smul_fix_sat.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
smul_fix.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
smul-with-overflow.ll
…
soft-fp-legal-in-HW-reg.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
soft-fp.ll
…
soft-sitofp.ll
…
speculative-load-hardening-call-and-ret.ll
[SLH] Regenerate tests with --no_x86_scrub_rip to restore the higher
2018-12-05 15:41:13 +00:00
speculative-load-hardening-gather.ll
[x86/SLH] Add a real Clang flag and LLVM IR attribute for Speculative
2018-09-04 12:38:00 +00:00
speculative-load-hardening-indirect.ll
X86: regenerate speculative-load-hardening-indirect.ll tests. NFC.
2019-04-02 22:44:46 +00:00
speculative-load-hardening.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
splat-const.ll
…
splat-for-size.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
split-eh-lpad-edges.ll
…
split-extend-vector-inreg.ll
[DAGCombine] Add calls to SimplifyDemandedVectorElts from visitINSERT_SUBVECTOR (PR37989)
2018-11-20 15:23:50 +00:00
split-store.ll
[DAGCombiner] Combine OR as ADD when no common bits are set
2019-04-23 10:01:08 +00:00
split-vector-bitcast.ll
…
split-vector-rem.ll
…
sqrt-fastmath-mir.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
sqrt-fastmath-tune.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sqrt-fastmath.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
sqrt-partial.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sqrt.ll
…
srem-seteq-optsize.ll
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
2019-08-13 14:57:37 +00:00
srem-seteq-vec-nonsplat.ll
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
2019-08-13 14:57:37 +00:00
srem-seteq-vec-splat.ll
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
2019-08-13 14:57:37 +00:00
srem-seteq.ll
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
2019-08-13 14:57:37 +00:00
sret-implicit.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sse1-fcopysign.ll
[X86] Recognize constant splats in LowerFCOPYSIGN.
2018-10-28 23:51:35 +00:00
sse1.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sse2-intrinsics-canonical.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
sse2-intrinsics-fast-isel-x86_64.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse2-intrinsics-fast-isel.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
sse2-intrinsics-x86_64-upgrade.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse2-intrinsics-x86_64.ll
[X86][SSE] Cleanup SSE2 intrinsics tests
2018-06-02 19:43:14 +00:00
sse2-intrinsics-x86-upgrade.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse2-intrinsics-x86.ll
[X86] Restore the pavg intrinsics.
2019-04-15 17:17:35 +00:00
sse2-vector-shifts.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
sse2.ll
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
2019-07-08 06:52:43 +00:00
sse3-avx-addsub-2.ll
[X86][AVX] Prefer to combine shuffle to broadcasts whenever possible
2019-01-30 16:19:19 +00:00
sse3-avx-addsub.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sse3-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
sse3-intrinsics-x86.ll
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead.
2019-04-03 23:28:30 +00:00
sse3.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
sse4a-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse4a-upgrade.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse4a.ll
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
2018-06-02 17:33:26 +00:00
sse41-intrinsics-fast-isel.ll
[X86] Use GetDemandedBits to simplify the operands of PMULDQ/PMULUDQ.
2018-12-24 19:40:20 +00:00
sse41-intrinsics-x86-upgrade.ll
[X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size.
2018-07-14 02:05:08 +00:00
sse41-intrinsics-x86.ll
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
2018-06-02 18:01:09 +00:00
sse41-pmovxrm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sse41.ll
[x86] try harder to use broadcast to load a scalar into vector reg
2018-08-25 14:56:05 +00:00
sse42-intrinsics-fast-isel-x86_64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sse42-intrinsics-fast-isel.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sse42-intrinsics-x86_64.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sse42-intrinsics-x86.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
sse_partial_update.ll
[x86] add test for SSE sqrtss register dep (PR22206)
2018-10-04 17:59:30 +00:00
sse_reload_fold.ll
…
sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
sse-commute.ll
…
sse-cvttp2si.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse-domains.ll
…
sse-fcopysign.ll
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
2019-07-02 17:51:02 +00:00
sse-fsignum.ll
[X86] Extend inputs with elements smaller than i32 to sint_to_fp/uint_to_fp before type legalization.
2018-02-10 17:58:58 +00:00
sse-intel-ocl.ll
…
sse-intrinsics-fast-isel-x86_64.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse-intrinsics-fast-isel.ll
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
2019-07-15 02:02:31 +00:00
sse-intrinsics-x86_64-upgrade.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse-intrinsics-x86_64.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-intrinsics-x86-upgrade.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
sse-intrinsics-x86.ll
[X86] Lowering sqrt intrinsics to native IR
2018-06-15 18:05:24 +00:00
sse-load-ret.ll
…
sse-minmax.ll
[DAGCombine] SimplifySelectCC - call FoldSetCC with the setcc result type
2019-03-21 14:07:18 +00:00
sse-only.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
sse-regcall.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
sse-scalar-fp-arith-unary.ll
[X86][SSE] Cleanup SSE1 intrinsics tests
2018-06-02 20:25:56 +00:00
sse-scalar-fp-arith.ll
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
2019-06-11 04:30:53 +00:00
sse-unaligned-mem-feature.ll
…
sse-varargs.ll
…
ssp-data-layout.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
ssp-guard-spill.ll
…
ssse3-intrinsics-fast-isel.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
ssse3-intrinsics-x86.ll
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
2018-06-02 18:41:46 +00:00
ssub_sat_vec.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
ssub_sat.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
stack_guard_remat.ll
…
stack-align2.ll
…
stack-align-memcpy.ll
[NFC] Update memcpy tests
2019-05-06 09:46:50 +00:00
stack-align.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
stack-folding-3dnow.ll
…
stack-folding-adx-x86_64.ll
[X86] Merge addcarryx/addcarry intrinsic into a single addcarry intrinsic.
2018-12-10 06:07:50 +00:00
stack-folding-adx.mir
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:27:49 +00:00
stack-folding-avx512bf16.ll
[X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading folding tables.
2019-06-01 06:20:59 +00:00
stack-folding-avx512vp2intersect.ll
[X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading folding tables.
2019-06-01 06:20:59 +00:00
stack-folding-bmi2.ll
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well
2018-12-12 20:50:24 +00:00
stack-folding-bmi2.mir
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well
2018-12-12 20:50:24 +00:00
stack-folding-bmi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
stack-folding-fp-avx1.ll
[X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialRegUpdate.
2019-02-16 03:34:54 +00:00
stack-folding-fp-avx512.ll
[X86] Make a bunch of merge masked binops commutable for loading folding.
2019-06-06 21:00:04 +00:00
stack-folding-fp-avx512vl.ll
[X86] Autoupgrade some of the intrinsics used by stack folding tests that have been previously removed.
2019-01-26 06:27:04 +00:00
stack-folding-fp-sse42.ll
[X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialRegUpdate.
2019-02-16 03:34:54 +00:00
stack-folding-int-avx1.ll
[X86] Autoupgrade some of the intrinsics used by stack folding tests that have been previously removed.
2019-01-26 06:27:04 +00:00
stack-folding-int-avx2.ll
[x86] make stack folding tests immune to unrelated transforms; NFC
2019-04-03 16:33:24 +00:00
stack-folding-int-avx512.ll
[X86] Make a bunch of merge masked binops commutable for loading folding.
2019-06-06 21:00:04 +00:00
stack-folding-int-avx512vl.ll
[X86] Autoupgrade some of the intrinsics used by stack folding tests that have been previously removed.
2019-01-26 06:27:04 +00:00
stack-folding-int-sse42.ll
[X86][SSE] Remove use of SSE ADDS/SUBS saturation intrinsics from schedule/stack tests
2018-12-19 12:00:25 +00:00
stack-folding-lwp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
stack-folding-mmx.ll
…
stack-folding-sha.ll
…
stack-folding-tbm.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
stack-folding-x86_64.ll
…
stack-folding-xop.ll
…
stack-probe-red-zone.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
stack-probe-size.ll
…
stack-probes.ll
…
stack-protector-dbginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
stack-protector-msvc.ll
Re-commit r319490 "XOR the frame pointer with the stack cookie when protecting the stack"
2017-12-05 20:22:20 +00:00
stack-protector-remarks.ll
…
stack-protector-target.ll
…
stack-protector-vreg-to-vreg-copy.ll
…
stack-protector-weight.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
stack-protector.ll
StackProtector: Use PointerMayBeCaptured
2019-06-12 14:23:33 +00:00
stack-size-section-function-sections.ll
Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"
2018-06-22 10:53:47 +00:00
stack-size-section.ll
Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"
2018-06-22 10:53:47 +00:00
stack-update-frame-opcode.ll
…
StackColoring-dbg.ll
…
StackColoring.ll
…
stackguard-internal.ll
…
stackmap-fast-isel.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
stackmap-frame-setup.ll
…
stackmap-large-constants.ll
…
stackmap-large-location-size.ll
…
stackmap-liveness.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
stackmap-nops.ll
…
stackmap-shadow-optimization.ll
…
stackmap.ll
…
stackpointer.ll
…
statepoint-allocas.ll
[Test] Use autogenerated checks for more statepoint tests
2019-02-12 00:12:46 +00:00
statepoint-call-lowering.ll
[Test] Use autogenerated checks for more statepoint tests
2019-02-12 00:12:46 +00:00
statepoint-far-call.ll
[Test] Use autogenerated checks for more statepoint tests
2019-02-12 00:12:46 +00:00
statepoint-forward.ll
…
statepoint-gctransition-call-lowering.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
statepoint-invoke.ll
[Test] Use autogenerated checks for more statepoint tests
2019-02-12 00:12:46 +00:00
statepoint-live-in.ll
[Tests] A few more live-in deopt lowering tests
2019-02-12 23:00:07 +00:00
statepoint-no-realign-stack.ll
[Statepoints] Fix overalignment of loads in no-realign-stack functions
2019-08-02 20:17:37 +00:00
statepoint-stack-usage.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
statepoint-stackmap-format.ll
[CodeGen] Prefer static frame index for STATEPOINT liveness args
2018-11-30 16:22:41 +00:00
statepoint-uniqueing.ll
[Tests] Fill out a few tests around gc relocation uniquing
2019-02-12 00:01:39 +00:00
statepoint-vector-bad-spill.ll
…
statepoint-vector.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
stdarg.ll
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stdcall-notailcall.ll
…
stdcall.ll
…
store_op_load_fold2.ll
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
2018-03-19 20:19:46 +00:00
store_op_load_fold.ll
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store-empty-member.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
store-narrow.ll
…
store-zero-and-minus-one.ll
[X86] When using "and $0" and "orl $-1" to store 0 and -1 for minsize, make sure the store isn't volatile
2018-08-06 18:44:26 +00:00
stores-merging.ll
[DAGCombine] Fold overlapping constant stores
2019-02-22 16:00:19 +00:00
storetrunc-fp.ll
…
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
sttni.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
sub-of-not.ll
[Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
2019-07-03 09:41:35 +00:00
sub-with-overflow.ll
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
2019-04-09 18:33:56 +00:00
sub.ll
…
subcarry.ll
[DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
2019-07-16 15:17:00 +00:00
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
subreg-to-reg-2.ll
…
subreg-to-reg-3.ll
…
subreg-to-reg-4.ll
…
subreg-to-reg-6.ll
…
subvector-broadcast.ll
[x86] split 256-bit store of concatenated vectors
2019-06-04 16:40:04 +00:00
sunkaddr-ext.ll
…
swap.ll
Revert r357256 "[DAGCombine] Improve Lifetime node chains."
2019-04-03 07:41:58 +00:00
swift-error.ll
X86: remove R12 from CSR on Windows x64 SwiftCC
2017-09-25 22:00:17 +00:00
swift-return.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
swiftcc.ll
[X86] Enable tail calls for CallingConv::Swift
2019-04-05 20:18:25 +00:00
swifterror.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
swiftself.ll
[FastISel] Skip creating unnecessary vregs for arguments
2019-06-10 16:53:37 +00:00
switch-bt.ll
[CodeGen] Peel off the dominant case in switch statement in lowering
2017-11-14 21:44:09 +00:00
switch-crit-edge-constant.ll
…
switch-default-only.ll
…
switch-density.ll
…
switch-edge-weight.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
switch-jump-table.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
switch-lower-peel-top-case.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
switch-or.ll
…
switch-order-weight.ll
…
switch-zextload.ll
…
switch.ll
[test] Change comment wording (NFC)
2019-06-18 23:31:10 +00:00
SwitchLowering.ll
…
swizzle-2.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
swizzle-avx2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
SwizzleShuff.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
system-intrinsics-64-xsave.ll
…
system-intrinsics-64-xsavec.ll
…
system-intrinsics-64-xsaveopt.ll
…
system-intrinsics-64-xsaves.ll
…
system-intrinsics-64.ll
…
system-intrinsics-xgetbv.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
system-intrinsics-xsave.ll
…
system-intrinsics-xsavec.ll
…
system-intrinsics-xsaveopt.ll
…
system-intrinsics-xsaves.ll
…
system-intrinsics-xsetbv.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
system-intrinsics.ll
…
tail-call-attrs.ll
…
tail-call-casts.ll
…
tail-call-conditional.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
tail-call-got.ll
…
tail-call-legality.ll
…
tail-call-mutable-memarg.ll
…
tail-call-parameter-attrs-mismatch.ll
…
tail-call-win64.ll
…
tail-dup-addr.ll
…
tail-dup-catchret.ll
…
tail-dup-debugloc.ll
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
tail-dup-merge-loop-headers.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
tail-dup-no-other-successor.ll
…
tail-dup-repeat.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
tail-merge-after-mbp.mir
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
tail-merge-debugloc.ll
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
tail-merge-identical.ll
…
tail-merge-unreachable.ll
…
tail-merge-wineh.ll
…
tail-opts.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
tail-threshold.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
tailcall-64.ll
[x86] Clean up and convert test to use generated CHECK lines.
2018-07-24 03:18:08 +00:00
tailcall-calleesave.ll
…
tailcall-cgp-dup.ll
[CGP] Look through bitcasts when duplicating returns for tail calls
2019-04-23 21:57:46 +00:00
tailcall-disable.ll
…
tailcall-fastisel.ll
…
tailcall-largecode.ll
…
tailcall-lifetime-end.ll
[CodeGen] skip lifetime end marker in isInTailCallPosition
2018-10-24 17:03:19 +00:00
tailcall-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
tailcall-msvc-conventions.ll
…
tailcall-multiret.ll
…
tailcall-pseudo-64.mir
[X86] Preserve operand flag when expanding TCRETURNri
2019-04-05 20:18:21 +00:00
tailcall-pseudo.mir
[X86] Preserve operand flag when expanding TCRETURNri
2019-04-05 20:18:21 +00:00
tailcall-readnone.ll
…
tailcall-returndup-void.ll
…
tailcall-ri64.ll
…
tailcall-stackalign.ll
…
tailcall-structret.ll
…
tailcall.ll
…
tailcallbyval64.ll
…
tailcallbyval.ll
…
tailcallfp2.ll
…
tailcallfp.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallpic3.ll
…
tailcallstack64.ll
…
taildup-crash.ll
Fixed typos in tests: s/CEHCK/CHECK/
2019-02-25 13:12:33 +00:00
tailjmp_gotpcrel_relax_relocation.ll
Relax GOTPCREL relocations for tail jmp instructions.
2018-05-31 18:12:33 +00:00
targetLoweringGeneric.ll
…
tbm_patterns.ll
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
2019-07-10 22:44:32 +00:00
tbm-intrinsics-fast-isel-x86_64.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
tbm-intrinsics-fast-isel.ll
[X86] Teach convertToThreeAddress to handle SUB with immediate
2019-07-15 23:07:56 +00:00
tbm-intrinsics-x86_64.ll
[X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042)
2018-06-06 10:52:10 +00:00
tbm-intrinsics.ll
[X86][TBM] Use realistic BEXTR control bits
2018-06-03 18:15:06 +00:00
test_x86condbr_globaladdr.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
test-nofold.ll
…
test-shrink-bug.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
test-shrink.ll
[DAGCombiner] re-enable truncation of binops
2018-12-08 16:07:38 +00:00
test-vs-bittest.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
testb-je-fusion.ll
[X86] Make the post machine scheduler macrofusion-aware.
2019-04-03 09:37:30 +00:00
testl-commute.ll
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
2017-10-01 23:53:53 +00:00
this-return-64.ll
…
throws-cfi-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
throws-cfi-no-fp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
tls-addr-non-leaf-function.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
tls-android-negative.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
tls-android.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
tls-local-dynamic.ll
…
tls-models.ll
…
tls-no-plt.ll
[X86] -fno-plt: use GOT __tls_get_addr only if GOTPCRELX is enabled
2019-07-11 10:10:09 +00:00
tls-pic.ll
…
tls-pie.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
tls-shrink-wrapping.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
tls-windows-itanium.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
tls.ll
[X86] Support for the mno-tls-direct-seg-refs flag
2018-10-18 03:14:37 +00:00
tlv-1.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
tlv-2.ll
…
tlv-3.ll
…
token_landingpad.ll
…
trap.ll
…
tree_way_unsigned_cmp.ll
[NFC] Added test from PR19758
2019-06-09 15:12:46 +00:00
trunc-and.ll
[DAGCombiner][x86] prevent infinite loop from truncate/extend transforms
2019-08-05 11:27:07 +00:00
trunc-ext-ld-st.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
trunc-store.ll
[X86] Avoid icmp undef in reduced tests
2019-03-13 18:36:59 +00:00
trunc-subvector.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
trunc-to-bool.ll
[X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
2019-02-15 21:59:33 +00:00
TruncAssertSext.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
TruncAssertZext.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
twoaddr-coalesce-2.ll
…
twoaddr-coalesce-3.ll
…
twoaddr-coalesce.ll
…
twoaddr-dbg-value.mir
[CodeGen] Skip over dbg-instr in twoaddr pass
2019-01-03 08:36:06 +00:00
twoaddr-lea.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
twoaddr-pass-sink.ll
…
twoaddr-sink-terminator.ll
…
typeid-alias.ll
CodeGen: Don't follow aliases when extracting type info.
2019-08-02 17:43:45 +00:00
uadd_sat_vec.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
uadd_sat.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
uint64-to-float.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
uint_to_fp-2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
uint_to_fp-3.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
uint_to_fp.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
umul_fix.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
umul-with-carry.ll
…
umul-with-overflow.ll
[SDAG] Use shift amount type in MULO promotion; NFC
2019-02-19 17:37:55 +00:00
umulo-64-legalisation-lowering.ll
[SelectionDAG] Improve the legalisation lowering of UMULO.
2018-08-16 18:39:39 +00:00
umulo-128-legalisation-lowering.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
unaligned-32-byte-memops.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
unaligned-load.ll
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
2018-12-13 09:56:19 +00:00
unaligned-spill-folding.ll
…
undef-eflags.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
undef-globals-bss.ll
Place undefined globals in .bss instead of .data
2018-02-06 23:22:14 +00:00
undef-label.ll
[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.
2018-08-11 05:33:00 +00:00
undef-ops.ll
[SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC
2019-03-25 18:51:57 +00:00
unfold-masked-merge-scalar-constmask-innerouter.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
unfold-masked-merge-scalar-constmask-lowhigh.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
unfold-masked-merge-scalar-variablemask.ll
[DAGCombine] Fold (x & ~y) | y patterns
2019-03-17 15:45:38 +00:00
unfold-masked-merge-vector-variablemask-const.ll
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
2019-03-27 19:54:41 +00:00
unfold-masked-merge-vector-variablemask.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
unknown-location.ll
…
unreachable-loop-sinking.ll
…
unreachable-mbb-undef-phi.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unreachable-trap.ll
SelectionDAGBuilder, mach-o: Skip trap after noreturn call (for Mach-O)
2018-06-28 17:00:45 +00:00
unreachableblockelim.ll
…
unused_stackslots.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
unwind-init.ll
…
unwindraise.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
update-terminator-debugloc.ll
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
update-terminator.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
urem-i8-constant.ll
[x86] promote all multiply i8 by constant to i32
2018-11-26 15:22:30 +00:00
urem-power-of-two.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
urem-seteq-optsize.ll
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
2019-06-27 21:52:10 +00:00
urem-seteq-vec-nonsplat.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
urem-seteq-vec-splat.ll
[NFC][X86][AArch64] Revisit test coverage for X s% C == 0 fold - add tests for negative divisors, INT_MIN divisors
2019-07-30 08:00:49 +00:00
urem-seteq.ll
[NFC][X86][AArch64] Revisit test coverage for X s% C == 0 fold - add tests for negative divisors, INT_MIN divisors
2019-07-30 08:00:49 +00:00
use-add-flags.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
usub_sat_vec.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
usub_sat.ll
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
2019-08-11 19:27:14 +00:00
utf8.ll
…
utf16-cfstrings.ll
…
uwtables.ll
[X86] Remove powerpc cpu name and features from uwtables.ll
2018-08-30 06:01:01 +00:00
v2f32.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
v4f32-immediate.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
v4i32load-crash.ll
…
v8i1-masks.ll
[X86] Don't emit *_extend_vector_inreg nodes when both the input and output types are legal with AVX1
2018-11-02 21:09:49 +00:00
vaargs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx512-x86.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx512vl-x86.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx-x86.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
var-permute-128.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
var-permute-256.ll
[X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0))
2019-06-22 17:57:01 +00:00
var-permute-512.ll
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
2017-12-22 17:18:13 +00:00
vararg_no_start.ll
…
vararg_tailcall.ll
…
vararg-callee-cleanup.ll
…
variable-sized-darwin-bzero.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
variadic-node-pic.ll
Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models"
2018-07-23 21:14:35 +00:00
vastart-defs-eflags.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
vbinop-simplify-bug.ll
…
vec3.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_align_i256.ll
…
vec_align.ll
…
vec_anyext.ll
…
vec_call.ll
…
vec_cast2.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
vec_cast3.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
vec_cast.ll
[X86] Don't mark SEXTLOAD from v4i8/v4i16/v8i8 as Custom on pre-sse4.1.
2018-12-30 03:05:07 +00:00
vec_cmp_sint-128.ll
[X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32.
2018-10-09 19:05:50 +00:00
vec_cmp_uint-128.ll
[X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32.
2018-10-09 19:05:50 +00:00
vec_compare-sse4.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_compare.ll
[X86] Autogenerate complete checks. NFC
2018-10-09 17:52:07 +00:00
vec_ctbits.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_ext_inreg.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_extract-avx.ll
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
2019-06-21 19:10:21 +00:00
vec_extract-mmx.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_extract-sse4.ll
[DAGCombiner] after simplifying demanded elements of vector operand of extract, revisit the extract; 2nd try
2018-12-13 17:05:01 +00:00
vec_extract.ll
[X86][SSE] LowerINSERT_VECTOR_ELT - early out for out of range indices
2019-07-05 10:34:53 +00:00
vec_fabs.ll
[X86] Standardize floating point assembly comments
2018-10-02 09:08:51 +00:00
vec_floor.ll
[X86][InstCombine] Remove InstCombine code that turns X86 round intrinsics into llvm.ceil/floor. Remove some isel patterns that existed because that was happening.
2019-05-22 20:04:55 +00:00
vec_fneg.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
2019-06-13 19:24:51 +00:00
vec_fp_to_int.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_fpext.ll
[X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp extloads instead.
2019-05-31 06:21:53 +00:00
vec_fptrunc.ll
[x86] split 256-bit store of concatenated vectors
2019-06-04 16:40:04 +00:00
vec_i64.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_ins_extract-1.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_ins_extract.ll
…
vec_insert-2.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
vec_insert-3.ll
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support
2018-09-19 18:11:34 +00:00
vec_insert-4.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-5.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_insert-7.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_insert-8.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-9.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_insert-mmx.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_int_to_fp.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_loadsingles.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_logical.ll
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
2019-06-13 19:24:51 +00:00
vec_minmax_match.ll
[x86] increment/decrement constant vector with min/max in vsetcc lowering (PR39859)
2018-12-16 15:05:48 +00:00
vec_minmax_sint.ll
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
2019-07-23 15:35:55 +00:00
vec_minmax_uint.ll
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
2019-07-23 15:35:55 +00:00
vec_partial.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_reassociate.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_return.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_round.ll
…
vec_saddo.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_sdiv_to_shift.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-2.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-3.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-4.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-6.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-7.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-8.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-A.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-B.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-C.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-D.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-F.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_set-H.ll
[X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686)
2017-12-29 14:41:50 +00:00
vec_set.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_setcc-2.ll
[x86] use psubus for more vsetcc lowering (PR39859)
2019-04-23 15:20:17 +00:00
vec_setcc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_shift2.ll
[X86][SSE] Attempt to convert SSE shift-by-var to shift-by-imm.
2019-03-15 11:05:42 +00:00
vec_shift3.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_shift4.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
vec_shift5.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_shift6.ll
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
2018-07-10 07:58:33 +00:00
vec_shift7.ll
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
2018-07-17 09:45:35 +00:00
vec_shift.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_shuf-insert.ll
…
vec_smulo.ll
[X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
2019-08-13 10:51:39 +00:00
vec_split.ll
…
vec_ss_load_fold.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
vec_ssubo.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_trunc_sext.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_uaddo.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_udiv_to_shift.ll
…
vec_uint_to_fp-fastmath.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
vec_uint_to_fp.ll
[X86] Standardize floating point assembly comments
2018-10-02 09:08:51 +00:00
vec_umulo.ll
[X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
2019-08-13 10:51:39 +00:00
vec_unsafe-fp-math.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_usubo.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vec_zero_cse.ll
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
2019-03-04 19:12:16 +00:00
vec_zero-2.ll
…
vec_zero.ll
[X86][SSE] Regenerate vector zero tests
2019-03-05 16:52:14 +00:00
vec-copysign-avx512.ll
[X86] Stop promoting vector and/or/xor/andn to vXi64.
2018-10-26 17:21:26 +00:00
vec-copysign.ll
[X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
2019-01-22 13:44:49 +00:00
vec-libcalls.ll
[SelectionDAG] unroll unsupported vector FP ops earlier to avoid libcalls on undef elements (PR38527)
2018-08-22 22:52:05 +00:00
vec-loadsingles-alignment.ll
…
vec-trunc-store.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vecloadextract.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
vector_splat-const-shift-of-constmasked.ll
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
2019-05-14 20:17:04 +00:00
vector-bitreverse.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
vector-blend.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-compare-all_of.ll
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
2019-05-17 17:56:25 +00:00
vector-compare-any_of.ll
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
2019-05-17 17:56:25 +00:00
vector-compare-combines.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vector-compare-results.ll
[X86] Add a DAG combine to turn stores of vXi1 on pre-avx512 targets into a bitcast and a store of a iX scalar.
2018-12-02 19:47:14 +00:00
vector-compare-simplify.ll
[SelectionDAG] Support some SimplifySetCC cases for comparing against vector splats of constants.
2018-03-01 22:15:39 +00:00
vector-constrained-fp-intrinsics-fma.ll
[NFCI][FPEnv] Split constrained intrinsic tests
2018-11-05 15:28:10 +00:00
vector-constrained-fp-intrinsics.ll
[Strict FP] Allow custom operation actions
2019-08-06 10:43:13 +00:00
vector-ext-logic.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-extend-inreg.ll
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
2019-06-21 17:24:21 +00:00
vector-fshl-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshl-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshl-512.ll
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
2019-06-27 14:25:54 +00:00
vector-fshl-rot-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshl-rot-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshl-rot-512.ll
[SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit.
2019-07-27 12:48:46 +00:00
vector-fshr-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshr-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshr-512.ll
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
2019-06-27 14:25:54 +00:00
vector-fshr-rot-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshr-rot-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-fshr-rot-512.ll
[SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit.
2019-07-27 12:48:46 +00:00
vector-gep.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-half-conversions.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-idiv-sdiv-128.ll
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
2019-05-30 20:37:49 +00:00
vector-idiv-sdiv-256.ll
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
2019-05-30 20:37:49 +00:00
vector-idiv-sdiv-512.ll
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
2019-05-30 20:37:49 +00:00
vector-idiv-udiv-128.ll
[X86][SSE] Lower shuffle as ANY_EXTEND_VECTOR_INREG
2019-08-10 16:46:07 +00:00
vector-idiv-udiv-256.ll
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
2019-05-25 18:02:17 +00:00
vector-idiv-udiv-512.ll
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
2019-05-25 18:02:17 +00:00
vector-idiv-v2i32.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
vector-idiv.ll
[X86] Use a pcmpgt with 0 instead of psrad 31, to fill elements with the sign bit in v4i32 MULH lowering.
2018-11-19 07:22:26 +00:00
vector-interleave.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
vector-intrinsics.ll
…
vector-lzcnt-128.ll
[X86][SSE] Remove unnecessary bit-and in pshufb vector ctlz (PR39703)
2018-11-19 18:40:59 +00:00
vector-lzcnt-256.ll
[X86][SSE] Remove unnecessary bit-and in pshufb vector ctlz (PR39703)
2018-11-19 18:40:59 +00:00
vector-lzcnt-512.ll
[X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) fold.
2019-05-17 14:04:56 +00:00
vector-lzcnt-sub128.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
vector-merge-store-fp-constants.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vector-mul.ll
[X86] In decomposeMulByConstant, legalize the VT before querying whether the multiply is legal
2019-08-01 18:49:07 +00:00
vector-mulfix-legalize.ll
[SelectionDAG] Widen vector results of SMULFIX/UMULFIX/SMULFIXSAT
2019-08-11 19:27:06 +00:00
vector-narrow-binop.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-partial-undef.ll
[TargetLowering] try harder to determine undef elements of vector binops
2019-02-01 15:35:12 +00:00
vector-pcmp.ll
[SelectionDAG] computeKnownBits - support constant pool values from target
2019-05-24 10:03:11 +00:00
vector-popcnt-128.ll
[X86] In LowerHorizontalByteSum, emit vector_shuffle nodes instead of directly using X86ISD::UNPCKL/X86ISD::UNPCKH.
2018-11-10 00:26:42 +00:00
vector-popcnt-256.ll
[X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage.
2018-10-12 14:18:47 +00:00
vector-popcnt-512.ll
[X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage.
2018-10-12 14:18:47 +00:00
vector-reduce-add.ll
[X86] Add some reduction add test cases that show sub-optimal code on avx2 and later.
2019-08-12 06:55:58 +00:00
vector-reduce-and-bool.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-and.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-fadd-fast.ll
[X86] Regenerate fast fadd reduction tests. NFCI
2019-06-24 16:25:30 +00:00
vector-reduce-fadd.ll
Change semantics of fadd/fmul vector reductions.
2019-06-11 08:22:10 +00:00
vector-reduce-fmax-nnan.ll
Improve reduction intrinsics by overloading result value.
2019-06-13 09:37:38 +00:00
vector-reduce-fmax.ll
Improve reduction intrinsics by overloading result value.
2019-06-13 09:37:38 +00:00
vector-reduce-fmin-nnan.ll
Improve reduction intrinsics by overloading result value.
2019-06-13 09:37:38 +00:00
vector-reduce-fmin.ll
Improve reduction intrinsics by overloading result value.
2019-06-13 09:37:38 +00:00
vector-reduce-fmul-fast.ll
Change semantics of fadd/fmul vector reductions.
2019-06-11 08:22:10 +00:00
vector-reduce-fmul.ll
Change semantics of fadd/fmul vector reductions.
2019-06-11 08:22:10 +00:00
vector-reduce-mul.ll
Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT"
2019-08-13 09:33:25 +00:00
vector-reduce-or-bool.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-or.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-smax.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-smin.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-umax.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-umin.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-xor-bool.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-reduce-xor.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-rem.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vector-rotate-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-rotate-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-rotate-512.ll
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
2019-05-01 13:51:09 +00:00
vector-sext.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shift-ashr-128.ll
[DAGCombiner] don't hoist logic op if operands have other uses, part 2
2018-12-06 19:18:56 +00:00
vector-shift-ashr-256.ll
[DAGCombiner] try to move bitcast after extract_subvector
2019-05-12 14:43:20 +00:00
vector-shift-ashr-512.ll
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
2019-05-01 13:51:09 +00:00
vector-shift-ashr-sub128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shift-by-select-loop.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
vector-shift-lshr-128.ll
[CodeGenPrepare][x86] shift both sides of a vector select when profitable
2019-06-16 15:29:03 +00:00
vector-shift-lshr-256.ll
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
2019-05-01 13:51:09 +00:00
vector-shift-lshr-512.ll
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
2019-05-01 13:51:09 +00:00
vector-shift-lshr-sub128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shift-shl-128.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-shift-shl-256.ll
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
2019-08-07 11:43:13 +00:00
vector-shift-shl-512.ll
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
2019-05-01 13:51:09 +00:00
vector-shift-shl-sub128.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shuffle-128-unpck.ll
[x86] prevent infinite looping from inverse shuffle transforms
2019-03-08 19:20:28 +00:00
vector-shuffle-128-v2.ll
[X86] In lowerVectorShuffle, instead of creating a new node to canonicalize the shuffle mask by commuting, just commute the mask and swap V1/V2.
2019-07-23 18:46:15 +00:00
vector-shuffle-128-v4.ll
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
2019-07-09 19:55:28 +00:00
vector-shuffle-128-v8.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
vector-shuffle-128-v16.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shuffle-256-v4.ll
[X86][AVX] Add PR34359 shuffle test case.
2019-07-12 17:42:32 +00:00
vector-shuffle-256-v8.ll
[X86][SSE] Lower shuffle as ANY_EXTEND_VECTOR_INREG
2019-08-10 16:46:07 +00:00
vector-shuffle-256-v16.ll
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
2019-07-04 10:17:10 +00:00
vector-shuffle-256-v32.ll
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
2019-07-04 10:17:10 +00:00
vector-shuffle-512-v8.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
vector-shuffle-512-v16.ll
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
2019-07-03 15:46:08 +00:00
vector-shuffle-512-v32.ll
[X86][AVX] SimplifyDemandedVectorElts - combine PERMPD(x) -> EXTRACTF128(X)
2019-06-27 11:16:03 +00:00
vector-shuffle-512-v64.ll
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
2019-04-28 14:31:01 +00:00
vector-shuffle-avx512.ll
[X86][AVX] Support shuffle combining for VBROADCAST with smaller vector sources
2019-02-03 16:51:33 +00:00
vector-shuffle-combining-avx2.ll
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
2019-06-21 17:24:21 +00:00
vector-shuffle-combining-avx512bw.ll
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
2019-06-15 17:05:24 +00:00
vector-shuffle-combining-avx512bwvl.ll
[X86][SSE] Cleanup shuffle combining test check prefixes
2019-01-09 13:46:14 +00:00
vector-shuffle-combining-avx512vbmi.ll
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
2019-04-28 14:31:01 +00:00
vector-shuffle-combining-avx.ll
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
2019-06-15 17:05:24 +00:00
vector-shuffle-combining-sse4a.ll
[X86][SSE] Cleanup shuffle combining test check prefixes
2019-01-09 13:46:14 +00:00
vector-shuffle-combining-sse41.ll
[X86][SSE] Cleanup shuffle combining test check prefixes
2019-01-09 13:46:14 +00:00
vector-shuffle-combining-ssse3.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
vector-shuffle-combining-xop.ll
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
2019-06-15 17:05:24 +00:00
vector-shuffle-combining.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-shuffle-masked.ll
[X86] Add isel patterns for selecting masked SUBV_BROADCAST with bitcasts. Remove combineBitcastForMaskedOp.
2018-02-05 08:37:37 +00:00
vector-shuffle-mmx.ll
[X86][MMX] Improve handling of 64-bit MMX constants
2018-03-01 22:22:31 +00:00
vector-shuffle-sse1.ll
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
2019-07-15 02:02:31 +00:00
vector-shuffle-sse4a.ll
[X86][SSE] Use PSLLDQ/PSRLDQ to mask out zeroable ends of a shuffle
2019-02-01 16:02:12 +00:00
vector-shuffle-sse41.ll
[X86][SSE] Add SimplifyDemandedVectorElts support for PACKSS/PACKUS instructions.
2018-11-20 11:09:46 +00:00
vector-shuffle-v1.ll
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
2019-06-25 10:51:15 +00:00
vector-shuffle-v48.ll
[X86][SSE] Regenerate v48 shuffle test on a variety of targets
2019-06-27 11:22:23 +00:00
vector-shuffle-variable-128.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
vector-shuffle-variable-256.ll
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
2019-07-06 17:59:57 +00:00
vector-sqrt.ll
[X86] Merge the FR128 and VR128 regclass since they have identical spill and alignment characteristics.
2018-07-16 06:56:09 +00:00
vector-trunc-math.ll
[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.
2019-07-22 19:58:49 +00:00
vector-trunc-packus.ll
[X86] Allow combineTruncateWithSat to use pack instructions for i16->i8 without AVX512BW.
2019-08-12 22:18:23 +00:00
vector-trunc-ssat.ll
[X86] Allow combineTruncateWithSat to use pack instructions for i16->i8 without AVX512BW.
2019-08-12 22:18:23 +00:00
vector-trunc-usat.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-trunc.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
vector-truncate-combine.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-tzcnt-128.ll
[X86] In LowerHorizontalByteSum, emit vector_shuffle nodes instead of directly using X86ISD::UNPCKL/X86ISD::UNPCKH.
2018-11-10 00:26:42 +00:00
vector-tzcnt-256.ll
[X86][SSE] combineIncDecVector - use isConstantSplat
2018-10-13 14:45:44 +00:00
vector-tzcnt-512.ll
[X86] Stop promoting vector and/or/xor/andn to vXi64.
2018-10-26 17:21:26 +00:00
vector-unsigned-cmp.ll
[X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32.
2018-10-09 19:05:50 +00:00
vector-variable-idx2.ll
…
vector-variable-idx.ll
…
vector-width-store-merge.ll
Make sure that the DAG combiner doesn't merge stores that we explicitly
2019-05-07 19:25:34 +00:00
vector-zext.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vector-zmov.ll
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load
2019-06-25 17:08:26 +00:00
vector.ll
…
vectorcall.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
version_directive.ll
…
vfcmp.ll
…
viabs.ll
[X86] Improve vXi64 ISD::ABS codegen with SSE41+
2019-01-12 10:28:12 +00:00
virtreg-physreg-def-regallocfast.mir
[RegAllocFast] Scan physcial reg definitions before assigning virtual reg definitions
2019-05-08 18:30:26 +00:00
virtual-registers-cleared-in-machine-functions-liveins.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
visibility2.ll
…
visibility.ll
…
vmaskmov-offset.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
vmovq.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
volatile-memstores-nooverlapping-load-stores.ll
Fixing @llvm.memcpy not honoring volatile.
2019-07-09 09:53:36 +00:00
volatile.ll
…
vortex-bug.ll
…
vp2intersect_multiple_pairs.ll
[X86] Regenerate vp2intersect tests
2019-07-31 12:17:10 +00:00
vpshufbitqbm-intrinsics-upgrade.ll
[X86] Add new test file that was supposed to go with r351028.
2019-01-14 08:46:42 +00:00
vpshufbitqbm-intrinsics.ll
[X86] Remove mask parameter from vpshufbitqmb intrinsics. Change result to a vXi1 vector.
2019-01-14 00:03:50 +00:00
vsel-cmp-load.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vselect-2.ll
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
2019-07-08 06:52:49 +00:00
vselect-avx.ll
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
2019-08-13 14:57:37 +00:00
vselect-constants.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vselect-minmax.ll
[X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32.
2018-10-09 19:05:50 +00:00
vselect-packss.ll
[X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.
2018-11-09 19:05:51 +00:00
vselect-pcmp.ll
[X86] Add custom execution domain fixing for 128/256-bit integer logic operations with AVX512F, but not AVX512DQ.
2018-07-15 23:32:36 +00:00
vselect-zero.ll
[x86] limit transform for select-of-fp-constants
2018-11-25 17:27:02 +00:00
vselect.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vshift_scalar.ll
…
vshift_split2.ll
…
vshift_split.ll
…
vshift-1.ll
[X86][SSE] Add SimplifyDemandedVectorElts support for SSE splat-vector-shifts.
2018-11-18 20:21:52 +00:00
vshift-2.ll
[X86][SSE] Add SimplifyDemandedVectorElts support for SSE splat-vector-shifts.
2018-11-18 20:21:52 +00:00
vshift-3.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vshift-4.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
vshift-5.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vshift-6.ll
[X86] Move promotion of vector and/or/xor from legalization to DAG combine
2018-10-15 01:51:58 +00:00
vsplit-and.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vzero-excess.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
waitpkg-intrinsics.ll
[X86] WaitPKG instructions
2018-04-20 18:42:47 +00:00
warn-stack.ll
…
wbinvd-intrinsic.ll
[X86] Introduce LLVM wbinvd intrinsic
2018-04-12 18:38:18 +00:00
wbnoinvd-intrinsic.ll
[X86] Describe wbnoinvd instruction
2018-04-11 20:01:57 +00:00
weak_def_can_be_hidden.ll
…
weak-undef.ll
Handle undefined weak hidden symbols on all architectures.
2017-10-27 21:18:48 +00:00
weak.ll
…
webkit-jscc.ll
…
wide-fma-contraction.ll
AMD BdVer2 (Piledriver) Initial Scheduler model
2018-10-27 20:46:30 +00:00
wide-integer-cmp.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
wide-integer-fold.ll
…
widen_arith-1.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_arith-2.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_arith-3.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_arith-4.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_arith-5.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_arith-6.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_bitops-0.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_bitops-1.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
widen_cast-1.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_cast-2.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_cast-3.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_cast-4.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
widen_cast-5.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_cast-6.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_compare-1.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_conv-1.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_conv-2.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_conv-3.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_conv-4.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_conversions.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
widen_extract-1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
widen_load-0.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
widen_load-1.ll
[X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
2018-10-11 20:36:06 +00:00
widen_load-2.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
widen_load-3.ll
[x86] avoid vector load narrowing with extracted store uses (PR42305)
2019-06-19 18:13:47 +00:00
widen_mul.ll
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
2019-08-07 16:33:37 +00:00
widen_shuffle-1.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
WidenArith.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
widened-broadcast.ll
[X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcasts
2019-03-13 12:20:39 +00:00
win32_sret.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
win32-bool.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
win32-eh-available-externally.ll
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
win32-eh-states.ll
…
win32-eh.ll
…
win32-pic-jumptable.ll
[MC] Suppress .Lcfi labels when emitting textual assembly
2017-10-10 00:57:36 +00:00
win32-preemption.ll
Represent runtime preemption in the IR.
2017-10-26 15:00:26 +00:00
win32-seh-catchpad-realign.ll
…
win32-seh-catchpad.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
win32-seh-nested-finally.ll
…
win32-spill-xmm.ll
…
win32-ssp.ll
[MinGW] [X86] Add stubs for references to data variables that might end up imported from a dll
2018-08-29 17:28:34 +00:00
win64_alloca_dynalloca.ll
…
win64_call_epi.ll
…
win64_eh_leaf2.ll
…
win64_eh_leaf.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
win64_eh.ll
…
win64_frame.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
win64_nonvol.ll
…
win64_params.ll
…
win64_sibcall.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
win64_vararg.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
win64-bool.ll
[X86] Fix Windows i1 zeroext conventions to use i8 instead of i32
2018-03-26 18:49:48 +00:00
win64-byval.ll
[X86ISel] Implement byval lowering for Win64 calling convention
2018-09-17 17:37:14 +00:00
win64-funclet-savexmm.ll
[WinEH] Fix catch block parent frame pointer offset
2019-08-12 23:02:00 +00:00
win64-jumptable.ll
…
win64-long-double.ll
[X86] Properly implement the calling convention for f80 for mingw/x86_64
2018-03-20 06:19:38 +00:00
win64-nosse-csrs.ll
…
win_chkstk.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
win_coreclr_chkstk_liveins.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
win_coreclr_chkstk.ll
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
2019-05-25 06:17:47 +00:00
win_cst_pool.ll
Standardize on MSVC behavior for triples with no environment
2019-07-08 21:05:20 +00:00
win-alloca-expander.ll
…
win-catchpad-csrs.ll
…
win-catchpad-nested-cxx.ll
…
win-catchpad-nested.ll
…
win-catchpad-varargs.ll
…
win-catchpad.ll
…
win-cleanuppad.ll
…
win-funclet-cfi.ll
…
win-mixed-ehpersonality.ll
…
win-smallparams.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
windows-itanium-alloca.ll
…
wineh-coreclr.ll
…
wineh-exceptionpointer.ll
…
wineh-no-ehpads.ll
…
x32-cet-intrinsics.ll
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
2018-05-18 11:58:25 +00:00
x32-function_pointer-1.ll
…
x32-function_pointer-2.ll
…
x32-function_pointer-3.ll
…
x32-indirectbr.ll
…
x32-landingpad.ll
…
x32-lea-1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
x32-movtopush64.ll
…
x32-va_start.ll
…
x64-cet-intrinsics.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
x86_64-mul-by-const.ll
…
x86-16.ll
…
x86-32-intrcc.ll
[X86] Fix bug in x86_intrcc with arg copy elision
2019-02-26 02:11:25 +00:00
x86-32-vector-calling-conv.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-baseptr.ll
[X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 during isel.
2019-04-04 05:00:18 +00:00
x86-64-bittest-logic.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
x86-64-call.ll
…
x86-64-disp.ll
…
x86-64-double-precision-shift-left.ll
[X86] Regenerate double shift tests
2018-01-13 16:55:28 +00:00
x86-64-double-precision-shift-right.ll
[X86] Regenerate double shift tests
2018-01-13 16:55:28 +00:00
x86-64-double-shifts-Oz-Os-O2.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
x86-64-double-shifts-var.ll
[X86] AMD znver2 enablement
2019-02-26 16:55:10 +00:00
x86-64-extend-shift.ll
…
x86-64-flags-intrinsics.ll
…
x86-64-gv-offset.ll
…
x86-64-intrcc-nosse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
x86-64-intrcc.ll
[X86] Fix bug in x86_intrcc with arg copy elision
2019-02-26 02:11:25 +00:00
x86-64-jumps.ll
…
x86-64-mem.ll
…
x86-64-ms_abi-vararg.ll
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
2019-03-13 17:07:09 +00:00
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
…
x86-64-pic-5.ll
…
x86-64-pic-6.ll
…
x86-64-pic-7.ll
…
x86-64-pic-8.ll
…
x86-64-pic-9.ll
…
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-pic-12.ll
…
x86-64-pic.ll
…
x86-64-plt-relative-reloc.ll
…
x86-64-psub.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-64-ptr-arg-simple.ll
…
x86-64-ret0.ll
…
x86-64-shortint.ll
…
x86-64-sret-return-2.ll
…
x86-64-sret-return.ll
…
x86-64-stack-and-frame-ptr.ll
…
x86-64-static-relo-movl.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
x86-64-tls-1.ll
…
x86-64-varargs.ll
…
x86-64-veccallcc.ll
[X86] Fix bug in vectorcall calling convention
2019-02-26 19:48:16 +00:00
x86-big-ret.ll
…
x86-cmov-converter.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
x86-flags-intrinsics.ll
…
x86-fold-pshufb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
x86-framelowering-trap.ll
Correct dwarf unwind information in function epilogue
2018-04-24 10:32:08 +00:00
x86-inline-asm-validation.ll
…
x86-interleaved-access.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
x86-interleaved-check.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
x86-interrupt_cc.ll
[WinEH] Allocate space in funclets stack to save XMM CSRs
2019-07-26 07:33:15 +00:00
x86-interrupt_cld.ll
…
x86-interrupt_vzeroupper.ll
…
x86-mixed-alignment-dagcombine.ll
…
x86-no_caller_saved_registers-preserve.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
x86-no_caller_saved_registers.ll
…
x86-plt-relative-reloc.ll
…
x86-repmov-copy-eflags.ll
[x86] Switch EFLAGS copy lowering to use reg-reg form of testing for
2018-04-18 15:52:50 +00:00
x86-sanitizer-shrink-wrapping.ll
…
x86-setcc-int-to-fp-combine.ll
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
2018-10-29 04:52:04 +00:00
x86-shifts.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
x86-shrink-wrap-unwind.ll
[X86] improve split-stack machine BB placement
2018-11-07 17:41:57 +00:00
x86-shrink-wrapping.ll
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
2019-06-25 17:29:18 +00:00
x86-store-gv-addr.ll
…
x86-upgrade-avx2-vbroadcast.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
x86-upgrade-avx-vbroadcast.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
x86-win64-shrink-wrapping.ll
[MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM
2018-12-05 03:41:26 +00:00
x87.ll
[X86] Correctly use SSE registers if no-x87 is selected.
2018-10-03 14:13:30 +00:00
xaluo.ll
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
2019-04-09 18:33:56 +00:00
xchg-nofold.ll
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
2019-06-13 13:56:19 +00:00
xmm-r64.ll
…
xmulo.ll
[X86] Add load folding support to the custom isel we do for X86ISD::UMUL/SMUL.
2019-01-02 23:24:08 +00:00
xop-ifma.ll
Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."
2019-06-25 01:32:42 +00:00
xop-intrinsics-fast-isel.ll
[X86] Replace VPCOM/VPCOMU with generic integer comparisons (llvm)
2019-01-20 16:40:44 +00:00
xop-intrinsics-x86_64-upgrade.ll
[X86] Auto upgrade VPCOM/VPCOMU intrinsics to generic integer comparisons
2019-01-20 19:27:40 +00:00
xop-intrinsics-x86_64.ll
[X86] Auto upgrade VPCOM/VPCOMU intrinsics to generic integer comparisons
2019-01-20 19:27:40 +00:00
xop-mask-comments.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
xop-pcmov.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
xor-combine-debugloc.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
xor-icmp.ll
[X86] Only reorder srl/and on last DAG combiner run
2018-02-16 18:51:09 +00:00
xor-select-i1-combine.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
xor.ll
Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT"
2019-08-13 09:33:25 +00:00
xray-attribute-instrumentation.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-custom-log.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-empty-firstmbb.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
xray-empty-function.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
xray-log-args.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-loop-detection.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-multiplerets-in-blocks.mir
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-section-group.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-selective-instrumentation-miss.ll
…
xray-selective-instrumentation.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-tail-call-sled.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xray-typed-event-log.ll
[XRay] Fix machine verifier issues in X86
2018-07-12 14:36:43 +00:00
xtest.ll
…
zero-remat.ll
…
zext-demanded.ll
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
2019-03-27 19:54:41 +00:00
zext-extract_subreg.ll
[DAG] add undef simplifications for select nodes
2018-11-18 17:36:23 +00:00
zext-fold.ll
[x86] shrink 'and' immediate values by setting the high bits (PR35907)
2018-01-19 16:37:25 +00:00
zext-inreg-0.ll
…
zext-inreg-1.ll
…
zext-logicop-shift-load.ll
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
2019-04-12 06:49:28 +00:00
zext-sext.ll
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
2019-05-30 20:36:54 +00:00
zext-shl.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
zext-trunc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
zlib-longest-match.ll
…