Commit Graph

137462 Commits

Author SHA1 Message Date
Rafael Espindola
1a56948cc9 Move code only used by codegen out of MC. NFC.
MC itself never needs to know about these sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279965 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 12:33:42 +00:00
Haojian Wu
1801e2fa13 Fix -Wunused-but-set-variable warning.
Summary: A follow-up fix on r279958.

Reviewers: bkramer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23989

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279964 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 12:26:33 +00:00
Tom Stellard
675d6994e8 AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()
Summary:
The SILoadStoreOptimizer will need to use AliasAnalysis here in order to
move it before scheduling.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D23813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279963 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 12:05:32 +00:00
Igor Breger
922af1cb46 Fixed a bug in type legalizer for masked gather.
The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist.
In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain).

Differential Revision: http://reviews.llvm.org/D23756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279961 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 09:12:31 +00:00
Igor Breger
84cb7f4d14 [AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.
Differential Revision: http://reviews.llvm.org/D23490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279960 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 08:52:52 +00:00
Haojian Wu
f0a2d5f1a0 [InstructionSelect] NumBlocks isn't defined in DEBUG build.
Summary: A follow-up fixing on http://llvm.org/viewvc/llvm-project?view=revision&revision=279905.

Reviewers: bkramer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23985

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279959 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 08:48:15 +00:00
Craig Topper
51b695a52e [X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just create a ConstantFPSDNode and let that be lowered.
This allows broadcast loads to used when available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279958 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 04:49:31 +00:00
Craig Topper
79711e4f46 [AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer operations when DQI isn't supported. This is consistent with the recent changes to promote logical operations to i64 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279957 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 04:49:27 +00:00
Craig Topper
040e63ae36 [AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279956 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 04:49:24 +00:00
Lang Hames
572aa19a18 [Orc] Simplify LogicalDylib and move it back inside CompileOnDemandLayer. Also
switch to using one indirect stub manager per logical dylib rather than one per
input module.

LogicalDylib is a helper class used by the CompileOnDemandLayer to manage
symbol resolution between modules during lazy compilation. In particular, it
ensures that internal symbols resolve correctly even in the case where multiple
input modules contain the same internal symbol name (which must to be promoted
to external hidden linkage so that functions in any given module can be split
out by lazy compilation). LogicalDylib's resolution scheme (before this commit)
required one stub-manager per input module. This made recompilation of functions
(by adding a module containing a new definition) difficult, as the stub manager
for any given symbol was bound to the module that supplied the original
definition. By using one stubs manager for the whole logical dylib symbols can
be more easily replaced, although support for doing this is not included in this
patch (it will be implemented in a follow up).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279952 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29 00:54:29 +00:00
Craig Topper
75d518389c [AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279951 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 22:20:51 +00:00
Craig Topper
4d4300a816 [AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279950 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 22:20:48 +00:00
Craig Topper
28dc9c9b12 [AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. Will be fixed in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279949 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 22:20:45 +00:00
Sylvestre Ledru
297f179ffa Fix some typos in the doc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279943 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 20:29:18 +00:00
Sanjay Patel
481aed7978 [x86] add tests for <3 x N> vector types (PR29114)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279939 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 18:31:32 +00:00
Sanjay Patel
2c15995350 [InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat constant vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279937 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 18:18:00 +00:00
Simon Pilgrim
337ddd9188 [X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same number of vector elements
Over eager combing prevents the correct folding of writemasks.

At the moment this occurs for ALL EVEX shuffles, in the future we need to check that the user of the root shuffle is a VSELECT that can fold to a writemask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279934 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 17:27:14 +00:00
Hal Finkel
afa0d1049b [PowerPC] Implement lowering for atomicrmw min/max/umin/umax
Implement lowering for atomicrmw min/max/umin/umax. Fixes PR28818.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279933 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 16:17:58 +00:00
Elena Demikhovsky
1b2a8500af [Loop Vectorizer] Fixed memory confilict checks.
Fixed a bug in run-time checks for possible memory conflicts inside loop.
The bug is in Low <-> High boundaries calculation. The High boundary should be calculated as "last memory access pointer + element size".

Differential revision: https://reviews.llvm.org/D23176



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279930 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 08:53:53 +00:00
Craig Topper
800ba955e3 [AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.
Previously we weren't creating masked logical operations if bitcasts appeared between the logic operation and the select. The IR optimizers can move bitcasts across logic operations and create these cases. To minimize the number of cases we need to handle, this change promotes all logic ops to an i64 vector type just like when only SSE or AVX is available.

Unfortunately, this also has the consequence of making it difficult to select unmasked VPANDD/VPORD/VPXORD in all the cases it was previously used. This is the cause of most of the test change. This shouldn't result in any functional change though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279929 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 06:06:28 +00:00
Craig Topper
2e47cee376 [AVX-512] Add tests to show that we don't select masked logic ops if there are bitcasts between the logic op and the select.
This is taken from optimized IR of clang test cases for masked logic ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279928 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 06:06:24 +00:00
Craig Topper
460412aab8 [X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instead of ending 128/256. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279927 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-28 06:06:21 +00:00
Jan Vesely
3ed393863d AMDGPU/R600: Enable Load combine
Fix and improve tests

Differential Revision: https://reviews.llvm.org/D23899

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279925 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 19:09:43 +00:00
Craig Topper
53e8717515 [X86] Rename predicate function that detects if requires one of the REX.B, REX.X or REX.R bits. It's old name conflicted with a function in X8II namespace that doesnt' quite do the same thing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279924 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 17:13:43 +00:00
Craig Topper
7b84fc34ba [X86] Keep looping over operands looking for byte registers even if we already found a register that requires a REX prefix. Otherwise we don't error if a high byte register is used after SPL/BPL/DIL/SIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279923 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 17:13:41 +00:00
Craig Topper
b70cda8a99 [X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more consistent with its name and simplifies assembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279922 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 17:13:37 +00:00
Craig Topper
8b5392fd41 [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279921 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 17:13:34 +00:00
Craig Topper
a733d39899 [X86] Remove stale comment about FixupBWInsts pass being off by default. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279915 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 05:26:54 +00:00
Craig Topper
63994250fd [AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/SD to be commuted just like the SSE and AVX counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279914 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 05:22:15 +00:00
Craig Topper
ffbe7018fa [X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279913 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 05:22:12 +00:00
Craig Topper
9c6419de84 [AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279912 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 05:22:08 +00:00
Teresa Johnson
2b799fdb18 [LTO] Don't create a new common unless merged has different size
Summary:
This addresses a regression in common handling from the new LTO
API in r278338. Only create a new common if the size is different.
The type comparison against an array type fails when the size is
different but not an array. GlobalMerge does not handle the
array types as well and we lose some global merging opportunities.

Reviewers: mehdi_amini

Subscribers: junbuml, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279911 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 04:41:22 +00:00
Matt Arsenault
8b9a56b8e1 AMDGPU: Mark sched model complete
Fixes bug 26800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279910 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 03:39:27 +00:00
Matt Arsenault
6441d238c1 AMDGPU: Remove unneeded implicit exec uses/defs
SI_BREAK, SI_IF_BREAK, and SI_ELSE_BREAK do not def exec.
SI_IF_BREAK and SI_ELSE_BREAK do not read it either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279909 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 03:00:51 +00:00
Lang Hames
a59e27b537 [Orc] Explicitly specify type for assignment.
This should fix the MSVC errors in
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15120



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279908 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 02:59:24 +00:00
Sebastian Pop
fab5bb8a6c GVN-hoist: invalidate MD cache (PR29144)
Without invalidating the entries in the MD cache we would try to access instructions
that were removed in previous iterations of hoisting.

Differential Revision: https://reviews.llvm.org/D23927

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279907 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 02:48:41 +00:00
Quentin Colombet
529dc06de0 [RegBankSelect] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279906 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 02:38:27 +00:00
Quentin Colombet
16b39f4d7f [InstructionSelect] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279905 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 02:38:24 +00:00
Quentin Colombet
bbef3e060a [MachineLegalize] Do not abort when the target wants to fall back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279904 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 02:38:21 +00:00
Matt Arsenault
95ec13b22a AMDGPU: Select mulhi 24-bit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 01:32:27 +00:00
Matt Arsenault
e52dfc95ef AMDGPU: Move cndmask pseudo to be isel pseudo
There's only one use of this for the convenience
of a pattern. I think v_mov_b64_pseudo should also be
moved, but SIFoldOperands does currently make use of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279901 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 01:00:37 +00:00
Matt Arsenault
f5dc5ec299 AMDGPU: Fix sched type for branches
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279900 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:51:02 +00:00
Matt Arsenault
36a8c3e60f AMDGPU: Remove register operand from si_mask_branch
It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279899 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:42:21 +00:00
Matt Arsenault
d97fe48fe0 AMDGPU: Improve error reporting for maximum branch distance
Unfortunately this seems to only help the assembler diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279895 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:21:22 +00:00
Chris Bieneman
4ec9567b37 [CMake] Only generate Components.cmake if components are specified
Generating the Components import file is useless if there are no components coming in from the runtimes configuration, so we should skip generation in that case.

This also should fix the configuration error that Renato reported on llvm-dev.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:19:51 +00:00
Lang Hames
fd6bad6c38 [ORC] Fix typo in LogicalDylib, add unit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:19:05 +00:00
Quentin Colombet
c47e5db5f7 [GlobalISel] Add a fallback path to SDISel.
When global-isel fails on a MachineFunction MF, MF will be cleaned up
and given to SDISel.
Thanks to this fallback, we can already perform correctness test even if
we support only a small portion of the functions in a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279891 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:18:31 +00:00
Quentin Colombet
1dba46c5a7 [AArch64][CallLowering] Do not assert for not implemented part.
When doing the ABI lowering, report a failure to the caller instead of
asserting. This gives a chance for the caller to recover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279890 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:18:28 +00:00
Quentin Colombet
411fc079bb [GlobalISel] Teach the core pipeline not to run if ISel failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279889 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:18:24 +00:00
Michael Kuperstein
b274272581 [X86] Add baseline test for "odd" shuffles. NFC.
Adds a baseline test for lowering shuffles where the width of the output
vector is not twice the size of the input vectors. Many of those sequences
are suboptimal, and will hopefully be improved in follow-up patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279888 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:10:24 +00:00