1595 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
36d7c2b2e5 Move size and alignment information of regclass to TargetRegisterInfo
1. RegisterClass::getSize() is split into two functions:
   - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const;
   - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const;
2. RegisterClass::getAlignment() is replaced by:
   - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const;

This will allow making those values depend on subtarget features in the
future.

Differential Revision: https://reviews.llvm.org/D31783


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301221 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-24 18:55:33 +00:00
Renato Golin
d907744fff Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."
This reverts commit r301105, 4, 3 and 1, as a follow up of the previous
revert, which broke even more bots.

For reference:
Revert "[APInt] Use operator<<= where possible. NFC"
Revert "[APInt] Use operator<<= instead of shl where possible. NFC"
Revert "[APInt] Use ashInPlace where possible."

PR32754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 12:15:30 +00:00
Craig Topper
aeda136605 [APInt] Fix a few places that use APInt::getRawData to operate within the normal API.
getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail.

This patch fixes a few of the easy cases by using truncate, extract, or a rotate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301105 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-23 06:41:11 +00:00
Krzysztof Parzyszek
d9552968c4 [Hexagon] Generate proper offset in opt-addr-mode
Also, make a few changes to allow using the pass in .mir testcases.
Among other things, change the abbreviation from opt-amode to amode-opt,
because otherwise lit would expand the "opt" part to the full path to
the opt binary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300707 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:15:51 +00:00
Krzysztof Parzyszek
f6728e6d7d [Hexagon] Remove RDefMap, use Liveness:getNearestAliasedRef instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:14:30 +00:00
Krzysztof Parzyszek
ad6758286a [RDF] Switch NodeList to SmallVector from std::vector
The list has a single element 75+% of the time, reservation of 4 elements
is sufficient in 95% of cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300705 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:12:44 +00:00
Krzysztof Parzyszek
1896b7912b [RDF] Use faster version of findBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300704 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:11:23 +00:00
Krzysztof Parzyszek
111ac46fe7 [RDF] Cache register units for reg masks instead of recalculating them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300702 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:10:09 +00:00
Krzysztof Parzyszek
cfaa15d905 [Hexagon] Cache reached blocks in bit tracker instead of scanning list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300701 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:08:31 +00:00
Matt Arsenault
663bdf65c5 DAG: Make mayBeEmittedAsTailCall parameter const
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300603 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-18 21:16:46 +00:00
Krzysztof Parzyszek
ce27c612e6 [RDF] No longer ignore implicit defs or uses on any instructions
This used to be a Hexagon-specific treatment, but is no longer needed
since it's switched to subregister liveness tracking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300369 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 21:19:17 +00:00
Krzysztof Parzyszek
05d022e31e [RDF] Correctly enumerate reg units for reg masks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300368 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 21:17:36 +00:00
Krzysztof Parzyszek
0e9e7d51d9 [RDF] Switch RegisterAggr to a bit vector of register units
This avoids many complications related to the complex register
aliasing schemes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 17:25:13 +00:00
Krzysztof Parzyszek
58bea371b9 [RDF] Refine propagation of reached uses in liveness computation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300337 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 16:33:54 +00:00
Krzysztof Parzyszek
3a98382e18 [Hexagon] Fix a latent problem with interpreting live-in lane masks
A non-zero lane mask on a register with no subregister means that the
whole register is live-in. It is equivalent to a full mask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300335 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 16:21:55 +00:00
Krzysztof Parzyszek
c7e0860814 [Hexagon] Make a couple of passes compliant with -opt-bisect-limit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300329 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 15:26:34 +00:00
Andrew V. Tischenko
3796561c6e This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs.
The details are here: https://reviews.llvm.org/D30941


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300311 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 07:44:23 +00:00
Krzysztof Parzyszek
7fa51d159a [Hexagon] Implement HexagonTargetLowering::CanLowerReturn
Patch by Michael Wu.

Differential Revision: https://reviews.llvm.org/D32000


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300199 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-13 15:05:51 +00:00
Krzysztof Parzyszek
db734f0a3d [Hexagon] Fix "LowerFormalArguments emitted a value with the wrong type!" assertion
Patch by Michael Wu.

Differential Revision: https://reviews.llvm.org/D31999


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300198 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-13 15:00:18 +00:00
Serge Guelton
9d54400bba Module::getOrInsertFunction is using C-style vararg instead of variadic templates.
From a user prospective, it forces the use of an annoying nullptr to mark the end of the vararg, and there's not type checking on the arguments.
The variadic template is an obvious solution to both issues.

Differential Revision: https://reviews.llvm.org/D31070



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299949 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-11 15:01:18 +00:00
Diana Picus
1d02724c71 Revert "Turn some C-style vararg into variadic templates"
This reverts commit r299925 because it broke the buildbots. See e.g.
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/6008

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299928 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-11 10:07:12 +00:00
Serge Guelton
ec124b3a6f Turn some C-style vararg into variadic templates
Module::getOrInsertFunction is using C-style vararg instead of
variadic templates.

From a user prospective, it forces the use of an annoying nullptr
to mark the end of the vararg, and there's not type checking on the
arguments. The variadic template is an obvious solution to both
issues.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-11 08:36:52 +00:00
Krzysztof Parzyszek
6cf90d3647 [Hexagon] Change the vector scaling for vector offsets
Keep full offset value on MI-level instructions, but have it scaled down
in the MC-level instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299664 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 17:28:21 +00:00
Alex Bradbury
ff1254b6f8 Add MCContext argument to MCAsmBackend::applyFixup for error reporting
A number of backends (AArch64, MIPS, ARM) have been using
MCContext::reportError to report issues such as out-of-range fixup values in
their TgtAsmBackend. This is great, but because MCContext couldn't easily be
threaded through to the adjustFixupValue helper function from its usual
callsite (applyFixup), these backends ended up adding an MCContext* argument
and adding another call to applyFixup to processFixupValue. Adding an
MCContext parameter to applyFixup makes this unnecessary, and even better -
applyFixup can take a reference to MCContext rather than a potentially null
pointer.

Differential Revision: https://reviews.llvm.org/D30264


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 10:16:14 +00:00
Krzysztof Parzyszek
ab1bde3393 [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299367 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:26:40 +00:00
Craig Topper
68149f546e [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt class. Implement them without memory allocation for multiword
This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation.

Differential Revision: https://reviews.llvm.org/D31565




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299362 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 16:34:59 +00:00
Krzysztof Parzyszek
9a9ab69f85 [Hexagon] Remove unused variables
Found by PVS-Studio. Fixes llvm.org/PR31676.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299262 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31 21:03:59 +00:00
Krzysztof Parzyszek
8b1380a009 [Hexagon] Fix typo in HexagonEarlyIfCConv.cpp
Found by PVS-Studio. Fixes llvm.org/PR32480.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299258 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31 20:36:00 +00:00
Krzysztof Parzyszek
cfb0063c60 [Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognition
- Avoid explosive growth of the simplification queue by not queuing
  expressions that are alredy in it.
- Add an iteration counter and abort after a sufficiently large number
  of iterations (assuming that it's a symptom of an infinite loop).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298655 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-23 23:01:22 +00:00
Krzysztof Parzyszek
32a326f95b Recommit r298282 with fixes for memory allocation/deallocation
[Hexagon] Recognize polynomial-modulo loop idiom again

Regain the ability to recognize loops calculating polynomial modulo
operation. This ability has been lost due to some changes in the
preceding optimizations. Add code to preprocess the IR to a form
that the pattern matching code can recognize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298400 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 17:09:27 +00:00
Reid Kleckner
6707770d48 Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.

Rename AttributeSetImpl to AttributeListImpl to follow suit.

It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.

Reviewers: sanjoy, javed.absar, chandlerc, pete

Reviewed By: pete

Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits

Differential Revision: https://reviews.llvm.org/D31102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298393 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 16:57:19 +00:00
Vitaly Buka
9fe7c74027 Revert "[Hexagon] Recognize polynomial-modulo loop idiom again"
Fix memory leaks on check-llvm tests detected by Asan.

This reverts commit r298282.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298329 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 00:59:51 +00:00
Krzysztof Parzyszek
fea30225e1 [Hexagon] Recognize polynomial-modulo loop idiom again
Regain the ability to recognize loops calculating polynomial modulo
operation. This ability has been lost due to some changes in the
preceding optimizations. Add code to preprocess the IR to a form
that the pattern matching code can recognize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298282 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-20 18:12:58 +00:00
Nirav Dave
11fdc7845a Make library calls sensitive to regparm module flag (Fixes PR3997).
Reviewers: mkuper, rnk

Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D27050

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298179 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-18 00:44:07 +00:00
Nirav Dave
c78bc912e4 Capitalize ArgListEntry fields. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298178 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-18 00:43:57 +00:00
Colin LeMahieu
731cac0fcb [Hexagon] Updating inline saturate lanes for v62 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297920 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-16 00:35:28 +00:00
Krzysztof Parzyszek
702396c9dc [Hexagon] Fix a condition in HexagonEarlyIfConv.cpp
This fixes llvm.org/PR32265.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297745 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-14 15:21:33 +00:00
Krzysztof Parzyszek
2f2421b3c0 [RDF] Remove the map of reaching defs from copy propagation
Use Liveness::getNearestAliasedRef to find the reaching def instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-10 22:44:24 +00:00
Krzysztof Parzyszek
590c4ddc3f [RDF] Implement Liveness::getNearestAliasedRef(Reg, Inst)
This function will find the closest ref node aliased to Reg that is
in an instruction preceding Inst. This could be used to identify the
hypothetical reaching def of Reg, if Reg was a member of Inst.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297524 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-10 22:42:17 +00:00
Krzysztof Parzyszek
ea69bf92bb [Hexagon] Fixes to the bitsplit generation
- Fix the insertion point, which occasionally could have been incorrect.
- Avoid creating multiple bitsplits with the same operands, if an old one
  could be reused.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297414 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-09 22:02:14 +00:00
Krzysztof Parzyszek
6779169075 [Hexagon] Refactor the DAG preprocessing code, NFC
Extract individual transformations into their own functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297401 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-09 19:14:23 +00:00
Krzysztof Parzyszek
ef87bd9051 [Hexagon] Add -mhvx option to the Hexagon backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297393 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-09 17:05:11 +00:00
Krzysztof Parzyszek
e5673c3859 [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
(op ... (zext i1 c) ...) -> (select c (op ... 1 ...),
                                      (op ... 0 ...))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297391 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-09 16:29:30 +00:00
Krzysztof Parzyszek
b01d205e89 [Hexagon] Use correct offset when extracting from the high word
When extracting a bitfield from the high register in a register pair,
the final offset should be relative to the high register (for 32-bit
extracts).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297288 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-08 15:46:28 +00:00
Krzysztof Parzyszek
872fff124f [Hexagon] Check for presence before looking registers up in bit tracker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297240 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-07 23:12:04 +00:00
Krzysztof Parzyszek
cf301fc559 [Hexagon] Generate bitsplit instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297239 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-07 23:08:35 +00:00
Krzysztof Parzyszek
c1af14f0c1 [Hexagon] Do not insert instructions before PHI nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297141 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-07 14:20:19 +00:00
Krzysztof Parzyszek
aab471c445 [Hexagon] Early-if-convert branches that may exit the loop
Merge the tail block into the loop in cases where the main loop body
exits early, subject to profitability constraints. This will coalesce
the loop body into fewer blocks.

For example:
  loop:                           loop:
    // loop body                      // loop body
    if (...) jump exit      -->       // more body
  more:                               if (...) jump exit
    // more body                      jump loop
    jump loop



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297033 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 17:24:04 +00:00
Krzysztof Parzyszek
c551f30af4 [Hexagon] Mark dead defs as <dead> in expand-condsets
The code in updateDeadFlags removed unnecessary <dead> flags, but there
can be cases where such a flag is not set, and yet a register has become
dead. For example, if a mux with identical inputs is replaced with a COPY,
the predicate register may no longer be used after that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297032 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 17:09:06 +00:00
Krzysztof Parzyszek
f47f1166e4 [Hexagon] Pick a dot-old instruction that matches the architecture
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297031 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 17:03:16 +00:00