Commit Graph

104437 Commits

Author SHA1 Message Date
Alexander Potapenko
22471f5731 Add detection of OS X relocatable SDK to compiler-rt as a lit.util function
Clang's lit cfg already detects the currently selected SDK via
"xcrun --show-sdk-path". The same thing should be done for compiler-rt tests,
to make them work on recent OS X versions. Instead of duplicating the detection
code, this patch extracts the detection function into a lit.util method.

Patch by Kuba Brecka (kuba.brecka@gmail.com),
reviewed at http://reviews.llvm.org/D4072


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210534 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 14:22:00 +00:00
Artyom Skrobov
45a31492d5 Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 13:11:35 +00:00
Artyom Skrobov
8316a97e02 Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 12:47:23 +00:00
Artyom Skrobov
2093e88d67 Anonymous definitions in foreach blocks triggered a 'def already exists'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 12:41:14 +00:00
Tim Northover
e1db6ac10b AArch64: disallow x30 & x29 as the destination for indirect tail calls
As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 10:50:24 +00:00
Tim Northover
efbf7d1ceb Revert "X86: elide comparisons after cmpxchg instructions."
This reverts commit r210523. It was committed prematurely without waiting for
review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 10:50:11 +00:00
Tim Northover
984ee65445 X86: elide comparisons after cmpxchg instructions.
The C++ and C semantics of the compare_and_swap operations actually
require us to return a boolean "success" value. In LLVM terms this
means a second comparison of the output of "cmpxchg" against the input
desired value.

However, x86's "cmpxchg" instruction sets all flags for the comparison
formed, so we can skip any secondary comparison. (N.b. this isn't true
for cmpxchg8b/16b, which only set ZF).

rdar://problem/13201607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 10:49:07 +00:00
Tim Northover
46b3076cd0 AArch64: teach FastISel how to handle offset FrameIndices
Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 09:52:44 +00:00
Tim Northover
292c7c6a48 AArch64: make FastISel memcpy emission more robust.
We were hitting an assert if FastISel couldn't create the load or store we
requested. Currently this happens for large frame-local addresses, though
CodeGen could be improved there.

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 09:52:40 +00:00
Eric Christopher
48a7c150fc Delete X86JITInfo in the subtarget destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 08:03:42 +00:00
Simon Atanasyan
efcef81061 [llvm-readobj][ELF] Factor out the code retrieve ELF symbol information
(section name, section index, full name) into the separate functions.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 05:59:15 +00:00
NAKAMURA Takumi
6e02efd130 SmallVectorTest.cpp: Use LLVM_DELETED_FUNCTION.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 04:06:56 +00:00
Juergen Ributzka
8b9e31c6e2 [ConstantHoisting][X86] Improve the cost model for small constants with large types (i64 and above).
This improves the X86 cost model for small constants with large types. Before
this commit we would even hoist trivial constants such as i96 2.

This is related to <rdar://problem/17070936>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210504 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 00:32:29 +00:00
Reid Kleckner
9de6eef6d0 Reorder Value and User fields to save 8 bytes of padding on 64-bit
Reviewered by: rafael

Differential Revision: http://reviews.llvm.org/D4073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210501 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 23:32:20 +00:00
Richard Trieu
f31ecd3927 Removing an "if (!this)" check from two print methods. The condition will
never be true in a well-defined context.  The checking for null pointers
has been moved into the caller logic so it does not rely on undefined behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:53:16 +00:00
Alp Toker
8aeca44558 Reduce verbiage of lit.local.cfg files
We can just split targets_to_build in one place and make it immutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:42:55 +00:00
David Blaikie
78b4fd3a4b SmallVector: support resize(N) with move-only types
Unfortunately there's no way to elegantly do this with pre-canned
algorithms. Using a generating iterator doesn't work because you default
construct for each element, then move construct into the actual slot
(bad for copy but non-movable types, and a little unneeded overhead even
in the move-only case), so just write it out manually.

This solution isn't exception safe (if one of the element's ctors calls
we don't fall back, destroy the constructed elements, and throw on -
which std::uninitialized_fill does do) but SmallVector (and LLVM) isn't
exception safe anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:26:20 +00:00
Bill Schmidt
8e38e86266 [PPC64LE] Generate correct code for unaligned little-endian vector loads
The code in PPCTargetLowering::PerformDAGCombine() that handles
unaligned Altivec vector loads generates a lvsl followed by a vperm.
As we've seen in numerous other places, the vperm instruction has a
big-endian bias, and this is fixed for little endian by complementing
the permute control vector and swapping the input operands.  In this
case the lvsl is providing the permute control vector.  Rather than
generating an lvsl and a complement operation, it is sufficient to
generate an lvsr instruction instead.  Thus for LE code generation we
will generate an lvsr rather than an lvsl, and swap the other input
arguments on the vperm.

The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test
the code generation for PPC64 and PPC64LE, in addition to the existing
PPC32/G5 testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:00:52 +00:00
Alexey Samsonov
f4a702c079 Generate better location ranges for some register-described variables.
Don't terminate location ranges for register-described variables
at the end of machine basic block if this register is never modified
in the function body, except for the prologue and epilogue. Prologue
location is guessed by FrameSetup flags on MachineInstructions, while
epilogue location is deduced from debug locations of instructions
in the basic blocks ending with return instructions.

This patch is mostly targeted to fix non-trivial debug locations for
variables addressed via stack and frame pointers.

It is not really a generic fix. We can still produce poor debug info
for register-described variables if this register *is* modified somewhere
in the function, but in unrelated places. This might be the case for the debug
info in optimized binaries (e.g. for local variables in inlined functions).
LiveDebugVariables pass in CodeGen attempts to fix this problem by adjusting
DBG_VALUE instructions, but this pass is tied to greedy register allocator,
which is used in optimized builds only. Proper fix would likely involve
generalizing LiveDebugVariables to all register allocators. See more discussion
in http://reviews.llvm.org/D3933 review thread.

I'm proceeding with this patch to fix immediate severe problems and
important cases, e.g. fix completely broken debug info with AddressSanitizer
and fix PR19307 (missing debug info for by-value std::string arguments).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 21:53:47 +00:00
Rafael Espindola
ed7d283ce5 Update langref for unnamed_addr being allowed in aliases.
Thanks to Duncan P. N. Exon Smith and Owen Anderson for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210490 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 21:21:33 +00:00
Saleem Abdulrasool
c90ddb1869 ARM: add VLA extension for WoA Itanium ABI
The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It
has a few divergences, mostly revolving around the use of the Itanium ABI for
C++. VLA support is one of the extensions that are amongst the set of the
extensions.

This adds support for proper VLA emission for this environment. This is
somewhat similar to the handling for __chkstk emission on X86 and the large
stack frame emission for ARM. The invocation style for chkstk is still
controlled via the -mcmodel flag to clang.

Make an explicit note that this is an extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210489 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 20:18:42 +00:00
Matt Arsenault
8a0c2d17f5 Look through addrspacecasts when turning ptr comparisons into
index comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210488 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 19:20:29 +00:00
Stepan Dyatkovskiy
77b0b852fa Added functions cross-reference test.
Originally this similar was initiated by Björn Steinbrink here:
http://reviews.llvm.org/D3437

Bug itself has been fixed by principal changes in MergeFunctions. Though
special checks for functions merging are still actual. And the test has
been accepted with slight modifications.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210486 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 19:03:02 +00:00
Alp Toker
5396370ebb Remove old fenv.h workaround for a historic clang driver bug
Tested and works fine with clang using libstdc++.

All indications are that this was fixed some time ago and isn't a problem with
any clang version we support.

I've added a note in PR6907 which is still open for some reason.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 19:00:52 +00:00
Alp Toker
f4cf404837 Fold FEnv.h into the implementation
Support headers shouldn't use config.h definitions, and they should never be
undefined like this.

ConstantFolding.cpp was the only user of this facility and already includes
config.h for other math features, so it makes sense to move the checks there at
point of use.

(The implicit config.h was also quite dangerous -- removing the FEnv.h include
would have silently disabled math constant folding without causing any tests to
fail. Need to investigate -Wundef once the cleanup is done.)

This eliminates the last config.h include from LLVM headers, paving the way for
more consistent configuration checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210483 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 18:28:53 +00:00
Peter Zotov
7ffad46ea7 [OCaml] Add more Llvm_target tests
Patch by Jacques-Pascal Deplaix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210482 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 18:28:47 +00:00
Peter Zotov
08e709589d [OCaml] Unbreak Llvm_target.TargetMachine.set_verbose_asm
Patch by Jacques-Pascal Deplaix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 17:34:34 +00:00
Eric Christopher
fdea941583 Move all of the x86 subtarget initialized variables down into the x86 subtarget
from the x86 target machine. Should be no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 17:08:19 +00:00
Matt Arsenault
405ed284b7 R600/SI: Rename VOP3 helper class to be more general
It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 17:00:46 +00:00
Andrea Di Biagio
9b6992ddc2 [X86] Add target combine rules for horizontal add/sub.
This patch adds new target specific combine rules to identify horizontal
add/sub idioms from BUILD_VECTOR dag nodes.

This patch also teaches the DAGCombiner how to canonicalize sequences of
insert_vector_elt dag nodes according to the following rule:

  (insert_vector_elt (insert_vector_elt A, I0), I1) ->
    (insert_vecto_elt (insert_vector_elt A, I1), I0)

This new canonicalization rule only triggers if the inner insert_vector
dag node has exactly one use; also, both indices must be known constants,
and I1 < I0.
This last rule made it possible to write a simpler algorithm to identify
horizontal add/sub patterns because now we don't have to worry about the
ordering of insert_vector_elt dag nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:54:41 +00:00
Matt Arsenault
1968da36ed R600/SI: Keep 64-bit not on SALU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:36:31 +00:00
Matt Arsenault
cf7a113d2f R600: Fix selection failure for vector bswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:20:25 +00:00
Bill Schmidt
4cef3fb022 [PPC64LE] Generate correct little-endian code for v16i8 multiply
The existing code in PPCTargetLowering::LowerMUL() for multiplying two
v16i8 values assumes that vector elements are numbered in big-endian
order.  For little-endian targets, the vector element numbering is
reversed, but the vmuleub, vmuloub, and vperm instructions still
assume big-endian numbering.  To account for this, we must adjust the
permute control vector and reverse the order of the input registers on
the vperm instruction.

The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed
on powerpc64 and powerpc64le targets as well as the original powerpc
(32-bit) target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:06:29 +00:00
Evgeniy Stepanov
35d5a437ea Fix test in r210472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210473 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 14:48:53 +00:00
Evgeniy Stepanov
24f5e55fce [msan] Workaround for invalid origins in shufflevector.
Makes origin propagation ignore literal undef operands, and,
in general, any operand we don't have origin for.

https://code.google.com/p/memory-sanitizer/issues/detail?id=56


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 14:29:34 +00:00
NAKAMURA Takumi
5b7ac8ba18 llvm/test/CodeGen/X86/2014-05-29-factorial.ll: Relax an expression to match Win32 x64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 14:20:23 +00:00
Sasa Stankovic
49b83e1e76 [mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
load/store is in branch delay slot.

Differential Revision: http://llvm-reviews.chandlerc.com/D4048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 14:09:28 +00:00
Andrea Di Biagio
592d439efe [X86] Avoid emitting unnecessary test instructions.
This patch teaches the backend how to check for the 'NoSignedWrap' flag on
binary operations to improve the emission of 'test' instructions.

If the result of a binary operation is known not to overflow we know that
resetting the Overflow flag is unnecessary and so we can avoid emitting
the test instruction.

Patch by Marcello Maggioni.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210468 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 12:34:50 +00:00
Andrea Di Biagio
bc72c8f0d8 [DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.
This patch modifies SelectionDAGBuilder to construct SDNodes with associated
NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator
instructions.

Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing
nsw/nuw/exact flags during codegen.

Patch by Marcello Maggioni.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 12:32:53 +00:00
Alexey Volkov
a2bc6951a0 [X86] Use ADD/SUB instead of INC/DEC for Silvermont
According to Intel Software Optimization Manual 
on Silvermont INC or DEC instructions require 
an additional uop to merge the flags.
As a result, a branch instruction depending 
on an INC or a DEC instruction incurs a 1 cycle penalty.

Differential Revision: http://reviews.llvm.org/D3990



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210466 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 11:40:41 +00:00
Artyom Skrobov
a8d18fe946 [AArch64] Missing aliases for CMP/CMN [W]SP with no shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 11:10:14 +00:00
Jeroen Ketema
503447efba [docs] Fix typo, align comments, fix syntax highlighting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 10:12:29 +00:00
Zoran Jovanovic
0c7ac480e2 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 09:49:51 +00:00
Evgeniy Stepanov
503af43f3c Fix line numbers for code inlined from __nodebug__ functions.
Instructions from __nodebug__ functions don't have file:line
information even when inlined into no-nodebug functions. As a result,
intrinsics (SSE and other) from <*intrin.h> clang headers _never_
have file:line information.

With this change, an instruction without !dbg metadata gets one from
the call instruction when inlined.

Fixes PR19001.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 09:09:19 +00:00
Evgeniy Stepanov
544c895d71 [msan] Fix vector pack intrinsic handling.
This fixes a crash on MMX intrinsics, as well as a corner case in handling of
all unsigned pack intrinsics.

PR19953.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210454 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 08:40:16 +00:00
Matt Arsenault
6959336f6e R600: Add more and testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 08:36:53 +00:00
Patrik Hagglund
cbbf570823 Fix gcc warning (enumeral and non-enumeral type in conditional expression)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210450 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 07:35:07 +00:00
Chad Rosier
451cc566c1 [AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 01:54:00 +00:00
Chad Rosier
0607e82c0a [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add.  The shift can be folded into the add.  This only effects codegen
when the constant is 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 01:25:51 +00:00
Jingyue Wu
09d6a9040c [SeparateConstOffsetFromGEP] inbounds zext => sext for better splitting
For each array index that is in the form of zext(a), convert it to sext(a)
if we can prove zext(a) <= max signed value of typeof(a). The conversion
helps to split zext(x + y) into sext(x) + sext(y).

Reviewed in http://reviews.llvm.org/D4060



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210444 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 23:49:34 +00:00