Commit Graph

99452 Commits

Author SHA1 Message Date
Rui Ueyama
64382602e4 80-column.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 22:11:27 +00:00
Rui Ueyama
9106d365f5 llvm-objdump/COFF: Print ordinal base number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 22:02:24 +00:00
Juergen Ributzka
ceaf829339 Add two new calling conventions for runtime calls
This patch adds two new target-independent calling conventions for runtime
calls - PreserveMost and PreserveAll.
The target-specific implementation for X86-64 is defined as following:
  - Arguments are passed as for the default C calling convention
  - The same applies for the return value(s)
  - PreserveMost preserves all GPRs - except R11
  - PreserveAll preserves all GPRs and all XMMs/YMMs - except R11

Reviewed by Lang and Philip

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199508 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 19:47:03 +00:00
Daniel Sanders
41e1c04201 [mips][msa] Correct pattern for LSA
Summary:
$rs and $rt were the wrong way round in the .td and the testcase wasn't
strict enough to detect the mistake.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2554

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 15:40:05 +00:00
Daniel Sanders
61a2eb1df5 [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU
No functional change since the InstrItinData's were duplicated



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:48:06 +00:00
Daniel Sanders
235a81cbbf [mips][sched] Split IIImul and IIImult into subclasses.
IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:32:41 +00:00
Daniel Sanders
8821f3c6b2 [mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO
No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 14:17:34 +00:00
Renato Golin
3e2346341c Add MLA alias for ARMv4 support.
Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199491 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 13:53:08 +00:00
Chandler Carruth
825488c539 [PM] [cleanup] Rename some of the Verifier's members, re-arrange them,
and tweak comments prior to more invasive surgery. Also clean up some
other non-doxygen comments, and run clang-format over the parts that are
going to change dramatically in subsequent commits so that those don't
get cluttered with formatting changes.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199489 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 11:09:34 +00:00
Kostya Serebryany
bd2c711cdd [asan] extend asan-coverage (still experimental).
- add a mode for collecting per-block coverage (-asan-coverage=2).
   So far the implementation is naive (all blocks are instrumented),
   the performance overhead on top of asan could be as high as 30%.
 - Make sure the one-time calls to __sanitizer_cov are moved to function buttom,
   which in turn required to copy the original debug info into the call insn.

Here is the performance data on SPEC 2006
(train data, comparing asan with asan-coverage={0,1,2}):

                             asan+cov0     asan+cov1      diff 0-1    asan+cov2       diff 0-2      diff 1-2
       400.perlbench,        65.60,        65.80,         1.00,        76.20,         1.16,         1.16
           401.bzip2,        65.10,        65.50,         1.01,        75.90,         1.17,         1.16
             403.gcc,         1.64,         1.69,         1.03,         2.04,         1.24,         1.21
             429.mcf,        21.90,        22.60,         1.03,        23.20,         1.06,         1.03
           445.gobmk,       166.00,       169.00,         1.02,       205.00,         1.23,         1.21
           456.hmmer,        88.30,        87.90,         1.00,        91.00,         1.03,         1.04
           458.sjeng,       210.00,       222.00,         1.06,       258.00,         1.23,         1.16
      462.libquantum,         1.73,         1.75,         1.01,         2.11,         1.22,         1.21
         464.h264ref,       147.00,       152.00,         1.03,       160.00,         1.09,         1.05
         471.omnetpp,       115.00,       116.00,         1.01,       140.00,         1.22,         1.21
           473.astar,       133.00,       131.00,         0.98,       142.00,         1.07,         1.08
       483.xalancbmk,       118.00,       120.00,         1.02,       154.00,         1.31,         1.28
            433.milc,        19.80,        20.00,         1.01,        20.10,         1.02,         1.01
            444.namd,        16.20,        16.20,         1.00,        17.60,         1.09,         1.09
          447.dealII,        41.80,        42.20,         1.01,        43.50,         1.04,         1.03
          450.soplex,         7.51,         7.82,         1.04,         8.25,         1.10,         1.05
          453.povray,        14.00,        14.40,         1.03,        15.80,         1.13,         1.10
             470.lbm,        33.30,        34.10,         1.02,        34.10,         1.02,         1.00
         482.sphinx3,        12.40,        12.30,         0.99,        13.00,         1.05,         1.06


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199488 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 11:00:30 +00:00
Chandler Carruth
0c25726596 [PM] Remove the preverifier and directly compute the DominatorTree for
the verifier after ensuring the CFG is at least usefully formed.

This fixes a number of problems:
1) The PreVerifier was missing the controls the Verifier provides over
   *how* an invalid module is handled -- it just aborted the program!
   Now it uses the same logic as the Verifier which is significantly
   more library-friendly.
2) The DominatorTree used previously could have been cached and not
   updated due to bugs in prior passes and we would silently use the
   stale tree. This could cause dominance errors to not be as quickly
   diagnosed.
3) We can now (in the next patch) pull the functionality of the verifier
   apart from the pass infrastructure so that you can verify IR without
   having any form of pass manager. This in turn frees the code to share
   logic between old and new pass manager variants.

Along the way I fixed at least one annoying bug -- the state for
'Broken' wasn't being cleared from run to run causing all functions
visited after the first broken function to be marked as broken
regardless of whether *they* were a problem. Fortunately, I don't really
know much of a way to observe this peculiarity.

In case folks are worried about the runtime cost, its negligible.
I looked at running the entire regression test suite (which should be
a relatively good use of the verifier) before and after but was unable
to even measure the time spent on the verifier and there was no
regresion from before to after. I checked both with debug builds and
optimized builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 10:56:02 +00:00
Kevin Qin
b9536ac581 [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 09:54:30 +00:00
Chandler Carruth
b2671254bd Add the test for libstdc++ versions newer than 4.6 so we don't
accidentally pick that up while using Clang and run into subtle bugs
down the road related to C++11 features not fully implemented in that
version of the standard library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199484 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 09:47:55 +00:00
Craig Topper
3039306b76 Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 08:16:57 +00:00
Craig Topper
5f69be67b5 Add OpSize16 flags to 32-bit CRC32 instructions so they can be encoded correctly in 16-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 08:01:20 +00:00
Craig Topper
50a2b1672d Teach x86 asm parser to handle 'opaque ptr' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:44:10 +00:00
Craig Topper
9d0b786f72 Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:37:39 +00:00
Craig Topper
5d59bb44ee Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:25:39 +00:00
Craig Topper
4b42f26ab5 VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions don't use the size fields it controls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:11:45 +00:00
Craig Topper
ad6662f202 Replace duplicated code with a existing helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199468 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 06:42:38 +00:00
Hao Liu
84887ceca3 [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
Also add copy support for FPR16.
Also add a missing test case file belongs to commit r197361.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 06:23:30 +00:00
Kevin Qin
16511208f2 [AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:52:35 +00:00
Hao Liu
555f57f67b [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:44:46 +00:00
Bob Wilson
008425f5da Fix bad variable syntax in r199413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 00:40:39 +00:00
Rafael Espindola
e82dec5c0f Use LLVM_EXPLICIT instead of a function pointer as bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 23:37:23 +00:00
Reid Kleckner
ad60d3c304 Change inalloca rules to make it only apply to the last parameter
This makes things a lot easier, because we can now talk about the
"argument allocation", which allocates all the memory for the call in
one shot.

The only functional change is to the verifier for a feature that hasn't
shipped yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199434 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 22:59:24 +00:00
Quentin Colombet
9b24eeee01 [opt][PassInfo] Allow opt to run passes that need target machine.
When registering a pass, a pass can now specify a second construct that takes as
argument a pointer to TargetMachine.
The PassInfo class has been updated to reflect that possibility.
If such a constructor exists opt will use it instead of the default constructor
when instantiating the pass.

Since such IR passes are supposed to be rare, no specific support has been
added to this commit to allow an easy registration of such a pass.
In other words, for such pass, the initialization function has to be
hand-written (see CodeGenPrepare for instance).

Now, codegenprepare can be tested using opt:
opt -codegenprepare -mtriple=mytriple input.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199430 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 21:44:34 +00:00
Duncan P. N. Exon Smith
7c41150e85 LTO: document LTO_API_VERSION for each API
Adding a doxygen comment for each bit of API to indicate at which
LTO_API_VERSION each was available, manually gleaned from successive
git-blames.  A few notes:

- LTO_API_VERSION was set to 3 at its introduction.
- I've indicated all the API introduced before LTO_API_VERSION was
  around as available "prior to LTO_API_VERSION=3".
- A number of API changes neglected to bump LTO_API_VERSION.  These I've
  indicated as available at the *next* bump of LTO_API_VERSION.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 21:37:17 +00:00
Owen Anderson
5ee5e0c430 Fix two cases where we could lose fast math flags when optimizing FADD expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 21:26:02 +00:00
Owen Anderson
5d9450f92f Fix an instance where we would drop fast math flags when performing an fdiv to reciprocal multiply transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 21:07:52 +00:00
Owen Anderson
da5e148474 Fix a bug in InstCombine where we failed to preserve fast math flags when optimizing an FMUL expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:59:41 +00:00
Rui Ueyama
4b81ee4d9a Fix style issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:57:55 +00:00
Rui Ueyama
6010e5dfee llvm-objdump/COFF: Print DLL name in the export table header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199422 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:50:34 +00:00
Owen Anderson
a2a8bbb30f Teach InstCombine that (fmul X, -1.0) can be simplified to (fneg X), which LLVM expresses as (fsub -0.0, X).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199420 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:36:42 +00:00
Rui Ueyama
a560d155d9 Use static instead of anonymous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:30:36 +00:00
Rui Ueyama
6846082281 Reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:22:55 +00:00
Rui Ueyama
671a9e2ce0 Use the current local variable naming style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199417 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 20:11:48 +00:00
Bob Wilson
40c7e400fe Pass the --enable-libcpp configure option for cross builds, too.
<rdar://problem/15831288>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199413 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 19:35:01 +00:00
Kevin Enderby
ea32ab98f4 Tweak the MCExternalSymbolizer to print references to C string literals
with raw_ostream's write_escaped() method.

For example darwin's otool(1) program that uses the llvm
disassembler now produces disassembly like this:

leaq	0x7b(%rip), %rdi ## literal pool for: "%f\ntoto\n"

and not print the new lines which messes up the output.

rdar://15145300


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199407 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 18:43:56 +00:00
Ed Maste
22939fa0a4 llvm-symbolizer: make mangled name heuristic apply to all symbols
PR: http://llvm.org/pr18431
Review: http://llvm-reviews.chandlerc.com/D2552


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199404 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 17:25:12 +00:00
Daniel Sanders
fbe67dabad [mips][sched] Removed IIXfer. No instructions use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199403 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 17:23:08 +00:00
Daniel Sanders
89d1caaa1b [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class as their non-microMIPS counterparts.
No functional change since both classes have the same InstrItinData definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199402 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 17:13:57 +00:00
Rafael Espindola
640f8f65a7 Add an emitRawComment function and use it to simplify some uses of EmitRawText.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 16:28:37 +00:00
Daniel Sanders
1a6226f236 [mips][sched] Split IIseb into II_SEB and II_SEH
No functional change since there are no InstrItinData's.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 16:19:38 +00:00
Daniel Sanders
ba8f9dde32 [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI
This is necessary because the classes are shared between all implementations.

No functional change since the InstrItinData's have been duplicated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 15:57:05 +00:00
Amara Emerson
fc17ce612f Move the xscale build attribute test to the proper place and remove the old one.
The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 15:11:54 +00:00
Daniel Sanders
7bc4a7ced6 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:27:20 +00:00
Daniel Sanders
31505363ca [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult.
This matches the itin class used by the non-microMIPS equivalents of these
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199389 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 14:02:48 +00:00
Daniel Sanders
5655b118da [mips] IIImult should have an InstrItinData in the generic scheduler. Used the same one as for IIImul.
Affects:
  DMULT, DMULTu, MADD, MADD_MM, MADDU, MADDU_MM, MSUB, MSUB_MM, MSUBU,
  MSUBU_MM, MULT, MULTu

Does not affect MULT_MM, MULTu_MM since they are currently miscategorised
as IIImul.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 13:45:53 +00:00
Tim Northover
f390c22a93 ReMat: fix overly cavalier attitude to sub-register indices
There are two attempted optimisations in reMaterializeTrivialDef, trying to
avoid promoting the size of a register too much when rematerializing.
Unfortunately, both appear to be flawed. First, we see if the original register
would have worked, but this is inadequate. Consider:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0 = COPY v1:Q1 (v1, v2 are QQ)
    ...
    uses of v2

In this case even though v2 *could* be used directly as the output of
SOMETHING, this would set the wrong bits of the QQ register involved. The
correct rematerialization must be:

    v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ)
    ...
    uses of v2:Q1_Q2

For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then
we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try
to hunt for a class between v1 and v2 that works. Unfortunately, this is also
wrong:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ)
    ...
    uses of v2 as a QQQ

The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current
logic would decide that v2 could be a QQ (no interest is taken in later uses).

This patch, therefore, always accepts the widened register class without trying
to be clever. Generally there is no penalty to this (e.g. in the common GR32 <
GR64 case, expanding the width doesn't matter because it's not like you were
going to do anything else with the high bits of a GR32 register). It can
increase register pressure in cases like the ARM VFP regs though (multiple
non-overlapping but equivalent subregisters). This situation can be
spotted by the fact that both source and destination in the
not-quite-coalesced pair have a sub-register index and
rematerialisation is skipped in that situation.

Unfortunately, no in-tree targets actually expose this as far as I can tell
(there are so few isAsCheapAsAMove instructions for it to trigger on) so I've
been unable to produce a test. It was exposed in our ARM64 SPEC tests though,
and I will be adding a test there that we should be able to contribute
soon(TM).

rdar://problem/15775279

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 12:29:55 +00:00