93389 Commits

Author SHA1 Message Date
Derek Schuff
6b6b112dba [WebAssembly] Add asm.js-style exception handling support
Summary: This patch includes asm.js-style exception handling support for
WebAssembly. The WebAssembly MVP does not have any support for
unwinding or non-local control flow. In order to support C++ exceptions,
emscripten currently uses JavaScript exceptions along with some support
code (written in JavaScript) that is bundled by emscripten with the
generated code.
This scheme lowers exception-related instructions for wasm such that
wasm modules can be compatible with emscripten's existing scheme and
share the support code.

Patch by Heejin Ahn

Differential Revision: https://reviews.llvm.org/D22958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277391 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 21:34:04 +00:00
Zachary Turner
822ef4e420 [msf] Teach LLVM to parse a split Fpm.
The FPM is split at regular intervals across the MSF file, as the MS code
suggests. It turns out that the value of the interval is precisely the
block size. If the block size is 4096, then there are two Fpm pages every
4096 blocks.

So here we teach the PDBFile class to parse a split FPM, and also add more
options when dumping the FPM to display some additional information such
as orphaned pages (pages which the FPM says are allocated, but which
nothing appears to use), use after free pages (pages which the FPM says
are not allocated, but which are referenced by a stream), and multiple use
pages (pages which the FPM says are allocated but are used more than
once).

Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D23022

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277388 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 21:19:45 +00:00
Lang Hames
075c1e2e1a [ExecutionEngine][MCJIT][Orc] Replace RuntimeDyld::SymbolInfo with JITSymbol.
This patch replaces RuntimeDyld::SymbolInfo with JITSymbol: A symbol class
that is capable of lazy materialization (i.e. the symbol definition needn't be
emitted until the address is requested). This can be used to support common
and weak symbols in the JIT (though this is not implemented in this patch).

For consistency, RuntimeDyld::SymbolResolver is renamed to JITSymbolResolver.

For space efficiency a new class, JITEvaluatedSymbol, is introduced that
behaves like the old RuntimeDyld::SymbolInfo - i.e. it is just a pair of an
address and symbol flags. Instances of JITEvaluatedSymbol can be used in
symbol-tables to avoid paying the space cost of the materializer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277386 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:49:11 +00:00
Krzysztof Parzyszek
9296f21a70 [Hexagon] Tidy up some code, NFC: reapply r277372 with a fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277383 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:31:50 +00:00
Xinliang David Li
fa6022726f [Profile] IR profiling minor cleanup /nfc
Differential Revision: http://reviews.llvm.org/D22995



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277379 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:25:06 +00:00
Matthew Simpson
8a44831abe [LV] Move isGatherOrScatterLegal into LoopVectorizationLegality (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277376 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:11:25 +00:00
Matthew Simpson
abaa42dca0 [LV] Use getPointerOperand helper where appropriate (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277375 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:08:09 +00:00
Krzysztof Parzyszek
71a7b1e6dc Revert r277372, it is causing buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277374 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 20:00:33 +00:00
Krzysztof Parzyszek
d7943136ad [Hexagon] Tidy up some code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277372 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 19:46:21 +00:00
Michael Kuperstein
8be735fdf7 [DAGCombine] Make sext(setcc) combine respect getBooleanContents
We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)"
Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value
of T is 1 or -1, depending on the type of the setcc, and getBooleanContents()
for the type if it is not i1.

This fixes PR28504.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277371 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 19:39:49 +00:00
Ron Lieberman
16082a39ea [Hexagon] Generate vector printing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277370 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 19:36:39 +00:00
George Burgess IV
4df351da7d [CFLAA] Remove modref queries from CFLAA.
As it turns out, modref queries are broken with CFLAA. Specifically,
the data source we were using for determining modref behaviors
explicitly ignores operations on non-pointer values. So, it wouldn't
note e.g. storing an i32 to an i32* (or loading an i64 from an i64*).
It also ignores external function calls, rather than acting
conservatively for them.

(N.B. These operations, where necessary, *are* tracked by CFLAA; we just
use a different mechanism to do so. Said mechanism is relatively
imprecise, so it's unlikely that we can provide reasonably good modref
answers with it as implemented.)

Patch by Jia Chen.

Differential Revision: https://reviews.llvm.org/D22978


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277366 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 18:47:28 +00:00
Evandro Menezes
665f6036f6 [AArch64] Add support for Samsung Exynos M2 (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277364 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 18:39:45 +00:00
George Burgess IV
e0188664fb [CFLAA] Make CFLAnders more conservative with new Values.
Currently, CFLAnders assumes that values it hasn't seen don't alias
anything. This patch fixes that. Given that the only way for this to
happen is to query AA, rely on specific transformations happening, then
query AA again (looking for a specific set of queries), lit testing is a
bit difficult. If someone really wants a test, I'm happy to add one.

Patch by Jia Chen.

Differential Revision: https://reviews.llvm.org/D22981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277362 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 18:27:33 +00:00
David Majnemer
6687e3a1ed [Verifier] Resume instructions can only be in functions w/ a personality
This fixes PR28799.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277360 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 18:06:34 +00:00
Krzysztof Parzyszek
c54b1ec0f8 Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC
There were a few cases introduced with the modulo scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277358 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 17:55:48 +00:00
Krzysztof Parzyszek
c765d85307 [Hexagon] Check for offset overflow when reserving scavenging slots
Scavenging slots were only reserved when pseudo-instruction expansion in
frame lowering created new virtual registers. It is possible to still
need a scavenging slot even if no virtual registers were created, in cases
where the stack is large enough to overflow instruction offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277355 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 17:15:30 +00:00
Daniel Sanders
a738e21392 [mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.
Summary:
Allocating an AFGR64 shadows two GPR32's instead of just one.

This fixes an LNT regression detected by our internal buildbots.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D23012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277348 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 15:32:51 +00:00
Valery Pykhtin
1704eb6864 [AMDGPU] refactor DS instruction definitions. NFC.
Differential revision: https://reviews.llvm.org/D22522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277344 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 14:21:30 +00:00
Simon Pilgrim
f6cf26bc83 [X86] Use implicit masking of SHLD/SHRD shift double instructions
Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277341 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 12:11:43 +00:00
Simon Pilgrim
25fd1498fa Fixed MSVC out of range shift warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 09:40:38 +00:00
James Molloy
a77b56f254 [SimplifyCFG] Fix nasty RAUW bug from r277325
Using RAUW was wrong here; if we have a switch transform such as:
  18 -> 6 then
  6 -> 0

If we use RAUW, while performing the second transform the  *transformed* 6
from the first will be also replaced, so we end up with:
  18 -> 0
  6 -> 0

Found by clang stage2 bootstrap; testcase added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277332 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 09:34:48 +00:00
Diana Picus
deeb6ba1ab [AArch64] Return the correct size for TLSDESC_CALLSEQ
The branch relaxation pass is computing the wrong offsets because it assumes
TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction
sequence taking up 16 bytes. This can become a problem in huge files with lots
of TLS accesses, as it may slowly move branch targets out of the range computed
by the branch relaxation pass.

Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234

Differential Revision: https://reviews.llvm.org/D22870

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277331 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 08:38:49 +00:00
Craig Topper
6c739fb541 [AVX-512] Fix duplicate column in AVX512 execution dependency table that was preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277327 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 07:55:33 +00:00
James Molloy
16e549f1c0 [SimplifyCFG] Range reduce switches
If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example:

    switch (i) {
    case 5: ...
    case 9: ...
    case 13: ...
    case 17: ...
    }

can become:

    if ( (i - 5) % 4 ) goto default;
    switch ((i - 5) / 4) {
    case 0: ...
    case 1: ...
    case 2: ...
    case 3: ...
    }

or even better:

   switch ( ROTR(i - 5, 2) {
   case 0: ...
   case 1: ...
   case 2: ...
   case 3: ...
   }

The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277325 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 07:45:11 +00:00
Hrvoje Varga
5c02c44a28 [mips] Clang generates unaligned offset for MSA instruction st.d
Differential Revision: https://reviews.llvm.org/D19475



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277323 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 06:46:20 +00:00
Diana Picus
5bfb1b8c4e [AArch64] Register passes so they can be run by llc
Initialize all AArch64-specific passes in the TargetMachine so they can be run
by llc. This can lead to conflicts in opt with some command line options that
share the same name as the pass, so I took this opportunity to do some cleanups:
* rename all relevant command line options from "aarch64-blah" to
  "aarch64-enable-blah" and update the tests accordingly
* run clang-format on their declarations
* move all these declarations to a common place (the TargetMachine) as opposed
  to having them scattered around (AArch64BranchRelaxation and
  AArch64AddressTypePromotion were the only offenders)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277322 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 05:56:57 +00:00
Craig Topper
87efa54747 [AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported.
Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277321 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 05:31:50 +00:00
Craig Topper
e0f68ac00d [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277319 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 04:29:13 +00:00
Craig Topper
8b3212e29f [X86] Move mask register handling into the main switch of getLoadStoreRegOpcode. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277318 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 04:29:11 +00:00
Sean Silva
04c0c682a2 Revert r277313 and r277314.
They seem to trigger an LSan failure:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio

Revert "Add the tests for r277313"

This reverts commit r277314.

Revert "CodeExtractor : Add ability to preserve profile data."

This reverts commit r277313.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277317 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 04:16:09 +00:00
Sean Silva
980a4b4d40 Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent function.
When extracting a set of blocks make sure to inherit all of the target
dependent attributes to make sure that the function will be valid for
lowering. One example is the "target-features" attribute for x86, if the
extracted region has functionality that relies on a specific feature it
will fail to be lowered.
This also allows for extracted functions to be valid for inlining, at
least back into the parent function, as the target attributes are tested
when inlining for compatibility.

Patch by River Riddle!

Differential Revision: https://reviews.llvm.org/D22713

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277315 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 03:15:32 +00:00
Sean Silva
0f7cbe185c CodeExtractor : Add ability to preserve profile data.
Added ability to estimate the entry count of the extracted function and
the branch probabilities of the exit branches.

Patch by River Riddle!

Differential Revision: https://reviews.llvm.org/D22744

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277313 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 02:59:26 +00:00
Daniel Berlin
cdbca76b08 Fix the MemorySSA updating API to enable people to create memory accesses before removing old ones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277309 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 21:08:20 +00:00
Craig Topper
d29f9a0db2 [X86] Simplify code for determing GR or FR reg classes by querying for super classes instead of manually listing individual classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277306 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:20:08 +00:00
Craig Topper
4022678c7f [AVX512] Always use EVEX encodings for 128/256-bit move instructions in getLoadStoreRegOpcode if VLX is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277305 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:20:05 +00:00
Craig Topper
f015e11376 [AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277304 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:20:01 +00:00
Craig Topper
64e28736d1 [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main switch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:19:55 +00:00
Craig Topper
b08f1f36a7 [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277302 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:19:53 +00:00
Craig Topper
7882ecba2d [AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 20:19:50 +00:00
Simon Pilgrim
bc139df3fe [X86] Improve 64-bit shifts on 32-bit targets (PR14593)
As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

Differential Revision: https://reviews.llvm.org/D23000

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277299 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 19:50:45 +00:00
David Majnemer
081d3f18a8 [COFF] Expose iterators for ImportAddressTableRVA
Patch by Bandzi Michal!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277298 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 19:40:02 +00:00
David Majnemer
e2fac43a5a [COFF] Remove a duplicate import_directory_table_entry definition
We had import_directory_table_entry and
coff_import_directory_table_entry, remove one.  Also, factor out the
logic which determins if a descriptor is a terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277296 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 19:25:21 +00:00
Craig Topper
ed98854bb4 [AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD unless DQI instructions are supported. Same for ANDN, OR, and XOR.
Thanks to Igor Breger for pointing out my mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277292 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 17:15:07 +00:00
Amjad Aboud
67b0099873 Fixed "copy-paste" mistake from revision 255245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277290 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 14:41:50 +00:00
Elena Demikhovsky
d71fdd1359 AVX-512: Removed AssertZext node before TRUNCATE
Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1".

Differential Revision: https://reviews.llvm.org/D22850



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277289 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-31 06:48:01 +00:00
Davide Italiano
48f202f23f [HexagonConstPropagation] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277285 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-30 22:07:21 +00:00
Davide Italiano
b9766783ad [HexagonBitSimplify] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277284 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-30 22:07:18 +00:00
Davide Italiano
f796352534 [ARMConstantIslandPass] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277283 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-30 22:07:15 +00:00
Simon Pilgrim
3575d762d7 Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277280 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-30 20:53:21 +00:00