Craig Topper
930a1ebd92
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
Craig Topper
28a713b20a
Add vmfunc instruction to X86 assembler and disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
Craig Topper
9e3d0b3351
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
Eli Bendersky
0f0c411079
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
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Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 06:28:33 +00:00
James Molloy
3015dfb7d7
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
Craig Topper
06f554d06a
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e
Add FMA4 instructions to disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 05:20:36 +00:00
Craig Topper
1604ccfc01
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:43:40 +00:00
Craig Topper
19f18be449
Expose FMA3 instructions to the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:03:14 +00:00
Jim Grosbach
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
Wesley Peck
4c729f1152
Add several new instructions supported by the latest MicroBlaze.
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These instructions are not generated by the backend yet, this will come in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27 05:16:58 +00:00
Owen Anderson
b589be9334
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:55:00 +00:00
Jim Grosbach
ffc658b056
ARM VLDR/VSTR instructions don't need a size suffix.
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Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
Benjamin Kramer
70be28a5ad
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:00:59 +00:00
Owen Anderson
81550dc0a8
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 18:03:14 +00:00
Owen Anderson
60cb643f75
Fix disassembly of some VST1 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01 22:18:13 +00:00
Owen Anderson
fb6ab2b30e
More not-crashing NEON disassembly updates for the vld refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 17:17:32 +00:00
Owen Anderson
017f87cf68
Fix illegal disassembly testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143231 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 21:45:09 +00:00
Owen Anderson
cb9fed6655
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 18:02:13 +00:00
Owen Anderson
03e03b0984
Add testcase for r143162.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 22:54:14 +00:00
Owen Anderson
a7c98f58ea
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 18:04:29 +00:00
Craig Topper
5679ec3b52
Add X86 SARX, SHRX, and SHLX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 22:18:24 +00:00
Craig Topper
75485d6746
Add X86 RORX instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 07:34:00 +00:00
Craig Topper
4fea38f773
Add X86 MULX instruction for disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 00:33:32 +00:00
Owen Anderson
cd20c58e98
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 22:23:58 +00:00
Owen Anderson
fe0748d696
Fix decoding tests for fixed MSR encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 22:01:48 +00:00
Craig Topper
717cdb0df8
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Craig Topper
ee62e4f6d1
Add X86 PEXTR and PDEP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Craig Topper
b53fa8bf19
Add X86 BZHI instruction as well as BMI2 feature detection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
Craig Topper
17730847d5
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
Craig Topper
566f233ba6
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
Craig Topper
54a11176f6
Add X86 ANDN instruction. Including instruction selection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
Craig Topper
909652f687
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
Bill Wendling
1203fe7fc8
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:48:07 +00:00
Craig Topper
8ab1d1e900
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:09:14 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
fbab2206cf
Update test for r141704.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:18:50 +00:00
Craig Topper
37f2167f15
Add X86 LZCNT instruction. Including instruction selection support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:44:02 +00:00
Craig Topper
29480fd798
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd
Insert dummy ED table entries for pseudo-instructions.
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The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:30:16 +00:00
Craig Topper
da394041c4
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
Craig Topper
75fe5f3bab
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
Craig Topper
6744a17dcf
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
Craig Topper
581fe82c84
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:28:23 +00:00
Craig Topper
04c5be9f12
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
Craig Topper
04b0b34b3a
Test updates that were supposed to go with r140993.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:53:59 +00:00
Craig Topper
82f131a017
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 16:56:09 +00:00
Craig Topper
846a2dcada
Fix disassembling of INVEPT and INVVPID to take operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
James Molloy
acad68da50
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Owen Anderson
21733e8f80
Fix an incorrect decoder test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:08:34 +00:00
Craig Topper
100d86ada5
Fix VEX decoding in i386 mode. Fixes PR11008.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
Owen Anderson
1f24002ed4
Fix incorrect disassembly test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:05:54 +00:00
Owen Anderson
0781c1f700
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:07:25 +00:00
Craig Topper
4da632e6e0
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 06:57:25 +00:00
Craig Topper
adf01b3f18
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 07:01:50 +00:00
Owen Anderson
e136872970
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:44:46 +00:00
Owen Anderson
9d1a3dea15
Port over more Thumb2 encoding tests to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 17:44:48 +00:00
Owen Anderson
ecd1c55790
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:07:10 +00:00
Owen Anderson
be290af0d8
Add a testcase for another corner-case decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:15:29 +00:00
Owen Anderson
89db0f690c
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:29:48 +00:00
Owen Anderson
8a28bdcbcc
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:17:02 +00:00
Owen Anderson
705b48ff86
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:08:33 +00:00
Owen Anderson
a610d619ce
Port over more Thumb2 assembly tests to disassembly tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 17:56:04 +00:00
Owen Anderson
1070278efa
Port over more Thumb2 assembly tests to disassembly tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 17:22:48 +00:00
Craig Topper
a08e255e1e
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 06:41:26 +00:00
Craig Topper
3bb43a829e
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 05:55:28 +00:00
Craig Topper
6a9795a457
Add test case for PR10851.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 04:36:54 +00:00
Owen Anderson
13b8d1e396
Make use of Eli's FileCheck sorcery to improve this test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 21:37:50 +00:00
Owen Anderson
7782a58b87
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 20:46:26 +00:00
Craig Topper
58bbb81764
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
Owen Anderson
cd00dc6852
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:28:46 +00:00
Owen Anderson
a3157b4026
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:56:30 +00:00
Craig Topper
136046c9a2
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
Craig Topper
038197988b
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
Craig Topper
842f58f9be
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 20:23:20 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Craig Topper
d3be6ecafe
Add disassembler test for Intel syntax. Tests r139353.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 06:35:44 +00:00
Owen Anderson
d2fc31b3f7
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Owen Anderson
8a83f71301
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:10:42 +00:00
James Molloy
a5d5856854
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
Jim Grosbach
90502888f2
Update test for 139243
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:40:06 +00:00
Owen Anderson
6de3c6f1a9
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:55:19 +00:00
Owen Anderson
39950595f7
Port more encoding tests over to Thumb2 decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:26:34 +00:00
Kevin Enderby
d5705fe50d
Change X86 disassembly to print immediates values as signed by default. Special
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case those instructions that the immediate is not sign-extend. radr://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:01:23 +00:00
Kevin Enderby
98f213cd60
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:03:03 +00:00
Craig Topper
5ffedb9352
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 04:17:54 +00:00
Owen Anderson
eaca928a37
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:58:27 +00:00
Owen Anderson
3318d9c27d
Port Thumb2 assembler tests over to disassembler tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 20:03:11 +00:00
Craig Topper
3daa5c29d4
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:09:35 +00:00
Kevin Enderby
fff64ca9cf
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 22:06:28 +00:00
Owen Anderson
f1eab597b2
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Owen Anderson
9ab0f25fc1
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 20:43:14 +00:00
Owen Anderson
96425c8464
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:09:22 +00:00
Owen Anderson
5a18f20dab
Add a testcase for r138625.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 06:45:08 +00:00
Craig Topper
8fd13b6de5
Fix disassembling of VCVTSD2SI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
Owen Anderson
99906830e8
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 18:30:18 +00:00
Craig Topper
113061d39b
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 07:42:00 +00:00
Craig Topper
ea03659d23
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
Owen Anderson
ddaa513fce
Port over more encoding tests to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:08:34 +00:00
Owen Anderson
82265a2c72
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:51:38 +00:00
Owen Anderson
e732cb0043
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:37:32 +00:00
Owen Anderson
b4ff9698bd
Port more assemble tests over to disassembly tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:26:35 +00:00
Owen Anderson
c6788c83b4
t2SMLAD is a four-register instruction, not a three-register one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe
Correct operand naming of t2USAT16 to allow proper decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:27:47 +00:00
Owen Anderson
2379fc235f
Match operand naming to allow correct decoding of t2LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:22:05 +00:00
Owen Anderson
2c9f83533b
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:10:16 +00:00
Owen Anderson
838130e3b9
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 21:34:00 +00:00
Owen Anderson
357ec6850b
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:27:12 +00:00
Owen Anderson
2cbf210450
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:22:06 +00:00
Owen Anderson
88b7ccc7f0
Port another swathe of Thumb1 encoding tests over to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:05:49 +00:00
Owen Anderson
b113ec55e8
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 17:56:58 +00:00
Craig Topper
e004d941ec
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 05:28:50 +00:00
Owen Anderson
78affc9ea1
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:31:17 +00:00
Owen Anderson
14090bf263
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:11:02 +00:00
Jim Grosbach
93b3eff623
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 21:50:53 +00:00
Owen Anderson
847a7ad800
More Thumb1 decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 20:05:06 +00:00
James Molloy
dbe46744c5
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 18:03:02 +00:00
Owen Anderson
7cf6d7a083
Port over BL/BLX to disassembly tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 17:43:52 +00:00
Owen Anderson
3230e9537d
Port new Thumb1 encoding tests over to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 23:37:33 +00:00
Owen Anderson
4c81cf5dfc
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 18:21:36 +00:00
Owen Anderson
83e3f67fb6
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 17:44:15 +00:00
Owen Anderson
a9c989d55a
Add a test file for Thumb2 NEON.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:42:20 +00:00
Owen Anderson
c4bda5633a
Add some more comprehensive VFP decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 21:29:01 +00:00
Owen Anderson
c537f3be0c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:51:32 +00:00
Owen Anderson
95d01b8898
Add a test for Thumb1 LDRSH decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:15:43 +00:00
Owen Anderson
bd37b721c8
Add testcase for STRH. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:12:03 +00:00
Owen Anderson
5df7ef6cdb
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 18:44:44 +00:00
Owen Anderson
0d09499cf3
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:36:11 +00:00
Owen Anderson
a211c2c7e9
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 19:42:45 +00:00
Owen Anderson
508e1d3db5
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:47:56 +00:00
Owen Anderson
9fe72bcd37
Improve operand validation for Thumb2 addressing modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:40:40 +00:00
Owen Anderson
26d2f0ac91
Continue to tighten decoding by performing more operand validation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Owen Anderson
71156a6e00
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:24:51 +00:00
Owen Anderson
8533ebad6f
Add initial support for decoding NEON instructions in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 19:01:10 +00:00
Owen Anderson
33e57515b1
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:03:03 +00:00
Owen Anderson
de317f40f7
Tighten operand checking of register-shifted-register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:33:27 +00:00