In the MS ABI, the frontend is supposed to MD5 such pathologically long
names. LLVM should still defend itself from long names, though.
Fixes part of PR29098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284136 91177308-0d34-0410-b5e6-96231b3b80d8
We don't need to return a MachineInstr* from these stack probe insertion
calls anyway. If we ever need to add it back, we can return an iterator
instead.
Based on a patch by David Kreitzer
This bug is a consequence of
r279314 | dexonsmith | 2016-08-19 13:40:12 -0700 (Fri, 19 Aug 2016) | 110 lines
We hit the "Assertion `!NodePtr->isKnownSentinel()' failed" assertion,
but only when inserting a stack probe call at the end of an MBB, which
isn't necessarily a common situation.
Differential Revision: https://reviews.llvm.org/D25566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284130 91177308-0d34-0410-b5e6-96231b3b80d8
This patch assigns cost of the scaling used in addressing.
On many ARM cores, a negated register offset takes longer than a
non-negated register offset, in a register-offset addressing mode.
For instance:
LDR R0, [R1, R2 LSL #2]
LDR R0, [R1, -R2 LSL #2]
Above, (1) takes less cycles than (2).
By assigning appropriate scaling factor cost, we enable the LLVM
to make the right trade-offs in the optimization and code-selection phase.
Differential Revision: http://reviews.llvm.org/D24857
Reviewers: jmolloy, rengolin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284127 91177308-0d34-0410-b5e6-96231b3b80d8
This patch ensures that we scale the estimated cost of predicated stores by
block probability. This is a follow-on patch for r284123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284126 91177308-0d34-0410-b5e6-96231b3b80d8
This patch modifies the cost calculation of predicated instructions (div and
rem) to avoid the accumulation of rounding errors due to multiple truncating
integer divisions. The calculation for predicated stores will be addressed in a
follow-on patch since we currently don't scale the cost of predicated stores by
block probability.
Differential Revision: https://reviews.llvm.org/D25333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284123 91177308-0d34-0410-b5e6-96231b3b80d8
Because everything live is spilled at the end of a
block by fast regalloc, assume this will happen and
avoid the copies of the resource descriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284119 91177308-0d34-0410-b5e6-96231b3b80d8
These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.
Reviewers: vkalintiris
Differential Review: https://reviews.llvm.org/D24291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284115 91177308-0d34-0410-b5e6-96231b3b80d8
The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call.
This calling convention ensures that as many values as possible are passed or returned in registers.
This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86.
Differential Revision: http://reviews.llvm.org/D25022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284108 91177308-0d34-0410-b5e6-96231b3b80d8
We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom.
We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284102 91177308-0d34-0410-b5e6-96231b3b80d8
As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make
sure fences are properly handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284099 91177308-0d34-0410-b5e6-96231b3b80d8
This allows RegBankSelect in greedy mode to get rid some of the cross
register bank copies when loads are involved in the chain of
computation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284097 91177308-0d34-0410-b5e6-96231b3b80d8
- Use storage class C_STAT for 'PrivateLinkage' The storage class for
PrivateLinkage should equal to the Internal Linkage.
- Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes
x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix
"L" may conflict to the normal symbol name starting with 'L'.
Based on a patch by Han Sangjin! Manually updated test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284096 91177308-0d34-0410-b5e6-96231b3b80d8
Thanks to this patch, RegBankSelect is able to get rid of some register
bank copies as demonstrated in the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284094 91177308-0d34-0410-b5e6-96231b3b80d8
This CL didn't actually address the test case in PR30499, and clang
still crashes.
Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC"
Reverts r283965 and r283967.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284093 91177308-0d34-0410-b5e6-96231b3b80d8
Basically any vector types that fits in a 32-bit register is also valid
as far as copies are concerned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284089 91177308-0d34-0410-b5e6-96231b3b80d8
This document describes the proposal to move to GitHub, and
compare the two proposals through various workflow examples,
presenting the current set of commands following by the ones
involved in each of the two proposals.
It is intended to supersede the previous "submodule proposal"
document entirely, and drive the discussion at the BoF during
the next Dev Meeting.
Differential Revision: https://reviews.llvm.org/D24167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284077 91177308-0d34-0410-b5e6-96231b3b80d8
