144292 Commits

Author SHA1 Message Date
Taewook Oh
73b0db7269 Do not propagate DebugLoc across basic blocks
Summary:
DebugLoc shouldn't be propagated across basic blocks to prevent incorrect stepping and imprecise sample profile result. rL288903 addressed the wrong DebugLoc propagation issue by limiting the copy of DebugLoc when GVN removes a fully redundant load that is dominated by some other load. However, DebugLoc is still incorrectly propagated in the following example:


```
1:  extern int g;
2: 
3:  void foo(int x, int y, int z) {
4:    if (x)
5:      g = 0;
6:    else
7:      g = 1;
8:
9:    int i = 0;
10:   for ( ; i < y ; i++)
11:     if (i > z)
12:       g++;
13: }

```
Below is LLVM IR representation of the program before GVN:


```
@g = external local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
define void @foo(i32 %x, i32 %y, i32 %z) local_unnamed_addr #0 !dbg !4 {
entry:
  %not.tobool = icmp eq i32 %x, 0, !dbg !8
  %.sink = zext i1 %not.tobool to i32, !dbg !8
  store i32 %.sink, i32* @g, align 4, !tbaa !9
  %cmp8 = icmp sgt i32 %y, 0, !dbg !13
  br i1 %cmp8, label %for.body.preheader, label %for.end, !dbg !17

for.body.preheader:                               ; preds = %entry
  br label %for.body, !dbg !19

for.body:                                         ; preds = %for.body.preheader, %for.inc
  %i.09 = phi i32 [ %inc4, %for.inc ], [ 0, %for.body.preheader ]
  %cmp1 = icmp sgt i32 %i.09, %z, !dbg !19
  br i1 %cmp1, label %if.then2, label %for.inc, !dbg !21

if.then2:                                         ; preds = %for.body
  %0 = load i32, i32* @g, align 4, !dbg !22, !tbaa !9
  %inc = add nsw i32 %0, 1, !dbg !22
  store i32 %inc, i32* @g, align 4, !dbg !22, !tbaa !9
  br label %for.inc, !dbg !23

for.inc:                                          ; preds = %for.body, %if.then2
  %inc4 = add nuw nsw i32 %i.09, 1, !dbg !24
  %exitcond = icmp ne i32 %inc4, %y, !dbg !13
  br i1 %exitcond, label %for.body, label %for.end.loopexit, !dbg !17

for.end.loopexit:                                 ; preds = %for.inc
  br label %for.end, !dbg !26

for.end:                                          ; preds = %for.end.loopexit, %entry
  ret void, !dbg !26
}

```
where 


```
!21 = !DILocation(line: 11, column: 9, scope: !15)
!22 = !DILocation(line: 12, column: 8, scope: !20)
!23 = !DILocation(line: 12, column: 7, scope: !20)
!24 = !DILocation(line: 10, column: 20, scope: !25)
```

And below is after GVN:


```
@g = external local_unnamed_addr global i32, align 4

define void @foo(i32 %x, i32 %y, i32 %z) local_unnamed_addr !dbg !4 {
entry:
  %not.tobool = icmp eq i32 %x, 0, !dbg !8
  %.sink = zext i1 %not.tobool to i32, !dbg !8
  store i32 %.sink, i32* @g, align 4, !tbaa !9
  %cmp8 = icmp sgt i32 %y, 0, !dbg !13
  br i1 %cmp8, label %for.body.preheader, label %for.end, !dbg !17

for.body.preheader:                               ; preds = %entry
  br label %for.body, !dbg !19

for.body:                                         ; preds = %for.inc, %for.body.preheader
  %0 = phi i32 [ %1, %for.inc ], [ %.sink, %for.body.preheader ], !dbg !21
  %i.09 = phi i32 [ %inc4, %for.inc ], [ 0, %for.body.preheader ]
  %cmp1 = icmp sgt i32 %i.09, %z, !dbg !19
  br i1 %cmp1, label %if.then2, label %for.inc, !dbg !22

if.then2:                                         ; preds = %for.body
  %inc = add nsw i32 %0, 1, !dbg !21
  store i32 %inc, i32* @g, align 4, !dbg !21, !tbaa !9
  br label %for.inc, !dbg !23

for.inc:                                          ; preds = %if.then2, %for.body
  %1 = phi i32 [ %inc, %if.then2 ], [ %0, %for.body ]
  %inc4 = add nuw nsw i32 %i.09, 1, !dbg !24
  %exitcond = icmp ne i32 %inc4, %y, !dbg !13
  br i1 %exitcond, label %for.body, label %for.end.loopexit, !dbg !17

for.end.loopexit:                                 ; preds = %for.inc
  br label %for.end, !dbg !26

for.end:                                          ; preds = %for.end.loopexit, %entry
  ret void, !dbg !26
}

```
As you see, GVN removes the load in if.then2 block and creates a phi instruction in for.body for it. The problem is that DebugLoc of remove load instruction is propagated to the newly created phi instruction, which is wrong. rL288903 cannot handle this case because ValuesPerBlock.size() is not 1 in this example when the load is removed.

Reviewers: aprantl, andreadb, wolfgangp

Reviewed By: andreadb

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D29254

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293688 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 20:57:13 +00:00
Matthew Simpson
91af052212 Fix VectorUtils include guard name (NFC)
VectorUtils was moved to Analysis from Transforms/Utils, but some comments and
the include guard name still reflect its old location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293684 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 20:29:10 +00:00
Tim Northover
3b21070320 GlobalISel: the translation of an invoke must branch to the good block.
Otherwise bad things happen if the basic block order isn't trivial after an
invoke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293679 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 20:12:18 +00:00
Matthias Braun
becaf19d2d InterleaveAccessPass: Avoid constructing invalid shuffle masks
Fix a bug where we would construct shufflevector instructions addressing
invalid elements.

Differential Revision: https://reviews.llvm.org/D29313

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293673 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:37:53 +00:00
Tim Northover
a90703d224 GlobalISel: merge invoke and call translation paths.
Well, sort of. But the lower-level code that invoke used to be using completely
botched the handling of varargs functions, which hopefully won't be possible if
they're using the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293670 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:36:11 +00:00
Peter Collingbourne
043d1a96c9 MC: Introduce the ABS8 symbol modifier.
@ABS8 can be applied to symbols which appear as immediate operands to
instructions that have a 8-bit immediate form for that operand. It causes
the assembler to use the 8-bit form and an 8-bit relocation (e.g. R_386_8
or R_X86_64_8) for the symbol.

Differential Revision: https://reviews.llvm.org/D28688

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293667 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:28:44 +00:00
Simon Pilgrim
44cd8ce6e5 [X86][XOP] Add test showing failure to combine build vector to vpermil2ps shuffle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293663 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:10:34 +00:00
Kevin Enderby
536a298311 Fix a bug in llvm-obdump(1) with the -macho flag disassembling an object
without symbols that makes calls through a symbol stub which were not
correctly being annotated with “## symbol stub for: _foo”.

Just adds the same parameters for getting the annotations from
DisAsm->getInstruction() and passing them to IP->printInst() from the
code above when boolean variable symbolTableWorked was true.

rdar://29791952


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293662 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:09:10 +00:00
Davide Italiano
ee994236c6 [Instcombine] Combine consecutive identical fences
Differential Revision:  https://reviews.llvm.org/D29314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293661 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 18:09:05 +00:00
Arnold Schwaighofer
b77943578a Don't combine stores to a swifterror pointer operand to a different type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293658 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:53:49 +00:00
Dehao Chen
500e57803c Explicitly promote indirect calls before sample profile annotation.
Summary: In iterative sample pgo where profile is collected from PGOed binary, we may see indirect call targets promoted and inlined in the profile. Before profile annotation, we need to make this happen in order to annotate correctly on IR. This patch explicitly promotes these indirect calls and inlines them before profile annotation.

Reviewers: xur, davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29040

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293657 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:49:37 +00:00
Sanjay Patel
076c840012 [InstCombine] add test for possible zext-phi transform; NFC
The datalayout doesn't include i1, so we don't do a potential shrink and sink transform.

Example based on discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/109631.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293656 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:43:00 +00:00
Matt Arsenault
90657acceb AMDGPU: Use source mods with fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293654 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:28:40 +00:00
Sanjay Patel
963ec7630c fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293652 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:25:42 +00:00
Nirav Dave
53d52e9e2b [X86] Implement -mfentry
Summary: Insert calls to __fentry__ at function entry.

Reviewers: hfinkel, craig.topper

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D28000

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293648 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 17:00:27 +00:00
David Bozier
34d37a4707 Add support for demangling C++11 thread_local variables.
In clang, the grammar for mangling for these names are "<special-name> ::= TW <object name>" for wrapper variables or "<special-name> ::= TH <object name>" for initialization variables.

Initial change was made in libccxxabi r293638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293643 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 15:56:36 +00:00
Artem Tamazov
537d96c366 [AMDGPU][mc][tests][NFC] Revert coverage/smoke Gfx7 asm test
Reason: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/2916/testReport/junit/LLVM/MC_AMDGPU/gfx7_asm_all_s/

This seems to reveal an AMDGPU/mc issue which needs to be triaged & fixed prior re-committing the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293642 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 15:50:11 +00:00
Tom Stellard
d925fa77b2 AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds
Summary:
For some reason instructions are being inserted in the wrong order with some
builds.  I'm not sure why this is happening.

Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D29325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293639 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 15:24:11 +00:00
Simon Pilgrim
2563d410c9 [X86][SSE] Add support for combining PINSRB into a target shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:59:44 +00:00
Nicolai Haehnle
ab43652716 [DAGCombine] require UnsafeFPMath for re-association of addition
Summary:
The affected transforms all implicitly use associativity of addition,
for which we usually require unsafe math to be enabled.

The "Aggressive" flag is only meant to convey information about the
performance of the fused ops relative to a fmul+fadd sequence.

Fixes Bug 31626.

Reviewers: spatel, hfinkel, mehdi_amini, arsenm, tstellarAMD

Subscribers: jholewinski, nemanjai, wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D28675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293635 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:35:37 +00:00
Sam Parker
d9605fec4b [ARM] Avoid using ARM instructions in Thumb mode
The Requires class overrides the target requirements of an instruction,
rather than adding to them, so all ARM instructions need to include the
IsARM predicate when they have overwitten requirements.

This caused the swp and swpb instructions to be allowed in thumb mode
assembly, and the ARM encoding of CDP to be selected in codegen (which
is different for conditional instructions).

Differential Revision: https://reviews.llvm.org/D29283



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293634 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:35:01 +00:00
Benjamin Kramer
3bfb126ba5 [X86] Silence unused variable warning in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293631 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:13:53 +00:00
Silviu Baranga
150da15398 [InstCombine] Make sure that LHS and RHS have the same type in
transformToIndexedCompare

If they don't have the same type, the size of the constant
index would need to be adjusted (and this wouldn't be always
possible).

Alternatively we could try the analysis with the initial
RHS value, which would guarantee that the two sides have
the same type. However it is unlikely that in practice this
would pass our transformation requirements.

Fixes PR31808 (https://llvm.org/bugs/show_bug.cgi?id=31808).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293629 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:04:15 +00:00
Simon Pilgrim
438897d8de [X86][SSE] Detect unary PBLEND shuffles.
These can appear during shuffle combining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293628 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 13:58:01 +00:00
Simon Pilgrim
e8b7298325 [X86][SSE] Add support for combining PINSRW into a target shuffle.
Also add the ability to recognise PINSR(Vex, 0, Idx).

Targets shuffle combines won't replace multiple insertions with a bit mask until a depth of 3 or more, so we avoid codesize bloat.

The unnecessary vpblendw in clearupper8xi16a will be fixed in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293627 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 13:51:10 +00:00
Nemanja Ivanovic
9ca0f8737c [PowerPC][Altivec] Add vmr extended mnemonic
Just adds the vmr (Vector Move Register) mnemonic for the VOR instruction in
the PPC back end.

Committing on behalf of brunoalr (Bruno Rosa).

Differential Revision: https://reviews.llvm.org/D29133


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 13:43:11 +00:00
Florian Hahn
2938de42db [LoopUnroll] Use addClonedBlockToLoopInfo to clone the top level loop (NFC)
Summary:
rL293124 added the necessary infrastructure to properly add the cloned
top level loop to LoopInfo, which means we do not have to do it manually
in CloneLoopBlocks.

@mkuper sorry for not pointing this out during my review of D29156, I just
realized that today.


Reviewers: mzolotukhin, chandlerc, mkuper

Reviewed By: mkuper

Subscribers: llvm-commits, mkuper

Differential Revision: https://reviews.llvm.org/D29173

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293615 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 11:13:44 +00:00
Simon Dardis
0f9a41d64a [mips] Addition of the immediate cases for the instructions [d]div, [d]divu
Related to http://reviews.llvm.org/D15772

Depends on http://reviews.llvm.org/D16888

Adds support for immediate operand for [D]DIV[U] instructions.

Patch By: Srdjan Obucina

Reviewers: zoran.jovanovic, vkalintiris, dsanders, obucina

Differential Revision: https://reviews.llvm.org/D16889



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293614 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 10:49:24 +00:00
Craig Topper
5f528dcc0a [AVX-512] Don't both looking into the AVX512DQ execution domain fixing tables if AVX512DQ isn't supported since we can't do any conversion anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293608 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 06:49:55 +00:00
Craig Topper
25b197c99d [X86] Add AVX and SSE2 version of MOVSDmr to execution domain fixing table. AVX-512 already did this for the EVEX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 06:49:53 +00:00
Craig Topper
bde6e7c9de [AVX-512] Fix copy and paste bug in execution domain fixing tables so that we can convert 256-bit movnt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293606 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 06:49:50 +00:00
Justin Lebar
6731e5394b [NVPTX] Implement NVPTXTargetLowering::getSqrtEstimate.
Summary:

This lets us lower to sqrt.approx and rsqrt.approx under more
circumstances.

* Now we emit sqrt.approx and rsqrt.approx for calls to @llvm.sqrt.f32,
  when fast-math is enabled.  Previously, we only would emit it for
  calls to @llvm.nvvm.sqrt.f.  (With this patch we no longer emit
  sqrt.approx for calls to @llvm.nvvm.sqrt.f; we rely on intcombine to
  simplify llvm.nvvm.sqrt.f into llvm.sqrt.f32.)

* Now we emit the ftz version of rsqrt.approx when ftz is enabled.
  Previously, we only emitted rsqrt.approx when ftz was disabled.

Reviewers: hfinkel

Subscribers: llvm-commits, tra, jholewinski

Differential Revision: https://reviews.llvm.org/D28508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293605 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 05:58:22 +00:00
Craig Topper
374362d920 [X86] Update the broadcast fallback patterns to use shuffle instructions from the appropriate execution domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293603 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 05:18:29 +00:00
Craig Topper
04abfe94cf [X86] Add test cases for AVX1 broadcast fallback patterns when load can't be folded.
Also add test cases that do an insertelement to all elements for the 8 element vector tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 05:18:27 +00:00
Craig Topper
dc6cd899fc [AVX-512] Fix the ExeDomain for VMOVDDUP, VMOVSLDUP, and VMOVSHDUP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293601 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 05:18:24 +00:00
Matt Arsenault
3b595d2304 AMDGPU: Generalize matching of v_med3_f32
I think this is safe as long as no inputs are known to ever
be nans.

Also add an intrinsic for fmed3 to be able to handle all safe
math cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 03:07:46 +00:00
Matt Arsenault
6a569f5700 InferAddressSpaces: Rename constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293594 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:17:41 +00:00
Matt Arsenault
1394a16b28 InferAddressSpaces: Handle icmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293593 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:17:32 +00:00
Craig Topper
3a54f7ad1b [X86] Remove patterns for X86VPermilpi with integer types. I don't think we've formed these since the shuffle lowering rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293592 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:53 +00:00
Craig Topper
98925ead78 [X86] Remove duplicate patterns for X86VPermilpv that already exist in the instructions themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293591 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:51 +00:00
Craig Topper
afa112a7fa [X86] Remove patterns for selecting PSHUFD with FP types. We don't seem to do this anymore and the AVX case definitely should be using VPERMILPS anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293590 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:49 +00:00
Craig Topper
e45c0bf83f [X86] Remove 'else' after 'return'. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:46 +00:00
Craig Topper
1c8955ec1e [X86] Use integer broadcast instructions for integer broadcast patterns.
I'm not sure why we were using an FP instruction before and had to have a comment calling attention to it, but not justifying it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293588 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:43 +00:00
Matt Arsenault
35b092a75f InferAddressSpaces: Support memory intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 01:56:57 +00:00
Matt Arsenault
6be67912a8 InferAddressSpaces: Support atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293584 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 01:40:38 +00:00
Matt Arsenault
de6cb7e695 InferAddressSpaces: Don't replace volatile users
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 01:30:16 +00:00
Matt Arsenault
264e91f294 AMDGPU: Implement hook for InferAddressSpaces
For now just port some of the existing NVPTX tests
and from an old HSAIL optimization pass which
approximately did the same thing.

Don't enable the pass yet until more testing is done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293580 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 01:20:54 +00:00
Matt Arsenault
9be098398c NVPTX: Move InferAddressSpaces to generic code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293579 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 01:10:58 +00:00
Eugene Zelenko
bfea59083d [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293578 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 00:56:17 +00:00
Saleem Abdulrasool
91f734b9ab TableGen: use fully qualified name for StringLiteral
Use the qualified name for StringLiteral (llvm::StringLiteral) when
generating the sources.  This is needed as the generated files may be
used out-of-tree (e.g. swift) where you may not have a
`using namespace llvm;` resulting in an undefined lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293577 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 00:45:01 +00:00