139897 Commits

Author SHA1 Message Date
Kevin Enderby
bbe3a735a8 For llvm-objdump for Mach-O files add printing of
the ARM_THREAD_STATE in the same format as
otool-classic(1) on darwin.

Also remove an extra space in printing the initprot to make
the output match otool-classic(1) on darwin.

rdar://28851457


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284852 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 18:22:35 +00:00
Sanjay Patel
be29b1044e [DAG] fold negation of sign-bit
0 - X --> 0, if the sub is NUW
0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW
0 - X --> X, if X is 0 or the minimum signed value

This is the DAG equivalent of:
https://reviews.llvm.org/rL284649

plus the fold for the NUW case which already existed in InstSimplify.

Note that we miss a vector fold because of a deficiency in the DAG version of
computeKnownBits().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284844 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 17:24:26 +00:00
Sanjay Patel
7ff284e6ae [x86] add tests for potential negation folds
These are the backend equivalents for the tests added in r284627.
The patterns may emerge late, so we should have folds for these in the DAG too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284842 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:56:29 +00:00
Krzysztof Parzyszek
b77f18e769 [Hexagon] Handle spills of partially defined double vector registers
After register allocation it is possible to have a spill of a register
that is only partially defined. That in itself it fine, but creates a
problem for double vector registers. Stores of such registers are pseudo
instructions that are expanded into pairs of individual vector stores,
and in case of a partially defined source, one of the stores may use
an entirely undefined register. To avoid this, track the defined parts
and only generate actual stores for those.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284841 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:38:29 +00:00
Derek Schuff
dc833052ac [WebAssembly] Fix for 0xc call_indirect changes
Summary:
Need to reorder the operands to have the callee as the last argument.
Adds a pseudo-instruction, and a pass to lower it into a real
call_indirect.

This is the first of two options for how to fix the problem.

Reviewers: dschuff, sunfish

Subscribers: jfb, beanz, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D25708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284840 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:38:07 +00:00
Abderrazek Zaafrani
6706bad78d Set the vectorizer MaxInterleaveFactor for Exynos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284839 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:28:27 +00:00
Reid Kleckner
57a3dc5d8b Fix -Wunused-variable warning in libFuzzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284838 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:26:27 +00:00
Simon Pilgrim
c2abd3ebe2 [X86][SSE] Regenerated sext/zext constant folding tests and added i686 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284837 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:22:16 +00:00
Simon Pilgrim
ed8dcc872b [X86] Use DAG::getBuildVector helper wrapper where possible. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284835 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:07:51 +00:00
Konstantin Zhuravlyov
466e9f4bea [MachineMemOperand][AtomicSDNode] Remove getSuccessOrdering()
Differential Revision: https://reviews.llvm.org/D25786


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284834 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 16:02:35 +00:00
Simon Pilgrim
51f1efc164 [X86][SSE] Regenerated chained pmovsx store tests and added i686 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284833 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 15:51:24 +00:00
Abderrazek Zaafrani
b03d0d9ced Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284832 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 15:24:08 +00:00
Artur Pilipenko
d193fb5457 [LVI] Fix a bug with a guard being the very first instruction in a BB not taken into account
While looking for guards use reverse iterator and scan up to rend() not to begin()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284827 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 15:02:21 +00:00
Sanjay Patel
73cda08c45 fix variable names; NFCI
Because we're just 'or-ing' these 2 variables later in the code, I
don't think there's a logical bug here, but of course the string with
"no size" is the one that should have the size suffix stripped off.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284826 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 14:58:30 +00:00
Artem Tamazov
3398735496 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284825 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 14:49:22 +00:00
Sanjay Patel
f8de69b006 [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds
As discussed in D24815, let's start the process of killing off the broken fast-math global
state housed in TargetOptions and eliminate the need for function-level fast-math attributes.

Here we enable two similar folds that are possible when we don't care about signed-zero:
fadd nsz x, 0 --> x
fsub nsz 0, x --> -x

Note that although the test cases include a 'sin' function call, I'm side-stepping the 
FMF-on-calls question (and lack of support in the DAG) for now. It's not needed for these
tests - isNegatibleForFree/GetNegatedExpression just look through a ISD::FSIN node.

Also, when we create an FNEG node and propagate the Flags of the FSUB to it, this doesn't
actually do anything today because Flags are silently dropped for any node that is not a
binary operator.

Differential Revision: https://reviews.llvm.org/D25297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284824 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 14:36:58 +00:00
Simon Pilgrim
06bac82d8f [X86][AVX2] Begun generalizing lowering to VPERMD/VPERMPS in preparation for AVX512 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284823 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 13:00:47 +00:00
Simon Pilgrim
aaafc1d16c Wdocumentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284822 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 12:51:16 +00:00
Simon Pilgrim
01109e8b73 [X86][AVX512] Add mask/maskz writemask support to subvector broadcast shuffle decode comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284821 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 12:14:24 +00:00
John Brawn
9e0c61cbeb [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops
When we have a loop with a known upper bound on the number of iterations, and
furthermore know that either the number of iterations will be either exactly
that upper bound or zero, then we can fully unroll up to that upper bound
keeping only the first loop test to check for the zero iteration case.

Most of the work here is in plumbing this 'max-or-zero' information from the
part of scalar evolution where it's detected through to loop unrolling. I've
also gone for the safe default of 'false' everywhere but howManyLessThans which
could probably be improved.

Differential Revision: https://reviews.llvm.org/D25682


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284818 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 11:08:48 +00:00
Simon Pilgrim
4b5784c2cd [X86][AVX] Add 32-bit target tests for vector lzcnt/tzcnt to demonstrate missed folding opportunities
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284816 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 10:50:52 +00:00
Bjorn Pettersson
46ab1d2bd2 [AArch64] Corrected spill size for DDD register class. NFCI
Summary:
The spill size was incorrectly set to 196 bits,
which isn't a multiple of 8. This problem was detected when
experimenting with asserts that the spill size should be a
multiple of the byte size.

New corrected value for the spill size is set to 192 bits.

Note that tablegen (RegisterInfoEmitter) will divide the
size set in the RegisterClass definition by 8. So this
change should not have any impact on the tablegen output
(trunc(192/8) == trunc(196/8) == 24 bytes).

Reviewers: t.p.northover

Subscribers: llvm-commits, aemerson, rengolin

Differential Revision: https://reviews.llvm.org/D25818

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284814 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 09:53:42 +00:00
Benjamin Kramer
02d2642a5d Fix WebAssembly test after r284757.
The change to MachineSink shuffles code around, disable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284813 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 09:51:41 +00:00
Benjamin Kramer
c2cab9b61f [Support] Fix AlignOf test on i386-linux.
On i386 alignof(double) = 8 is not the same as alignof(struct { double
}) = 4. This used to be not an issue because the old implementation
always measured alignment inside of structs. Wrap a dummy struct around
the test to avoid this issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284812 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 09:15:57 +00:00
Craig Topper
7413606415 [AVX-512] Add tests to show opportunities for commuting vpermi2/vpermt2 instructions.
Commuting will be added in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284808 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 05:55:40 +00:00
Davide Italiano
b8c31038cf Revert "[GVN/PRE] Hoist global values outside of loops."
There's no agreement about this patch. I personally find the
PRE machinery of the current GVN hard enough to reason about
that I'm not sure I'll try to land this again, instead of working
on the rewrite).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284796 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 01:37:02 +00:00
Keno Fischer
a45d706e76 Fix cross-endianness RuntimeDyld relocation for ARM
rL284780 fixed the PREL31 relocation and added a test for it. Being
the first such test for ARM relocations, it exposed incorrect endianness
assumptions (causing buildbot failures on big-endian hosts). Fix that by
using the same helpers used for the x86 case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284789 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 22:15:56 +00:00
Li Huang
3c09f0b786 [SCEV] Add a threshold to restrict number of mul operands to be inlined into SCEV
This is to avoid inlining too many multiplication operands into a SCEV, which could 
take exponential time in the worst case.

Reviewers: Sanjoy Das, Mehdi Amini, Michael Zolotukhin

Differential Revision: https://reviews.llvm.org/D25794


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284784 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 21:38:39 +00:00
Keno Fischer
a5f79d9770 Fix PREL31 relocation on ARM
Summary:
This is a 31bits relative relocation instead of a 32bits absolute relocation.

Reviewers: t.p.northover, peter.smith, rengolin

Subscribers: aemerson, llvm-commits, samparker

Differential Revision: https://reviews.llvm.org/D25069

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 21:15:29 +00:00
Michael Kuperstein
fe040323c6 [X86] Enable interleaved memory access by default
This lets the loop vectorizer generate interleaved memory accesses on x86.

Differential Revision: https://reviews.llvm.org/D25350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284779 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 21:04:31 +00:00
Daniel Berlin
6d6a5e6250 [MSSA] Avoid unnecessary use walks when calling getClobberingMemoryAccess
Summary:
This allows us to mark when uses have been optimized.
This lets us avoid rewalking (IE when people call getClobberingAccess on everything), and also
enables us to later relax the requirement of use optimization during updates with less cost.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25172

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284771 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 20:13:45 +00:00
Kevin Enderby
d6842a6b77 Another additional error check for invalid Mach-O files for the
load commands that use the MachO::twolevel_hints_command type
which includes only the LC_TWOLEVEL_HINTS load command.

This is not used in llvm libObject code or in llvm tool code.  But
does appear in one of the binary test files.  While this load command is
obsolete it is easier to add code for it in libObject than edit or change
the binary test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284769 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 20:10:30 +00:00
Zachary Turner
838c3a9ae7 Fix case of file include path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284763 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:34:37 +00:00
Zachary Turner
a459ab93aa [CodeView] Refactor serialization to use StreamInterface.
This was all using ArrayRef<>s before which presents a problem
when you want to serialize to or deserialize from an actual
PDB stream.  An ArrayRef<> is really just a special case of
what can be handled with StreamInterface though (e.g. by using
a ByteStream), so changing this to use StreamInterface allows
us to plug in a PDB stream and get all the record serialization
and deserialization for free on a MappedBlockStream.

Subsequent patches will try to remove TypeTableBuilder and
TypeRecordBuilder in favor of class that operate on
Streams as well, which should allow us to completely merge
the reading and writing codepaths for both types and symbols.

Differential Revision: https://reviews.llvm.org/D25831

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:31:19 +00:00
Konstantin Zhuravlyov
37962abba1 [AMDGPU] Make note record name a static const member of target streamer
Differential Revision: https://reviews.llvm.org/D25746


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284760 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:22:36 +00:00
Konstantin Zhuravlyov
e0e811c4ce [AMDGPU] Emit constant address space data in .rodata section and use relocations instead of fixups (amdhsa only)
Differential Revision: https://reviews.llvm.org/D25693


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284759 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:12:38 +00:00
Dehao Chen
0872bb248f Using branch probability to guide critical edge splitting.
Summary:
The original heuristic to break critical edge during machine sink is relatively conservertive: when there is only one instruction sinkable to the critical edge, it is likely that the machine sink pass will not break the critical edge. This leads to many speculative instructions executed at runtime. However, with profile info, we could model the splitting benefits: if the critical edge has 50% taken rate, it would always be beneficial to split the critical edge to avoid the speculated runtime instructions. This patch uses profile to guide critical edge splitting in machine sink pass.

The performance impact on speccpu2006 on Intel sandybridge machines:

spec/2006/fp/C++/444.namd                  25.3  +0.26%
spec/2006/fp/C++/447.dealII               45.96  -0.10%
spec/2006/fp/C++/450.soplex               41.97  +1.49%
spec/2006/fp/C++/453.povray               36.83  -0.96%
spec/2006/fp/C/433.milc                   23.81  +0.32%
spec/2006/fp/C/470.lbm                    41.17  +0.34%
spec/2006/fp/C/482.sphinx3                48.13  +0.69%
spec/2006/int/C++/471.omnetpp             22.45  +3.25%
spec/2006/int/C++/473.astar               21.35  -2.06%
spec/2006/int/C++/483.xalancbmk           36.02  -2.39%
spec/2006/int/C/400.perlbench              33.7  -0.17%
spec/2006/int/C/401.bzip2                  22.9  +0.52%
spec/2006/int/C/403.gcc                   32.42  -0.54%
spec/2006/int/C/429.mcf                   39.59  +0.19%
spec/2006/int/C/445.gobmk                 26.98  -0.00%
spec/2006/int/C/456.hmmer                 24.52  -0.18%
spec/2006/int/C/458.sjeng                 28.26  +0.02%
spec/2006/int/C/462.libquantum            55.44  +3.74%
spec/2006/int/C/464.h264ref               46.67  -0.39%

geometric mean                                   +0.20%

Manually checked 473 and 471 to verify the diff is in the noise range.

Reviewers: rengolin, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24818

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284757 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:06:52 +00:00
Simon Pilgrim
e1ac64bc87 [CostModel][X86] Fixed AVX1/AVX512 sdiv/udiv uniformconst costs for 256/512 bit integer vectors
We weren't checking for uniform const costs before the general cost, resulting in very high estimates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284755 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 18:00:35 +00:00
Pirama Arumuga Nainar
f2b19f9394 Fix *_EXTEND_VECTOR_INREG legalization
Summary:
While promoting *_EXTEND_VECTOR_INREG nodes whose inputs are already
promoted, perform the appropriate sign extension for the promoted node
before doing the *_EXTEND_VECTOR_INREG operation.  If not, the undefined
high-order bits of the promoted operand may (a) be garbage inc ase of
zext) or (b) contribute the wrong sign-bit (in case of sext)

Updated the promote-vec3.ll test after this change.  The diff shows
explicit zeroing in case of zext and intermediate sign extension in case
of sext.

Reviewers: RKSimon

Subscribers: llvm-commits, srhines

Differential Revision: https://reviews.llvm.org/D25790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284752 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 17:56:36 +00:00
Simon Pilgrim
ca13ae18d8 [CostModel][X86] Added tests for sdiv/udiv costs for uniform const and uniform const power-of-2
Shows poor costings in AVX1/AVX512BW for certain vector types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284748 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 17:16:38 +00:00
Sanjay Patel
928f047b68 [Target] remove TargetRecip class; 2nd try
This is a retry of r284495 which was reverted at r284513 due to use-after-scope bugs
caused by faulty usage of StringRef.

This version also renames a pair of functions:
getRecipEstimateDivEnabled()
getRecipEstimateSqrtEnabled()
as suggested by Eric Christopher.

original commit msg:

[Target] remove TargetRecip class; move reciprocal estimate isel functionality to TargetLowering

This is a follow-up to https://reviews.llvm.org/D24816 - where we changed reciprocal estimates to be function attributes
rather than TargetOptions.

This patch is intended to be a structural, but not functional change. By moving all of the
TargetRecip functionality into TargetLowering, we can remove all of the reciprocal estimate
state, shield the callers from the string format implementation, and simplify/localize the
logic needed for a target to enable this.

If a function has a "reciprocal-estimates" attribute, those settings may override the target's
default reciprocal preferences for whatever operation and data type we're trying to optimize.
If there's no attribute string or specific setting for the op/type pair, just use the target
default settings.

As noted earlier, a better solution would be to move the reciprocal estimate settings to IR
instructions and SDNodes rather than function attributes, but that's a multi-step job that
requires infrastructure improvements. I intend to work on that, but it's not clear how long
it will take to get all the pieces in place.

Differential Revision: https://reviews.llvm.org/D25440



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284746 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 16:55:45 +00:00
Benjamin Kramer
c32b5967a7 Put the move ctor for PassManager back for now, it breaks some builds.
For some reason using the default move ctor creates undefined references
to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284745 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 16:50:07 +00:00
Simon Pilgrim
99edc4fc3c [CostModel][X86] Fixed AVX1/AVX512 sdiv/udiv general costs for 256/512 bit integer vectors
We weren't accounting for legal types on every subtarget, meaning that many of the costs were using defaults.

We still don't correctly cost (or test) the 512-bit sdiv/udiv by uniform const cases, nor the power-of-2 cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284744 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 16:39:11 +00:00
Valery Pykhtin
446cd5eefe [AMDGPU] add fcopysign(f64, f32) pattern
Differential revision: https://reviews.llvm.org/D25827

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284743 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 16:17:54 +00:00
Benjamin Kramer
fd82ba5f93 [Support] Put back the MSVC hack for AlignedCharArray.
MSVC 2015 still errors when passing an alignas'd object by value as an
argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284738 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 15:53:04 +00:00
Benjamin Kramer
cafdc34428 [Support] Remove llvm::alignOf now that all uses are gone.
Also clean up the legacy hacks for AlignedCharArray. I'm keeping
LLVM_ALIGNAS alive for a bit longer because GCC 4.8.0 (which we still
support apparently) shipped a buggy alignas(). All other supported
compilers have a working alignas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284736 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 15:36:38 +00:00
Benjamin Kramer
cb58e1e3bc Retire llvm::alignOf in favor of C++11 alignof.
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284733 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 15:02:18 +00:00
Benjamin Kramer
2913220dd6 [GVN] Use defaulted members. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 13:09:12 +00:00
Simon Dardis
f7463aa366 [mips][mcjit] Add the majority of N32 support.
The missing piece is relocation composition for %hi(%neg(%gp_rel(x))) and
similar.

Patch by: Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 13:02:23 +00:00
Simon Pilgrim
7b259eb4f8 [CostModel][X86] Added tests for sdiv/udiv costs for scalar and 128/256/512 bit integer vectors
Shows current bug in AVX1/AVX512BW costs for 256 bit vector types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284723 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-20 12:34:00 +00:00