147462 Commits

Author SHA1 Message Date
Petr Hosek
75d650872f [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia
This mode is just like -mcmodel=small except that it moves the
thread pointer from TPIDR_EL0 to TPIDR_EL1.

Patch by Roland McGrath.

Differential Revision: https://reviews.llvm.org/D31624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299462 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:51:53 +00:00
Craig Topper
80bfe66e42 [InstCombine] Add test cases for missing combines of phis with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299460 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:31:21 +00:00
Yi Kong
4dd33e6269 Implement host CPU detection for AArch64
This shares detection logic with ARM(32), since AArch64 capable CPUs may
also run in 32-bit system mode.

We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where
they report all CPU cores as one single model, depending on which CPU
core the kernel is running on. As a workaround, we hardcode the known
CPU part name for these SoCs.

For big.LITTLE systems, this patch would only return the part name of
the first core (usually the little core). Proper support will be added
in a follow-up change.

Differential Revision: D31675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299458 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:06:04 +00:00
Matt Arsenault
dce3b51aea Verifier: Check some amdgpu calling convention restrictions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299457 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 18:43:11 +00:00
Balaram Makam
5d76ab9dec [AArch64] Refine Falkor Machine Model - Part 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299456 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 18:42:14 +00:00
Coby Tayree
983e1a1b99 [X86][inline-asm] Add support for MS 'EVEN' directive
MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'.
This patch include the (small, simple) changes need to allow it.

Test is provided at the following (clang-side) review:
https://reviews.llvm.org/D27418

Differential Revision: https://reviews.llvm.org/D27417



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299453 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:57:23 +00:00
Craig Topper
c1eaf3a1f1 [InstCombine] Add more test cases for missing combines of selects with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299450 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:48:08 +00:00
Lang Hames
e65aa1c44e [RuntimeDyld] Make RuntimeDyld honor the ProcessAllSections flag.
When the ProcessAllSections flag (introduced in r204398) is set RuntimeDyld is
supposed to make a call to the client's memory manager for every section in each
object that is loaded. Due to some missing checks, this was not happening in all
cases. This patch adds the missing cases, and fixes the Orc unit test that
verifies correct behavior for ProcessAllSections (The unit test had been
silently bailing out due to an ordering issue: a change in the test order meant
that this unit-test was running before the native target was registered. This
issue has also been fixed in this patch).

This fixes <rdar://problem/22789965>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299449 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:03:49 +00:00
Sanjay Patel
1f3f346415 [x86] remove dead select-of-constants transform; NFCI
https://reviews.llvm.org/D30537 / https://reviews.llvm.org/rL296977 added these transforms
and other related transforms to the generic DAGCombiner (with a hook that x86 sets to true),
so these patterns should not exist by the time we reach the target-specific combiner hook.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299448 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 16:54:58 +00:00
Rong Xu
9e52f8ee8b [PGO] Memory intrinsic calls optimization based on profiled size
This patch optimizes two memory intrinsic operations: memset and memcpy based
on the profiled size of the operation. The high level transformation is like:
  mem_op(..., size)
  ==>
  switch (size) {
    case s1:
       mem_op(..., s1);
       goto merge_bb;
    case s2:
       mem_op(..., s2);
       goto merge_bb;
    ...
    default:
       mem_op(..., size);
       goto merge_bb;
    }
  merge_bb:

Differential Revision: http://reviews.llvm.org/D28966


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299446 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 16:42:20 +00:00
Matt Arsenault
452506a655 AMDGPU: Remove legacy export intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 16:34:39 +00:00
Matt Arsenault
f486610d1f AMDGPU: Remove legacy image intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299443 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 16:34:35 +00:00
Coby Tayree
7c1642caaf [X86][MS-compatability]Allow named synonymous for MS-assembly operators
This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx

Differential Revision: D31277



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299439 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 14:43:23 +00:00
Simon Pilgrim
21de338c73 Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299438 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 14:40:53 +00:00
Daniel Sanders
62b3ad70e2 [globalisel][tablegen] Fix non-determinism introduced in r299430.
This should fix the last issue on llvm-clang-x86_64-expensive-checks-win.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299436 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 14:27:06 +00:00
Daniel Sanders
8eaecfe64f [globalisel][tablegen] Try to make MSVC happy with r299430
Fix other cases of 'const StringRef' creeping back in at the same time.

This should fix the llvm-clang-x86_64-expensive-checks-win buildbot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299433 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 13:52:00 +00:00
Michael Zuckerman
3341db988b [X86][LLVM] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into generic intrinsics.
This patch is a part one of two reviews, one for the clang and the other for LLVM. 
The patch deletes the back-end intrinsics and adds support for them in the auto upgrade.

Differential Revision: https://reviews.llvm.org/D31393


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299432 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 13:32:14 +00:00
Daniel Sanders
690f0b25ab [tablegen][globalisel] Add support for nested instruction matching.
Summary:
Lift the restrictions that prevented the tree walking introduced in the
previous change and add support for patterns like:
  (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3
Also adds support for G_SEXT and G_ZEXT to support these cases.

One particular aspect of this that I should draw attention to is that I've
tried to be overly conservative in determining the safety of matches that
involve non-adjacent instructions and multiple basic blocks. This is intended
to be used as a cheap initial check and we may add a more expensive check in
the future. The current rules are:
* Reject if any instruction may load/store (we'd need to check for intervening
  memory operations.
* Reject if any instruction has implicit operands.
* Reject if any instruction has unmodelled side-effects.
See isObviouslySafeToFold().

Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka

Reviewed By: ab

Subscribers: igorb, dberris, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D30539



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299430 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 13:25:23 +00:00
Simon Dardis
d7a71bf354 [mips] Deal with empty blocks in the mips hazard scheduler
This patch teaches the hazard scheduler how to handle empty blocks
when search for the next real instruction when dealing with forbidden
slots.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D31293



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299427 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 11:28:53 +00:00
Oren Ben Simhon
78ed6ce91d [X86] Add 64 bit pattern matching for PSADBW
PSADBW pattern currently supports the 32 bit IR pattern and only GLT (greather than) comparison.
The patch extends the pattern to catch also 64 bit IR pattern and includes all other comparison types (not only GLT).

Differential Revision: https://reviews.llvm.org/D31577



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299425 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 10:23:18 +00:00
Jonas Hahnfeld
ba1514c219 Align all scalar numbers to LLVM_YAML_IS_FLOW_SEQUENCE_VECTOR
Otherwise, yamlize in YAMLTraits.h might be wrongly defined.
This makes some AMDGPU tests fail when LLVM_LINK_LLVM_DYLIB is set.

Differential Revision: https://reviews.llvm.org/D30508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299415 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 06:02:32 +00:00
Craig Topper
099a6fd775 [InstCombine] Use setAllBits in place of getAllOnesValue since we know the bitwidths are the same. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299413 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 05:03:02 +00:00
Zvi Rackover
c7f9b76a74 InstCombine: Use the InstSimplify hook for shufflevector
Summary: Start using the recently added InstSimplify hook for shuffles in the respective InstCombine visitor.

Reviewers: spatel, RKSimon, craig.topper, majnemer

Reviewed By: majnemer

Subscribers: majnemer, llvm-commits

Differential Revision: https://reviews.llvm.org/D31526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299412 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 04:47:57 +00:00
Reid Kleckner
48f7bb5c74 [PDB] Save one type record copy
Summary:
The TypeTableBuilder provides stable storage for type records. We don't
need to copy all of the bytes into a flat vector before adding it to the
TpiStreamBuilder.

This makes addTypeRecord take an ArrayRef<uint8_t> and a hash code to go
with it, which seems like a simplification.

Reviewers: ruiu, zturner, inglorion

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31634

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299406 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 00:56:34 +00:00
Reid Kleckner
7c5b7f36c1 [codeview] Cope with unsorted streams in type merging
Summary:
MASM can produce type streams that are not topologically sorted. It can
even produce type streams with circular references, but those are not
common in practice.

Reviewers: inglorion, ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31629

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299403 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 23:58:15 +00:00
Reid Kleckner
d6780ccb60 [Fuzzer] Flush std::cout before aborting in CxxStringEqTest
On Windows, abort() does not appear to flush std::cout. Should fix red
sanitizer-windows bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299398 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 23:00:25 +00:00
Sanjay Patel
e20330959b add/move codegen tests for and/or of setcc; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299396 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 22:45:46 +00:00
Tim Northover
9d740a4a71 Update stale doxygen links in ProgrammersManual.rst
Patch by Wei-Ren Chen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299395 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 22:24:32 +00:00
Zvi Rackover
07d42b869d InstSimplify: Add a hook for shufflevector
Summary:
Add a hook for simplification of shufflevector's with the following rules:
- Constant folding - NFC, as it was already being done by the default handler.
-  If only one of the operands is constant, constant fold the shuffle if the
    mask does not select elements from the variable operand -  to show the hook is firing and affecting the test-cases.

Reviewers: RKSimon, craig.topper, spatel, sanjoy, nlopes, majnemer

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299393 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 22:05:30 +00:00
Weiming Zhao
c4d3801c20 Reland r298901 with modifications (reverted in r298932)
Dont emit Mapping symbols for sections that contain only data.

Summary:
Dont emit mapping symbols for sections that contain only data.

Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith

Reviewed By: t.p.northover

Patched by Shankar Easwaran <shankare@codeaurora.org>

Subscribers: alekseyshl, t.p.northover, llvm-commits

Differential Revision: https://reviews.llvm.org/D30724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299392 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 21:50:04 +00:00
Matt Arsenault
513e714dfd AMDGPU: Remove llvm.SI.vs.load.input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299391 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 21:45:13 +00:00
Matt Arsenault
5b7b340242 DAG: Fix missing legalization for any_extend_vector_inreg operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299389 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 21:28:13 +00:00
Reid Kleckner
2c2955a045 [codeview] Add support for label type records
MASM can produce these type records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299388 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 21:25:20 +00:00
Simon Pilgrim
dc4f56dd52 [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + VECTOR_SHUFFLE
It can be costly to transfer from the gprs to the xmm registers and can prevent loads merging.

This patch splits vXi16/vXi32/vXi64 BUILD_VECTORS that use the same operand in multiple elements into a BUILD_VECTOR with only a single insertion of each of those elements and then performs an unary shuffle to duplicate the values.

There are a couple of minor regressions this patch unearths due to some missing MOVDDUP/BROADCAST folds that I will address in a future patch.

Note: Now that vector shuffle lowering and combining is pretty good we should be reusing that instead of duplicating so much in LowerBUILD_VECTOR - this is the first of several patches to address this.

Differential Revision: https://reviews.llvm.org/D31373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299387 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 21:06:51 +00:00
Craig Topper
d1815f3bc3 [InstCombine] Remove canonicalization for (X & C1) | C2 --> (X | C2) & (C1|C2) when C1 & C2 have common bits.
It turns out that SimplifyDemandedInstructionBits will get called earlier and remove bits from C1 first. Effectively doing (X & (C1&C2)) | C2. So by the time it got to this check there could be no common bits.

I think the DAGCombiner has the same check but its check can be executed because it handles demanded bits later. I'll look at it next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299384 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 20:41:47 +00:00
Amjad Aboud
019f65e751 x86 interrupt calling convention: re-align stack pointer on 64-bit if an error code was pushed
The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated.

This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue.

Fixes Bug 26413

Patch by Philipp Oppermann.

Differential Revision: https://reviews.llvm.org/D30049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299383 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 20:28:45 +00:00
Jun Bum Lim
78c95b332b [CodeGenPrep] move aarch64-type-promotion to CGP
Summary:
Move the aarch64-type-promotion pass within the existing type promotion framework in CGP.
This change also support forking sexts when a new sext is required for promotion.
Note that change is based on D27853 and I am submitting this out early to provide a better idea on D27853.

Reviewers: jmolloy, mcrosier, javed.absar, qcolombet

Reviewed By: qcolombet

Subscribers: llvm-commits, aemerson, rengolin, mcrosier

Differential Revision: https://reviews.llvm.org/D28680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299379 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 19:20:07 +00:00
Craig Topper
445d3cfd6b [DAGCombine][InstCombine] Fix inverted if condition in equivalent comments in DAGCombine and InstCombine. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299378 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 19:18:48 +00:00
Joel Jones
5b2afe9ffb Fix LLVMBuild.txt typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299373 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 18:21:50 +00:00
Matt Arsenault
cd7c9c3178 AMDGPU: Remove legacy bfe intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299372 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 18:08:08 +00:00
Graydon Hoare
211802721c [Support] Make printAllJSONValues public, for custom output.
Summary:
This changes the static method TimerGroup::printAllJSONValues from private to
public, to match the static method TimerGroup::printAll. When trying to drive
the reporting machinery by hand, the existing API is _almost_ flexible enough,
but this entrypoint is required to intermix printing timers with other
non-timer output.

The underlying motive here is a Swift change to consolidate the collection of
timers, LLVM statistics and other (non-assert-dependent) counters into JSON
files, which requires a bit of manual intervention in LLVM's stat and timer
output routines. See https://github.com/apple/swift/pull/8477 for details.

Reviewers: MatzeB

Reviewed By: MatzeB

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299371 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 18:04:15 +00:00
Peter Collingbourne
7bceb16031 Bitcode: Remove reader support for MODULE_CODE_PURGEVALS.
Support for writing this module code was removed in r73220, which was well
before the LLVM 3.0 release, so we do not need to be able to understand it
for backwards compatibility.

Differential Revision: https://reviews.llvm.org/D31563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299370 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:58:48 +00:00
Craig Topper
aee31d3e9a [InstCombine] Add test cases showing how we fail to fold vector constants into selects the way we do with scalars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299369 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:49:15 +00:00
Zvi Rackover
f60f35be0a Revert "[DAGCombine] A shuffle of a splat is always the splat itself"
This reverts commit r299047 which is incorrect because the
simplification may result in incorrect propogation of undefs to users of
the folded shuffle.

Thanks to Andrea Di Biagio for pointing this out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299368 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:41:19 +00:00
Krzysztof Parzyszek
ab1bde3393 [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299367 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:26:40 +00:00
Craig Topper
1cca49874c Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"
One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers.

Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299366 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 17:22:23 +00:00
Sanjay Patel
7d1d15ba84 [InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCI
1. Improve enum, function, and variable names.
2. Improve comments.
3. Fix variable capitalization.
4. Run clang-format.

As an existing code comment suggests, this should work with vector types / splat constants too,
so making this look right first will reduce the diffs needed for that change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299365 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 16:53:12 +00:00
Craig Topper
68149f546e [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt class. Implement them without memory allocation for multiword
This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation.

Differential Revision: https://reviews.llvm.org/D31565




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299362 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 16:34:59 +00:00
Simon Pilgrim
3c078c1589 [DAGCombiner] Check limits before accessing array element (PR32502)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299361 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 15:27:49 +00:00
Sjoerd Meijer
d369b4141b ARMAsmParser: clean up of isImmediate functions
- we are now using immediate AsmOperands so that the range check functions are
  tablegen'ed.
- Big bonus is that error messages become much more accurate, i.e. instead of a
  useless "invalid operand" error message it will not say that the immediate
  operand must in range [x,y], which is why regression tests needed updating.

More tablegen operand descriptions could probably benefit from using
immediateAsmOperand, but this is a first good step to get rid of most of the
nearly identical range check functions. I will address the remaining immediate
operands in next clean ups.

Differential Revision: https://reviews.llvm.org/D31333



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299358 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03 14:50:04 +00:00