1551 Commits

Author SHA1 Message Date
Simon Pilgrim
ada0a4f5b0 [DAGCombine] Allow vector constant folding of any value type before type legalization
The patch comes in 2 parts:

1 - it makes use of the SelectionDAG::NewNodesMustHaveLegalTypes flag to tell when it can safely constant fold illegal types.

2 - it correctly resets SelectionDAG::NewNodesMustHaveLegalTypes at the start of each call to SelectionDAGISel::CodeGenAndEmitDAG so all the pre-legalization stages can make use of it - not just the first basic block that gets handled.

Fix for PR30760

Differential Revision: https://reviews.llvm.org/D29568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294749 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-10 14:37:25 +00:00
Amaury Sechet
6f12c47b49 Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.
Summary: As per title.

Reviewers: bkramer, sunfish, lattner, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294188 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-06 14:59:06 +00:00
Amaury Sechet
ffd1e5a54c [DAGCombiner] Make DAGCombiner smarter about overflow
Summary: Leverage it to transform addc into add.

Reviewers: mkuper, spatel, RKSimon, zvi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294187 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-06 14:54:49 +00:00
Simon Pilgrim
0aca40051b [X86][SSE] Combine shuffle nodes with multiple uses if all the users are being combined.
Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines.

We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree.

This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list.

Differential Revision: https://reviews.llvm.org/D29399

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294183 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-06 13:44:45 +00:00
Matt Arsenault
430953ebc8 DAG: Constant fold fp16_to_fp/fp16_to_fp
This fixes emitting conversions of constants on targets
without legal f16 that need to use these for legalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293499 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 16:57:41 +00:00
Craig Topper
544a997a27 [SelectionDAG] Make SDNode::getConstantOperandVal an inline method.
It's operation already exists manually in many places without using the method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293421 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-29 06:08:02 +00:00
Craig Topper
8a3705cb10 [SelectionDAG] Teach getNode to simplify a couple easy cases of EXTRACT_SUBVECTOR
Summary:
This teaches getNode to simplify extracting from Undef. This is similar to what is done for EXTRACT_VECTOR_ELT. It also adds support for extracting from CONCAT_VECTOR when we can reuse one of the inputs to the concat. These seem like simple non-target specific optimizations.

For X86 we currently handle undef in extractSubvector, but not all EXTRACT_SUBVECTOR creations go through there.

Ultimately, my motivation here is to simplify extractSubvector and remove custom lowering for EXTRACT_SUBVECTOR since we don't do anything but handle undef and BUILD_VECTOR optimizations, but those should be DAG combines.

Reviewers: RKSimon, delena

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29000

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 02:36:59 +00:00
Simon Pilgrim
64f91a5757 [SelectionDAG] Improve knownbits handling of UMIN/UMAX (PR31293)
This patch improves the knownbits logic for unsigned integer min/max opcodes.

For UMIN we know that the result will have the maximum of the inputs' known leading zero bits in the result, similarly for UMAX the maximum of the inputs' leading one bits.

This is particularly useful for simplifying clamping patterns,. e.g. as SSE doesn't have a uitofp instruction we want to use sitofp instead where possible and for that we need to confirm that the top bit is not set.

Differential Revision: https://reviews.llvm.org/D28853

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292528 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 22:41:22 +00:00
Matt Arsenault
4cddac93ec DAG: Consider nnan in isKnownNeverNaN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292328 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 02:10:08 +00:00
Simon Pilgrim
1f7c0c9364 [SelectionDAG] Add knownbits support for BITREVERSE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292130 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 14:49:26 +00:00
Simon Pilgrim
b648fac5ca [SelectionDAG] Add support for BITREVERSE constant folding
We were relying on constant folding of the legalized instructions to do what constant folding we had previously

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292114 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16 13:39:00 +00:00
Malcolm Parsons
60f78e3e92 Remove unused lambda captures. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-13 17:12:16 +00:00
Matt Arsenault
d8c5040a18 Remove unused CONVERT_RNDSAT intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-10 22:38:02 +00:00
Simon Dardis
961fc84304 [mips] Fix Mips MSA instrinsics
The usage of some MIPS MSA instrinsics that took immediates could crash LLVM
during lowering. This patch addresses that behaviour. Crucially this patch
also makes the use of intrinsics with out of range immediates as producing an
internal error.

The ld,st instrinsics would trigger an assertion failure for MIPS64 as their
lowering would attempt to add an i32 offset to a i64 pointer.

Reviewers: vkalintiris, slthakur

Differential Revision: https://reviews.llvm.org/D25438



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-10 16:40:57 +00:00
Simon Pilgrim
a3ff10f4aa [SelectionDAG] Early out from computeKnownBits when we know we will have no common bits.
Avoid extra (recursive) calls to computeKnownBits if we already know that there are no common known bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290490 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-24 12:59:35 +00:00
Matt Arsenault
27bb0f08ca DAG: Add helper for testing constant values
There are helpers for testing for constant or constant build_vector,
and for splat ConstantFP vectors, but not for a constantfp or
non-splat ConstantFP vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290317 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:39:45 +00:00
Joel Jones
a07f27643c Fix name typo in SelectonDAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289969 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-16 18:22:54 +00:00
Simon Pilgrim
ddae161376 [DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2
Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases.

Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value.

Differential Revision: https://reviews.llvm.org/D27714

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289654 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-14 15:08:13 +00:00
Stephan Bergmann
20a600c431 Replace APFloatBase static fltSemantics data members with getter functions
At least the plugin used by the LibreOffice build
(<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly
uses those members (through inline functions in LLVM/Clang include files in turn
using them), but they are not exported by utils/extract_symbols.py on Windows,
and accessing data across DLL/EXE boundaries on Windows is generally
problematic.

Differential Revision: https://reviews.llvm.org/D26671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289647 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-14 11:57:17 +00:00
Simon Pilgrim
7e389a2c48 [SelectionDAG] computeKnownBits - simplified knownbits sign extension. NFCI.
We don't need to extract+test the sign bit of the known ones/zeros, we can use sext which will handle all of this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289534 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-13 13:36:27 +00:00
Simon Pilgrim
2dc2fca37b [SelectionDAG] Add support for EXTRACT_SUBVECTOR to ComputeNumSignBits
Pre-commit as discussed on D27657

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289425 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-12 10:29:43 +00:00
Simon Pilgrim
9f18372c90 [SelectionDAG] Add ability for computeKnownBits to peek through bitcasts from 'large element' scalar/vector to 'small element' vector.
Extension to D27129 which already supported bitcasts from 'small element' vector to 'large element' scalar/vector types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289329 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-10 17:00:00 +00:00
Simon Pilgrim
70df293944 [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)
Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289232 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 17:53:11 +00:00
Simon Pilgrim
699047a12d [SelectionDAG] Use SelectionDAG.getBuildVector helper. NFCI.
Makes interception of BUILD_VECTOR creation easier for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289218 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 15:23:41 +00:00
Simon Pilgrim
3ddbece9fe [SelectionDAG] Add additional checks to CONCAT_VECTORS creation
Part of the work for PR31323 - add extra asserts checking that the input vectors are of consistent type and result in the correct number of vector elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289214 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 14:27:52 +00:00
Simon Pilgrim
ce7af2b725 [SelectionDAG] Add partial BITCAST support to computeKnownBits
Adds support for bitcasting a little endian 'small element' vector to 'large element' scalar/vector (e.g. v16i8 to v4i32 or v2i32 to i64), which is required for PR30845. We extract the knownbits for each 'small element' part and concatenate the results together.

We can add support for big endian and 'large element' scalar/vector to 'small element' vector bitcasting once we have test cases for them.

Differential Revision: https://reviews.llvm.org/D27129

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 10:13:45 +00:00
Daniel Jasper
a47587665f Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes"
This reverts commit r288916 as it is currently causing a crasher in
Halide. Reproducer on llvm.org/PR31323. While it might be that halide is
generating invalid IR, llc shouldn't crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289194 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 09:04:51 +00:00
Simon Pilgrim
aee7c6e2f5 [SelectionDAG] Add knownbits support for vector demandedelts in SMAX/SMIN/UMAX/UMIN opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288926 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-07 17:54:00 +00:00
Simon Pilgrim
def95b9c34 [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288916 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-07 16:28:21 +00:00
Simon Pilgrim
9b37990fd7 [SelectionDAG] Removed old knownbits TODO comment. NFCI.
EXTRACT_VECTOR_ELT does support demanded elts if the element index is known and in range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288913 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-07 15:31:12 +00:00
Simon Pilgrim
3074f79595 [SelectionDAG] We can ignore knownbits from an undef shuffle vector index if we don't actually demand that element
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288839 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-06 18:58:25 +00:00
Simon Pilgrim
44a9007743 Avoid repeated calls to Op.getOpcode(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288814 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-06 14:50:09 +00:00
Matt Arsenault
728c815331 DAG: Fold out out of bounds insert_vector_elt
getNode already prevents formation of out of bounds constant
extract_vector_elts. Do the same for insert_vector_elt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288603 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-03 23:03:26 +00:00
John Brawn
aae639e0bd [DAGCombiner] Fix infinite loop in vector mul/shl combining
We have the following DAGCombiner transformations:
 (mul (shl X, c1), c2) -> (mul X, c2 << c1)
 (mul (shl X, C), Y) -> (shl (mul X, Y), C)
 (shl (mul x, c1), c2) -> (mul x, c1 << c2)
Usually the constant shift is optimised by SelectionDAG::getNode when it is
constructed, by SelectionDAG::FoldConstantArithmetic, but when we're dealing
with vectors and one of those vector constants contains an undef element
FoldConstantArithmetic does not fold and we enter an infinite loop.

Fix this by making FoldConstantArithmetic use getNode to decide how to fold each
vector element, the same as FoldConstantVectorArithmetic does, and rather than
adding the constant shift to the work list instead only apply the transformation
if it's already been folded into a constant, as if it's not we're going to loop
endlessly. Additionally add missing NoOpaques to one of those transformations,
which I noticed when writing the tests for this.

Differential Revision: https://reviews.llvm.org/D26605


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287766 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-23 16:05:51 +00:00
Simon Pilgrim
3d4bb54474 [SelectionDAG] ComputeNumSignBits of TRUNCATE operations
Add basic ComputeNumSignBits support for TRUNCATE ops for cases where the source's number of sign bits overlaps with the truncated size.

Improves X86 SIGN_EXTEND_IN_REG vector cases which were needlessly sign extending boolean vector results.

Differential Revision: https://reviews.llvm.org/D26851

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287635 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-22 11:29:19 +00:00
Simon Pilgrim
09211df264 [SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287541 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-21 14:36:19 +00:00
Simon Pilgrim
3000aab2fb [SelectionDAG] Add knowbits support for CONCAT_VECTOR opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287387 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-18 22:21:22 +00:00
Simon Pilgrim
aa9211b5c6 [SelectionDAG] Add support for vector demandedelts in BSWAP opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286582 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:51:29 +00:00
Simon Pilgrim
912c7ec127 [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286578 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 11:23:43 +00:00
Simon Pilgrim
5809b919f1 [SelectionDAG] Add support for vector demandedelts in UDIV opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286576 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11 10:47:24 +00:00
Simon Pilgrim
c5bdc92c0d [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:41:49 +00:00
Simon Pilgrim
7a98835990 [SelectionDAG] Add support for splatted vectors in SUB opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:57:42 +00:00
Simon Pilgrim
9ae088bf72 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:43:52 +00:00
Simon Pilgrim
e84f684084 [SelectionDAG] Add support for vector demandedelts in MUL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:42 +00:00
Simon Pilgrim
2eb0b40c6a [SelectionDAG] Add support for vector demandedelts in SRA opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286461 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:05:09 +00:00
Simon Pilgrim
f524b350db [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:52:42 +00:00
Simon Pilgrim
dc0f6aec55 [SelectionDAG] Add support for vector demandedelts in XOR opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286075 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-06 16:49:19 +00:00
Simon Pilgrim
67ef8244cb [SelectionDAG] Add support for vector demandedelts in OR opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286071 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-06 16:29:09 +00:00
Simon Pilgrim
6960085571 Use !operator to test if APInt is zero/non-zero. NFCI.
Avoids APInt construction and slower comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285822 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-02 15:41:15 +00:00
Simon Pilgrim
6722cc3c8a [DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits
Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements.

This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.

The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used.

I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course.

DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit.

This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander!

Differential Revision: https://reviews.llvm.org/D25691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285494 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-29 11:29:39 +00:00