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intrinsics
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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loop-idiom
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[Hexagon] Add Hexagon-specific loop idiom recognition pass
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2017-01-26 21:41:10 +00:00 |
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vect
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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absaddr-store.ll
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absimm.ll
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adde.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh-sext-trunc.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh-shifted.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addh.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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addr-calc-opt.ll
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addrmode-indoff.ll
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alu64.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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always-ext.ll
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anti-dep-partial.mir
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Move .mir tests to appropriate directories
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2016-12-09 19:08:15 +00:00 |
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args.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ashift-left-right.ll
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Atomics.ll
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avoid-predspill-calleesaved.ll
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avoid-predspill.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-eval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-extractu-half.ll
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bit-gen-rseq.ll
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bit-loop-rc-mismatch.ll
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bit-loop.ll
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bit-phi.ll
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bit-rie.ll
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bit-skip-byval.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bit-validate-reg.ll
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bit-visit-flowq.ll
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bitconvert-vector.ll
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block-addr.ll
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block-ranges-nodef.ll
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branch-non-mbb.ll
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branchfolder-keep-impdef.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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BranchPredict.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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brev_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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brev_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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bugAsmHWloop.ll
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build-vector-shuffle.ll
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builtin-prefetch-offset.ll
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builtin-prefetch.ll
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calling-conv-2.ll
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callr-dep-edge.ll
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cext-check.ll
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cext-valid-packet1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfi-late.ll
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cfi-offset.ll
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checktabs.ll
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circ_ld.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_ldd_bug.ll
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circ_ldw.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ_st.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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circ-load-isel.ll
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clr_set_toggle.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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cmpb_pred.ll
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cmpb-eq.ll
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combine_ir.ll
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combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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common-gep-basic.ll
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common-gep-icm.ll
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compound.ll
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const64.ll
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const-pool-tf.ll
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constp-clb.ll
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constp-combine-neg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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constp-ctb.ll
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constp-extract.ll
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constp-physreg.ll
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constp-rewrite-branches.ll
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constp-rseq.ll
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constp-vsplat.ll
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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copy-to-combine-dbg.ll
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csr-func-usedef.ll
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ctlz-cttz-ctpop.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ctor.ll
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dadd.ll
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dead-store-stack.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
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early-if-phi-i1.ll
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early-if-spare.ll
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early-if-vecpi.ll
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early-if.ll
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eh_return.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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eliminate-pred-spill.ll
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expand-condsets-basic.ll
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expand-condsets-def-undef.mir
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[Hexagon] Separate Hexagon subreg indices for different register classes
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2016-11-09 16:19:08 +00:00 |
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expand-condsets-extend.ll
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expand-condsets-impuse.mir
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[Hexagon] Maintain kill flags through splitting in expand-condsets
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2016-10-28 15:50:22 +00:00 |
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expand-condsets-pred-undef.ll
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expand-condsets-rm-reg.mir
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[Hexagon] Remove registers coalesced in expand-condsets from live intervals
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2016-11-02 17:59:54 +00:00 |
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expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir
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[Hexagon] Don't expand mux instructions with both sources identical
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2016-10-31 15:45:09 +00:00 |
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expand-condsets-undef2.ll
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expand-condsets-undef.ll
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expand-vstorerw-undef2.ll
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[Hexagon] Remove dead defs from the live set when expanding wstores
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2017-01-18 23:11:40 +00:00 |
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expand-vstorerw-undef.ll
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[Hexagon] Handle spills of partially defined double vector registers
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2016-10-21 16:38:29 +00:00 |
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extload-combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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extract-basic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fadd.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fcmp.ll
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find-loop-instr.ll
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[Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions
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2017-02-02 19:36:37 +00:00 |
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fixed-spill-mutable.ll
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float-amode.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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float.ll
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floatconvert-ieee-rnd-near.ll
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fminmax.ll
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fmul.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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frame-offset-overflow.ll
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frame.ll
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fsel.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fsub.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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fusedandshift.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
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2017-02-06 23:18:57 +00:00 |
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hwloop1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop3.ll
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hwloop4.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop5.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-cleanup.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
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hwloop-le.ll
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hwloop-loop1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-wrap2.ll
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hwloop-wrap.ll
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i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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idxload-with-zero-offset.ll
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ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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ifcvt-edge-weight.ll
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ifcvt-impuse-livein.mir
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ifcvt-live-subreg.mir
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indirect-br.ll
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inline-asm-hexagon.ll
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inline-asm-i1.ll
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inline-asm-qv.ll
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insert4.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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insert-basic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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is-legal-void.ll
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lit.local.cfg
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livephysregs-lane-masks2.mir
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Handle non-~0 lane masks on live-in registers in LivePhysRegs
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2016-10-28 20:06:37 +00:00 |
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livephysregs-lane-masks.mir
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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long-calls.ll
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loop-prefetch.ll
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lower-extract-subvector.ll
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macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
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memcpy-likely-aligned.ll
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memops1.ll
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memops2.ll
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memops3.ll
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memops-stack.ll
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memops.ll
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned_double_vector_store_not_fast.ll
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misaligned-access.ll
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misched-top-rptracker-sync.ll
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mpy.ll
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mulhs.ll
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mux-basic.ll
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newvaluejump2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvaluejump.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvalueSameReg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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newvaluestore.ll
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NVJumpCmp.ll
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opt-addr-mode.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-fabs.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-fneg.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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opt-spill-volatile.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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packetize_cond_inst.ll
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packetize-cfi-location.ll
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packetize-return-arg.ll
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packetize-tailcall-arg.ll
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peephole-kill-flags.ll
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peephole-op-swap.ll
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pic-jumptables.ll
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pic-local.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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pic-regusage.ll
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pic-simple.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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pic-static.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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post-inc-aa-metadata.ll
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post-ra-kill-update.mir
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postinc-load.ll
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postinc-offset.ll
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postinc-store.ll
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pred-absolute-store.ll
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pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
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predicate-logical.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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predicate-rcmp.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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propagate-vcombine.ll
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rdf-copy-undef2.ll
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rdf-copy.ll
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rdf-dead-loop.ll
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rdf-extra-livein.ll
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rdf-filter-defs.ll
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rdf-ignore-undef.ll
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rdf-inline-asm-fixed.ll
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rdf-inline-asm.ll
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rdf-multiple-phis-up.ll
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rdf-phi-shadows.ll
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rdf-phi-up.ll
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[RDF] Switch RefMap in liveness calculation to use lane masks
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2016-10-19 16:30:56 +00:00 |
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rdf-reset-kills.ll
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reg-scavengebug-3.ll
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reg-scavenger-valid-slot.ll
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regalloc-bad-undef.mir
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[Hexagon] Separate Hexagon subreg indices for different register classes
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2016-11-09 16:19:08 +00:00 |
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regalloc-block-overlap.ll
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Treat segment [B, E) as not overlapping block with boundaries [A, B)
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2017-01-18 23:12:19 +00:00 |
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relax.ll
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remove_lsr.ll
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remove-endloop.ll
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restore-single-reg.ll
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ret-struct-by-val.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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runtime-stkchk.ll
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sdata-array.ll
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sdata-basic.ll
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sdr-basic.ll
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sdr-shr32.ll
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section_7275.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
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2017-02-06 23:18:57 +00:00 |
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select-instr-align.ll
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sf-min-max.ll
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sffms.ll
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shrink-frame-basic.ll
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signed_immediates.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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simple_addend.ll
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simpletailcall.ll
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split-const32-const64.ll
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stack-align1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-align2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-alloca1.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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stack-alloca2.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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static.ll
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[Hexagon] Adding gp+ to the syntax of gp-relative instructions
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2017-02-06 23:18:57 +00:00 |
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store-shift.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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store-widen-aliased-load.ll
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store-widen-negv2.ll
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store-widen-negv.ll
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store-widen.ll
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storerd-io-over-rr.ll
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storerinewabs.ll
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struct_args_large.ll
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struct_args.ll
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sube.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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subi-asl.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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SUnit-boundary-prob.ll
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swp-const-tc.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-dag-phi.ll
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swp-epilog-phi10.ll
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Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
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2016-12-22 18:49:55 +00:00 |
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swp-epilog-reuse-1.ll
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swp-epilog-reuse.ll
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swp-matmul-bitext.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-max.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-multi-loops.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-prolog-phi4.ll
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Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
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2016-12-22 18:49:55 +00:00 |
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swp-stages4.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-stages5.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-vect-dotprod.ll
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swp-vmult.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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swp-vsum.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
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tail-dup-subreg-abort.ll
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tail-dup-subreg-map.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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tailcall_fastcc_ccc.ll
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tfr-to-combine.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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tls_pic.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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tls_static.ll
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two-crash.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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union-1.ll
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usr-ovf-dep.ll
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v6vec-vprint.ll
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v60-cur.ll
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v60-vsel1.ll
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[Hexagon] Do not expand ISD::SELECT for HVX vectors
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2016-10-27 14:30:16 +00:00 |
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v60Intrins.ll
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v60small.ll
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v60Vasr.ll
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vaddh.ll
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[Hexagon] Replace instruction definitions with auto-generated ones
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2017-02-10 15:33:13 +00:00 |
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validate-offset.ll
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vassign-to-combine.ll
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vdmpy-halide-test.ll
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vec-pred-spill1.ll
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vector-align.ll
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vector-ext-load.ll
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vload-postinc-sel.ll
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vmpa-halide-test.ll
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vpack_eo.ll
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vselect-pseudo.ll
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vsplat-isel.ll
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zextloadi1.ll
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