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llvm/lib/Target/AMDGPU
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Matt Arsenault 078c435803 AMDGPU: Return correct type during argument lowering 
The type needs to be casted back to the original argument type.
Fixes an assert that for some reason is only run when
using -debug.

Includes an additional combine to avoid test regressions
from having conversions mixed with multiple Assert[SZ]ext
nodes. On subtargets where i16 is legal, this was producing an i32
register with an i16 AssertZExt, truncated to i16 with another i8
AssertZExt.

t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: i16 = truncate t2
t5: i16 = AssertZext t3, ValueType:ch:i8
t6: i8 = truncate t5
t7: i32 = zero_extend t6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308082 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-15 05:52:59 +00:00
..
AsmParser [AMDGPU] Assembler: refactor convert methods (VOP3 and MIMG) 2017-07-07 15:21:52 +00:00
Disassembler [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructions 2017-06-27 15:02:23 +00:00
InstPrinter [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
MCTargetDesc Fully fix the movw/movt addend. 2017-07-11 23:18:25 +00:00
TargetInfo fix trivial typos; NFC 2017-07-02 03:24:54 +00:00
Utils Revert "AMDGPU: Do not test for SI in getIsaVersion" 2017-07-11 17:57:41 +00:00
AMDGPU.h AMDGPU: Annotate call graph with used features 2017-07-13 21:43:42 +00:00
AMDGPU.td [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructions 2017-06-27 15:02:23 +00:00
AMDGPUAliasAnalysis.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUAliasAnalysis.h AMDGPU/R600: Fix amdgpu alias analysis pass. 2017-03-31 19:26:23 +00:00
AMDGPUAlwaysInlinePass.cpp [AMDGPU] Testing commit access only, no real change 2017-06-15 23:02:55 +00:00
AMDGPUAnnotateKernelFeatures.cpp [AMDGPU] Throw away more dead code. NFCI. 2017-07-14 21:20:29 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU: Fix converting unanalyzable global loads to SMRD 2017-07-12 23:06:18 +00:00
AMDGPUAsmPrinter.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AMDGPUAsmPrinter.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUCallingConv.td AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
AMDGPUCallLowering.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUCallLowering.h AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
AMDGPUCodeGenPrepare.cpp [AMDGPU] Always use rcp + mul with fast math 2017-07-06 20:34:21 +00:00
AMDGPUFrameLowering.cpp [AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets for SI 2017-03-10 19:39:07 +00:00
AMDGPUFrameLowering.h [AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets for SI 2017-03-10 19:39:07 +00:00
AMDGPUGenRegisterBankInfo.def Re-commit AMDGPU/GlobalISel: Add support for simple shaders 2017-01-30 21:56:46 +00:00
AMDGPUInstrInfo.cpp [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions 2017-06-21 08:53:38 +00:00
AMDGPUInstrInfo.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUInstrInfo.td [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setcc 2017-06-21 22:05:06 +00:00
AMDGPUInstructions.td [AMDGPU][MC] Added check for truncation of SOPK imm operand 2017-04-26 15:34:19 +00:00
AMDGPUInstructionSelector.cpp AMDGPU: Start adding offset fields to flat instructions 2017-06-12 15:55:58 +00:00
AMDGPUInstructionSelector.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUIntrinsicInfo.cpp Rename AttributeSet to AttributeList 2017-03-21 16:57:19 +00:00
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td AMDGPU: Remove legacy bfe intrinsics 2017-04-03 18:08:08 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU: Start selecting flat instruction offsets 2017-06-12 16:53:51 +00:00
AMDGPUISelLowering.cpp AMDGPU: Return correct type during argument lowering 2017-07-15 05:52:59 +00:00
AMDGPUISelLowering.h AMDGPU: Return correct type during argument lowering 2017-07-15 05:52:59 +00:00
AMDGPULegalizerInfo.cpp AMDGPU/GlobalISel: Mark 32-bit G_SHL as legal 2017-06-26 15:56:52 +00:00
AMDGPULegalizerInfo.h Re-commit AMDGPU/GlobalISel: Add support for simple shaders 2017-01-30 21:56:46 +00:00
AMDGPULowerIntrinsics.cpp Extend memcpy expansion in Transform/Utils to handle wider operand types. 2017-07-07 02:00:06 +00:00
AMDGPUMachineCFGStructurizer.cpp fix trivial typos, NFC 2017-06-27 10:35:37 +00:00
AMDGPUMachineFunction.cpp AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
AMDGPUMachineFunction.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUMacroFusion.cpp AMDGPU: Add macro fusion schedule DAG mutation 2017-07-06 20:57:05 +00:00
AMDGPUMacroFusion.h AMDGPU: Add macro fusion schedule DAG mutation 2017-07-06 20:57:05 +00:00
AMDGPUMCInstLower.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPUMCInstLower.h
AMDGPUOpenCLImageTypeLoweringPass.cpp
AMDGPUPromoteAlloca.cpp [AMDGPU] Fix for issue in alloca to vector promotion pass 2017-06-09 14:16:22 +00:00
AMDGPUPTNote.h [AMDGPU] Restructure code object metadata creation 2017-03-22 22:32:22 +00:00
AMDGPURegAsmNames.inc.cpp AMDGPU: Work around build special casing .inc files 2017-06-08 19:25:21 +00:00
AMDGPURegisterBankInfo.cpp [RegisterBankInfo] Uniquely allocate instruction mapping. 2017-05-05 22:48:22 +00:00
AMDGPURegisterBankInfo.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPURegisterBanks.td Re-commit AMDGPU/GlobalISel: Add support for simple shaders 2017-01-30 21:56:46 +00:00
AMDGPURegisterInfo.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
AMDGPURegisterInfo.h AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI. 2017-07-07 10:18:57 +00:00
AMDGPUSubtarget.h [AMDGPU] fcaninicalize optimization for GFX9+ 2017-07-13 23:59:15 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Add macro fusion schedule DAG mutation 2017-07-06 20:57:05 +00:00
AMDGPUTargetMachine.h TargetMachine: Indicate whether machine verifier passes. 2017-05-31 18:41:23 +00:00
AMDGPUTargetObjectFile.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AMDGPUTargetObjectFile.h [AMDGPU] Get address space mapping by target triple environment 2017-03-27 14:04:01 +00:00
AMDGPUTargetTransformInfo.cpp [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI. 2017-06-28 15:53:17 +00:00
AMDGPUTargetTransformInfo.h [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI. 2017-06-28 15:53:17 +00:00
AMDGPUUnifyDivergentExitNodes.cpp AMDGPU: Unify divergent function exits. 2017-03-24 19:52:05 +00:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp Remove unused functions. Remove static qualifier from functions in header files. NFC. 2017-04-11 14:55:32 +00:00
AMDKernelCodeT.h
BUFInstructions.td [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
CaymanInstructions.td
CIInstructions.td
CMakeLists.txt AMDGPU: Add macro fusion schedule DAG mutation 2017-07-06 20:57:05 +00:00
DSInstructions.td [AMDGPU][MC] New syntax for ds_swizzle_b32 offset 2017-05-31 16:26:47 +00:00
EvergreenInstructions.td AMDGPU: Fix unnecessary ands when packing f16 vectors 2017-03-15 19:04:26 +00:00
FLATInstructions.td AMDGPU: Start adding global_* instructions 2017-06-20 19:54:14 +00:00
GCNHazardRecognizer.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
GCNHazardRecognizer.h AMDGPU: Fix broken condition in hazard recognizer 2017-03-17 21:36:28 +00:00
GCNIterativeScheduler.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
GCNIterativeScheduler.h [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler 2017-03-21 13:15:46 +00:00
GCNMinRegStrategy.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
GCNRegPressure.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
GCNRegPressure.h [AMDGPU] Fix incorrect register usage tracking in GCNUpwardTracker 2017-05-22 13:09:40 +00:00
GCNSchedStrategy.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
GCNSchedStrategy.h fix typos in comments and error messges; NFC 2017-07-13 06:48:39 +00:00
LLVMBuild.txt
MIMGInstructions.td [AMDGPU] Fix latency of MIMG instructions 2017-07-04 14:43:38 +00:00
Processors.td AMDGPU: Whitespace fixes 2017-06-26 03:01:36 +00:00
R600ClauseMergePass.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
R600ControlFlowFinalizer.cpp [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI. 2017-07-07 10:18:57 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
R600ExpandSpecialInstrs.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
R600FrameLowering.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
R600FrameLowering.h [AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets for SI 2017-03-10 19:39:07 +00:00
R600InstrFormats.td
R600InstrInfo.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
R600InstrInfo.h Cyle -> Cycle; NFCI 2017-03-15 15:37:42 +00:00
R600Instructions.td [AMDGPU] Get address space mapping by target triple environment 2017-03-27 14:04:01 +00:00
R600Intrinsics.td AMDGPU: Make intrinsics speculatable 2017-05-02 16:57:44 +00:00
R600ISelLowering.cpp Add DAG argument to canMergeStoresTo NFC. 2017-07-10 20:25:54 +00:00
R600ISelLowering.h Add DAG argument to canMergeStoresTo NFC. 2017-07-10 20:25:54 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
R600Packetizer.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
R600RegisterInfo.cpp AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
R600RegisterInfo.h AMDGPU: Start defining a calling convention 2017-05-17 21:56:25 +00:00
R600RegisterInfo.td [AMDGPU] Add INDIRECT_BASE_ADDR to R600_Reg32 class (PR33045) 2017-05-23 21:27:15 +00:00
R600Schedule.td
R700Instructions.td
SIAnnotateControlFlow.cpp Remove now useless trailing nullptr in StructType::get 2017-05-11 08:46:02 +00:00
SIDebuggerInsertNops.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SIDefines.h [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions 2017-06-21 08:53:38 +00:00
SIFixControlFlowLiveIntervals.cpp
SIFixSGPRCopies.cpp [AMDGPU] Eliminate SGPR to VGPR copy when possible 2017-06-20 18:32:42 +00:00
SIFixVGPRCopies.cpp
SIFoldOperands.cpp [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI. 2017-07-07 10:18:57 +00:00
SIFrameLowering.cpp AMDGPU: Setup SP/FP in callee function prolog/epilog 2017-06-26 17:53:59 +00:00
SIFrameLowering.h AMDGPU: Setup SP/FP in callee function prolog/epilog 2017-06-26 17:53:59 +00:00
SIInsertSkips.cpp AMDGPU: Rename SI_RETURN 2017-03-21 22:18:10 +00:00
SIInsertWaitcnts.cpp [AMDGPU] Fix uninit'ed var (RevisitLoop) 2017-06-05 19:29:01 +00:00
SIInsertWaits.cpp AMDGPU: Make auto waitcnt before barrier a feature 2017-06-02 17:40:26 +00:00
SIInstrFormats.td [AMDGPU][MC] Fixed bugs in export instruction 2017-05-19 13:36:09 +00:00
SIInstrInfo.cpp [AMDGPU] Do not insert an instruction into worklist twice in movetovalu 2017-07-14 17:56:55 +00:00
SIInstrInfo.h [AMDGPU] Do not insert an instruction into worklist twice in movetovalu 2017-07-14 17:56:55 +00:00
SIInstrInfo.td [AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX* 2017-07-07 14:29:06 +00:00
SIInstructions.td [AMDGPU] Add pattern for v_alignbit_b32 with immediate 2017-06-28 02:52:39 +00:00
SIIntrinsics.td AMDGPU: Remove legacy export intrinsic 2017-04-04 16:34:39 +00:00
SIISelLowering.cpp AMDGPU: Return correct type during argument lowering 2017-07-15 05:52:59 +00:00
SIISelLowering.h Add DAG argument to canMergeStoresTo NFC. 2017-07-10 20:25:54 +00:00
SILoadStoreOptimizer.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
SILowerControlFlow.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SILowerI1Copies.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SIMachineFunctionInfo.cpp AMDGPU: Detect kernarg segment pointer 2017-07-14 00:11:13 +00:00
SIMachineFunctionInfo.h AMDGPU: Partially fix implicit.buffer.ptr intrinsic handling 2017-06-26 03:01:31 +00:00
SIMachineScheduler.cpp [CodeGen] Rename DEBUG_TYPE to match passnames 2017-07-11 22:08:28 +00:00
SIMachineScheduler.h [AMDGPU] Update SI scheduler colorHighLatenciesGroups 2017-03-28 07:19:48 +00:00
SIOptimizeExecMasking.cpp
SIPeepholeSDWA.cpp [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructions 2017-06-27 15:02:23 +00:00
SIRegisterInfo.cpp AMDGPU: Partially fix implicit.buffer.ptr intrinsic handling 2017-06-26 03:01:31 +00:00
SIRegisterInfo.h AMDGPU: Partially fix implicit.buffer.ptr intrinsic handling 2017-06-26 03:01:31 +00:00
SIRegisterInfo.td AMDGPU: Fix not including v2i16/v2f16 in register class 2017-03-21 16:42:50 +00:00
SISchedule.td
SIShrinkInstructions.cpp AMDGPU: Allow SIShrinkInstructions to fold FrameIndexes 2017-07-10 20:04:35 +00:00
SIWholeQuadMode.cpp
SMInstructions.td AMDGPUAnnotateUniformValue should always treat volatile loads as divergent 2017-06-02 15:25:52 +00:00
SOPInstructions.td Resubmit r303859 with test fixed. 2017-05-26 20:38:26 +00:00
VIInstrFormats.td
VIInstructions.td
VOP1Instructions.td [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions 2017-06-21 08:53:38 +00:00
VOP2Instructions.td [AMDGPU] SDWA: remove support for VOP2 instructions that have only 64-bit encoding 2017-06-22 12:42:14 +00:00
VOP3Instructions.td [AMDGPU] Add intrinsics for alignbit and alignbyte instructions 2017-06-09 19:03:00 +00:00
VOP3PInstructions.td [AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX* 2017-07-07 14:29:06 +00:00
VOPCInstructions.td [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions 2017-06-21 08:53:38 +00:00
VOPInstructions.td [AMDGPU] Assembler: refactor convert methods (VOP3 and MIMG) 2017-07-07 15:21:52 +00:00