mirror of
https://github.com/ares-emulator/ares.git
synced 2026-11-07 17:01:59 -10:00
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No files matched your search
@@ -1,8 +0,0 @@
|
||||
# yaml-language-server: $schema=https://raw.githubusercontent.com/BlankSpruce/gersemi/master/gersemi/configuration.schema.json
|
||||
|
||||
definitions: [ares/CMakeLists.txt]
|
||||
line_length: 120
|
||||
indent: 2
|
||||
list_expansion: favour-inlining
|
||||
unsafe: false
|
||||
warn_about_unknown_commands: false
|
||||
@@ -1,2 +0,0 @@
|
||||
# When archiving, export a version file containing tag/commit information
|
||||
cmake/common/.archive-version.json export-subst
|
||||
@@ -1,32 +0,0 @@
|
||||
# dummy GitHub target used to enable editing of GitHub files within generated IDE projects
|
||||
|
||||
add_library(.github INTERFACE)
|
||||
|
||||
set(.github_sources
|
||||
ISSUE_TEMPLATE/bug_report.md
|
||||
ISSUE_TEMPLATE/feature_request.md
|
||||
ISSUE_TEMPLATE/game-issue-report.md
|
||||
scripts/build_macos.sh
|
||||
scripts/build_sdl.sh
|
||||
scripts/build_ubuntu.sh
|
||||
scripts/build_windows.sh
|
||||
scripts/package_artifacts.sh
|
||||
workflows/build-aux.yml
|
||||
workflows/build.yml
|
||||
workflows/pr.yml
|
||||
workflows/push.yml
|
||||
workflows/release.yml
|
||||
)
|
||||
|
||||
target_sources(
|
||||
.github
|
||||
PRIVATE
|
||||
${.github_sources}
|
||||
../.gitignore
|
||||
../.gitattributes
|
||||
../README.md
|
||||
../LICENSE
|
||||
)
|
||||
|
||||
source_group(TREE ${CMAKE_CURRENT_SOURCE_DIR} FILES ${.github_sources})
|
||||
|
||||
@@ -1,27 +0,0 @@
|
||||
---
|
||||
name: Bug report
|
||||
about: Report a bug *not* relating to game compatibility
|
||||
title: ''
|
||||
labels: ''
|
||||
assignees: ''
|
||||
|
||||
---
|
||||
|
||||
**Describe the bug**
|
||||
A clear and concise description of what the bug is.
|
||||
|
||||
**To Reproduce**
|
||||
Steps to reproduce the behavior:
|
||||
1. Go to '...'
|
||||
2. Click on '....'
|
||||
3. Scroll down to '....'
|
||||
4. See error
|
||||
|
||||
**Expected behavior**
|
||||
A clear and concise description of what you expected to happen.
|
||||
|
||||
**Screenshots**
|
||||
If applicable, add screenshots to help explain your problem.
|
||||
|
||||
**Additional context**
|
||||
Add any other context about the problem here.
|
||||
@@ -1,20 +0,0 @@
|
||||
---
|
||||
name: Feature request
|
||||
about: Suggest an idea for this project
|
||||
title: ''
|
||||
labels: ''
|
||||
assignees: ''
|
||||
|
||||
---
|
||||
|
||||
**Is your feature request related to a problem? Please describe.**
|
||||
A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
|
||||
|
||||
**Describe the solution you'd like**
|
||||
A clear and concise description of what you want to happen.
|
||||
|
||||
**Describe alternatives you've considered**
|
||||
A clear and concise description of any alternative solutions or features you've considered.
|
||||
|
||||
**Additional context**
|
||||
Add any other context or screenshots about the feature request here.
|
||||
@@ -1,22 +0,0 @@
|
||||
---
|
||||
name: Game Issue Report
|
||||
about: Report an issue running a specific game in ares
|
||||
title: "[system] Game"
|
||||
labels: bug
|
||||
assignees: ''
|
||||
|
||||
---
|
||||
|
||||
Before submitting an issue, please use the search to make sure an issue doesn't already exist, you should also make sure your rom is not a bad dump, by comparing against the hashes in the No-Intro (Cartridges) or Redump (CD-ROM) databases.
|
||||
|
||||
**Describe the issue**
|
||||
A clear and concise description of what the bug is.
|
||||
|
||||
**Rom Information**
|
||||
Specify the impacted rom filename and any associated hashes (sha256 preferred);.
|
||||
The easiest way to do this is to open the game in ares, and go to "Tools -> Manifest" and copy/paste the contents.
|
||||
|
||||
```
|
||||
file: Some Game (REGION).ext
|
||||
sha256: <hash>
|
||||
```
|
||||
@@ -1,26 +0,0 @@
|
||||
#!/usr/bin/env sh
|
||||
set -euo pipefail
|
||||
|
||||
# configure
|
||||
cmake --preset $TARGET_PRESET
|
||||
|
||||
# change into the build directory
|
||||
pushd build
|
||||
|
||||
# build; pipe output to render warnings neatly
|
||||
xcodebuild -configuration RelWithDebInfo \
|
||||
DEBUG_INFORMATION_FORMAT="dwarf-with-dsym" \
|
||||
-parallelizeTargets \
|
||||
2>&1 | xcbeautify --renderer github-actions
|
||||
|
||||
popd
|
||||
|
||||
# package debug symbols
|
||||
|
||||
# move dependency dSYMs to build output directory
|
||||
ditto .deps/ares-deps-macos-universal/lib/*.dSYM build/desktop-ui/RelWithDebInfo
|
||||
|
||||
mkdir build/dsyms
|
||||
|
||||
# ares.app.dSYM already exists alongside ares.app; package it with the rest
|
||||
mv build/desktop-ui/RelWithDebInfo/*.dSYM build/dSYMs/
|
||||
@@ -1,14 +0,0 @@
|
||||
#!/usr/bin/env bash
|
||||
set -euo pipefail
|
||||
|
||||
# clone the SDL repository
|
||||
git clone https://github.com/libsdl-org/SDL.git
|
||||
# change into the SDL directory
|
||||
pushd SDL
|
||||
mkdir build
|
||||
# build SDL
|
||||
cmake -S . -B build -DCMAKE_BUILD_TYPE=Release
|
||||
cmake --build build --config Release
|
||||
# install SDL libs and include files to /usr/local
|
||||
sudo cmake --install build --prefix=/usr/local
|
||||
popd
|
||||
@@ -1,12 +0,0 @@
|
||||
#!/usr/bin/env bash
|
||||
set -euo pipefail
|
||||
|
||||
# configure
|
||||
cmake --preset $TARGET_PRESET
|
||||
|
||||
# change into the build directory
|
||||
pushd build
|
||||
|
||||
ninja
|
||||
|
||||
popd
|
||||
@@ -1,24 +0,0 @@
|
||||
#!/usr/bin/env sh
|
||||
set -euo pipefail
|
||||
|
||||
if [ "$CROSS_COMPILE" = true ]; then
|
||||
cmake --preset $NATIVE_PRESET -B build_native
|
||||
pushd build_native
|
||||
# build sourcery natively so it may be invoked during cross-compilation
|
||||
cmake --build . --target sourcery --config RelWithDebInfo
|
||||
popd
|
||||
fi
|
||||
|
||||
cmake --preset $TARGET_PRESET
|
||||
pushd build
|
||||
cmake --build . --config RelWithDebInfo
|
||||
|
||||
if [ "$CROSS_COMPILE" = true ] || [ "$ARES_PLATFORM_NAME" = "windows-arm64" ]; then
|
||||
cp ../.deps/ares-deps-windows-arm64/lib/*.pdb desktop-ui/rundir/
|
||||
else
|
||||
cp ../.deps/ares-deps-windows-x64/lib/*.pdb desktop-ui/rundir/
|
||||
fi
|
||||
|
||||
mkdir PDBs
|
||||
mv desktop-ui/rundir/*.pdb PDBs/
|
||||
popd
|
||||
@@ -1,49 +0,0 @@
|
||||
set -eu
|
||||
case ${GITHUB_REF} in
|
||||
refs/tags/*) suffix="-${GITHUB_REF#refs/tags/}" ;;
|
||||
refs/heads/master) suffix="-nightly" ;;
|
||||
*) suffix="" ;;
|
||||
esac
|
||||
|
||||
bindir="${GITHUB_WORKSPACE}/bin"
|
||||
|
||||
# Hack: Workaround for GitHub artifacts losing attributes.
|
||||
chmod +x ${bindir}/ares-macos-universal/ares.app/Contents/MacOS/ares
|
||||
|
||||
for package in macos-universal
|
||||
do
|
||||
mkdir "${package}"
|
||||
cd "${package}"
|
||||
|
||||
# Package ares.
|
||||
outdir=ares${suffix}
|
||||
mkdir ${outdir}
|
||||
mkdir ${outdir}-dSYMs
|
||||
cp -a ${bindir}/ares-${package}-dSYMs/*.dSYM ${outdir}-dSYMs
|
||||
cp -a ${bindir}/ares-${package}/*.app ${outdir}
|
||||
zip -r -y ../ares-${package}.zip ${outdir}
|
||||
zip -r -y ../ares-${package}-dSYMs.zip ${outdir}-dSYMs
|
||||
cd -
|
||||
done
|
||||
|
||||
for package in windows-x64 windows-clang-cl-arm64
|
||||
do
|
||||
mkdir "${package}"
|
||||
cd "${package}"
|
||||
|
||||
# Package ares.
|
||||
outdir=ares${suffix}
|
||||
mkdir ${outdir}
|
||||
mkdir ${outdir}-PDBs
|
||||
cp -a ${bindir}/ares-${package}-PDBs/*.pdb ${outdir}-PDBs
|
||||
zip -r ../ares-${package}-PDBs.zip ${outdir}-PDBs
|
||||
rm -rf ${bindir}/ares-${package}/PDBs
|
||||
cp -a ${bindir}/ares-${package}/* ${outdir}
|
||||
zip -r ../ares-${package}.zip ${outdir}
|
||||
cd -
|
||||
done
|
||||
|
||||
# Package the source archive
|
||||
pushd src
|
||||
git archive --format=tar.gz -o ../ares-source.tar.gz HEAD
|
||||
popd
|
||||
@@ -1,142 +0,0 @@
|
||||
name: Build (Auxiliary)
|
||||
on:
|
||||
workflow_call
|
||||
jobs:
|
||||
build:
|
||||
strategy:
|
||||
fail-fast: false
|
||||
matrix:
|
||||
program:
|
||||
- ares
|
||||
config:
|
||||
- RelWithDebInfo
|
||||
platform:
|
||||
- name: windows-x64-gcc
|
||||
os: windows-latest
|
||||
shell: 'msys2 {0}'
|
||||
msystem: mingw64
|
||||
install: make git cmake ccache ninja mingw-w64-x86_64-toolchain
|
||||
target-cmake-preset: windows-ci-mingw-native
|
||||
- name: windows-mingw-clang64-x64
|
||||
os: windows-latest
|
||||
compiler: clang++
|
||||
shell: 'msys2 {0}'
|
||||
msystem: clang64
|
||||
install: make git cmake ccache ninja mingw-w64-clang-x86_64-clang
|
||||
target-cmake-preset: windows-ci-mingw-native
|
||||
- name: windows-arm64
|
||||
os: windows-11-arm
|
||||
compiler: clang++
|
||||
shell: 'msys2 {0}'
|
||||
msystem: clangarm64
|
||||
install: mingw-w64-clang-aarch64-make git mingw-w64-clang-aarch64-cmake mingw-w64-clang-aarch64-ccache mingw-w64-clang-aarch64-ninja mingw-w64-clang-aarch64-clang
|
||||
target-cmake-preset: windows-ci-mingw-native
|
||||
- name: windows-msvc-x64
|
||||
os: windows-latest
|
||||
windres: rc
|
||||
shell: bash
|
||||
target-cmake-preset: windows-ci-msvc-native
|
||||
- name: windows-msvc-arm64
|
||||
os: windows-latest
|
||||
windres: rc
|
||||
shell: bash
|
||||
target-cmake-preset: windows-ci-msvc-cross
|
||||
native-cmake-preset: windows-ci-msvc-native
|
||||
- name: ubuntu-gcc-x64
|
||||
os: ubuntu-24.04
|
||||
shell: bash
|
||||
target-cmake-preset: ubuntu-ci
|
||||
- name: ubuntu-gcc-arm64
|
||||
os: ubuntu-24.04-arm
|
||||
shell: bash
|
||||
target-cmake-preset: ubuntu-ci
|
||||
- name: ubuntu-clang-x64
|
||||
os: ubuntu-24.04
|
||||
shell: bash
|
||||
target-cmake-preset: ubuntu-ci-clang
|
||||
- name: ubuntu-clang-arm64
|
||||
os: ubuntu-24.04-arm
|
||||
shell: bash
|
||||
target-cmake-preset: ubuntu-ci-clang
|
||||
- name: ubuntu-gcc-arm64-qt
|
||||
os: ubuntu-24.04-arm
|
||||
shell: bash
|
||||
target-cmake-preset: ubuntu-ci-qt
|
||||
- name: freebsd
|
||||
os: ubuntu-24.04
|
||||
shell: cpa.sh {0}
|
||||
target-cmake-preset: ubuntu-ci-clang
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}
|
||||
runs-on: ${{ matrix.platform.os }}
|
||||
defaults:
|
||||
run:
|
||||
shell: ${{ matrix.platform.shell }}
|
||||
steps:
|
||||
- name: Install MSYS2 Dependencies
|
||||
if: matrix.platform.shell == 'msys2 {0}'
|
||||
uses: msys2/setup-msys2@40677d36a502eb2cf0fb808cc9dec31bf6152638
|
||||
with:
|
||||
msystem: ${{ matrix.platform.msystem }}
|
||||
install: ${{ matrix.platform.install }}
|
||||
- name: Checkout source code
|
||||
uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683
|
||||
with:
|
||||
fetch-tags: true
|
||||
fetch-depth: 0
|
||||
- name: Setup MSYS2 Git Environment
|
||||
if: matrix.platform.shell == 'msys2 {0}'
|
||||
run: |
|
||||
git config core.autocrlf true
|
||||
- name: Install Linux Dependencies
|
||||
if: runner.os == 'Linux' && matrix.platform.name != 'freebsd'
|
||||
run: |
|
||||
sudo apt-get update -y -qq
|
||||
sudo apt-get install cmake ccache ninja-build libsdl2-dev libgtk-3-dev qt6-base-dev
|
||||
- name: Build SDL3
|
||||
if: runner.os == 'Linux' && matrix.platform.name != 'freebsd'
|
||||
run: .github/scripts/build_sdl.sh
|
||||
- name: "Build: Linux"
|
||||
if: runner.os == 'Linux' && matrix.platform.name != 'freebsd'
|
||||
run: .github/scripts/build_ubuntu.sh
|
||||
env:
|
||||
TARGET_PRESET: ${{ matrix.platform.target-cmake-preset }}
|
||||
- name: "Build: Windows"
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
run: .github/scripts/build_windows.sh
|
||||
env:
|
||||
ARES_PLATFORM_NAME: ${{ matrix.platform.name }}
|
||||
CROSS_COMPILE: ${{ matrix.platform.native-cmake-preset != '' }}
|
||||
NATIVE_PRESET: ${{ matrix.platform.native-cmake-preset }}
|
||||
TARGET_PRESET: ${{ matrix.platform.target-cmake-preset }}
|
||||
- name: "Start FreeBSD VM"
|
||||
if: matrix.platform.name == 'freebsd'
|
||||
uses: cross-platform-actions/action@e0b9770014ba65d5e0815f15b74031c3a635f641
|
||||
with:
|
||||
operating_system: freebsd
|
||||
version: '15.1'
|
||||
- name: "Install FreeBSD Dependencies"
|
||||
if: matrix.platform.name == 'freebsd'
|
||||
run: |
|
||||
sudo pkg upgrade -y
|
||||
sudo pkg install -y cmake-core pkgconf ccache ninja gtk3 sdl3 librashader
|
||||
- name: "Build: FreeBSD"
|
||||
if: matrix.platform.name == 'freebsd'
|
||||
env:
|
||||
TARGET_PRESET: ${{ matrix.platform.target-cmake-preset }}
|
||||
shell: cpa.sh {0} --environment-variables TARGET_PRESET
|
||||
run: .github/scripts/build_ubuntu.sh
|
||||
- name: "Compress Build Artifacts (Windows)"
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
run: |
|
||||
tar -cvJf ares-${{ matrix.platform.name }}.tar.xz -C build/desktop-ui/rundir/ .
|
||||
- name: Upload Build
|
||||
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02
|
||||
with:
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}
|
||||
path: ares-${{ matrix.platform.name }}.tar.xz
|
||||
- name: Upload Debug Symbols (Windows)
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02
|
||||
with:
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}-PDBs
|
||||
path: build/PDBs/*
|
||||
@@ -1,132 +0,0 @@
|
||||
name: Build (Primary)
|
||||
on:
|
||||
workflow_call:
|
||||
inputs:
|
||||
codesign:
|
||||
description: Enable codesigning
|
||||
required: false
|
||||
default: false
|
||||
type: boolean
|
||||
official:
|
||||
description: Use official version strings
|
||||
required: true
|
||||
default: true
|
||||
type: boolean
|
||||
jobs:
|
||||
build:
|
||||
strategy:
|
||||
fail-fast: false
|
||||
matrix:
|
||||
program:
|
||||
- ares
|
||||
config:
|
||||
- RelWithDebInfo
|
||||
platform:
|
||||
- name: windows-x64
|
||||
os: windows-latest
|
||||
windres: rc
|
||||
shell: bash
|
||||
target-cmake-preset: windows-ci-cl-native
|
||||
- name: windows-clang-cl-arm64
|
||||
os: windows-latest
|
||||
windres: rc
|
||||
shell: bash
|
||||
target-cmake-preset: windows-ci-cl-cross
|
||||
native-cmake-preset: windows-ci-cl-native
|
||||
- name: macos-universal
|
||||
os: macos-15
|
||||
compiler: clang++
|
||||
shell: sh
|
||||
install: cmake ccache xcbeautify
|
||||
target-cmake-preset: macos-ci-universal
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}
|
||||
runs-on: ${{ matrix.platform.os }}
|
||||
defaults:
|
||||
run:
|
||||
shell: ${{ matrix.platform.shell }}
|
||||
steps:
|
||||
- name: Install MSYS2 Dependencies
|
||||
if: matrix.platform.shell == 'msys2 {0}'
|
||||
uses: msys2/setup-msys2@40677d36a502eb2cf0fb808cc9dec31bf6152638
|
||||
with:
|
||||
msystem: ${{ matrix.platform.msystem }}
|
||||
install: ${{ matrix.platform.install }}
|
||||
- name: "macOS: Import Certificate"
|
||||
if: runner.os == 'macOS' && inputs.codesign
|
||||
uses: apple-actions/import-codesign-certs@65cfbc37e1464d733524cb555b724878f278b8c3
|
||||
continue-on-error: ${{ secrets.MACOS_CERTIFICATE_NAME == '' }}
|
||||
with:
|
||||
p12-file-base64: ${{ secrets.MACOS_CERTIFICATE_DATA }}
|
||||
p12-password: ${{ secrets.MACOS_CERTIFICATE_PASSPHRASE }}
|
||||
- name: Checkout source code
|
||||
uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683
|
||||
with:
|
||||
fetch-tags: true
|
||||
fetch-depth: 0
|
||||
- name: Setup MSYS2 Git Environment
|
||||
if: matrix.platform.shell == 'msys2 {0}'
|
||||
run: |
|
||||
git config core.autocrlf true
|
||||
- name: Install Linux Dependencies
|
||||
if: runner.os == 'Linux'
|
||||
run: |
|
||||
sudo apt-get update -y -qq
|
||||
sudo apt-get install ${{ matrix.platform.install }}
|
||||
- name: Install macOS Dependencies
|
||||
if: runner.os == 'macOS'
|
||||
run: |
|
||||
brew uninstall --ignore-dependencies cmake
|
||||
brew install ${{ matrix.platform.install }}
|
||||
- name: "Build: Windows"
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
run: .github/scripts/build_windows.sh
|
||||
env:
|
||||
ARES_BUILD_OFFICIAL: ${{ inputs.official }}
|
||||
ARES_PLATFORM_NAME: ${{ matrix.platform.name }}
|
||||
CROSS_COMPILE: ${{ matrix.platform.native-cmake-preset != '' }}
|
||||
NATIVE_PRESET: ${{ matrix.platform.native-cmake-preset }}
|
||||
TARGET_PRESET: ${{ matrix.platform.target-cmake-preset }}
|
||||
- name: "Windows: sign"
|
||||
if: runner.os == 'Windows' && inputs.codesign
|
||||
continue-on-error: true
|
||||
uses: DanaBear/code-sign-action@98c79121b376beab8d6a9484f445089db4461bca
|
||||
with:
|
||||
certificate: '${{ secrets.WIN_CERTIFICATE }}'
|
||||
password: '${{ secrets.WIN_PASSWORD }}'
|
||||
certificatesha1: '${{ secrets.WIN_CERTHASH }}'
|
||||
certificatename: '${{ secrets.WIN_CERTNAME }}'
|
||||
folder: 'build/desktop-ui/rundir/'
|
||||
timestampUrl: 'http://timestamp.digicert.com'
|
||||
- name: "Build: macOS"
|
||||
if: runner.os == 'macOS'
|
||||
run: .github/scripts/build_macos.sh
|
||||
env:
|
||||
ARES_BUILD_OFFICIAL: ${{ inputs.official }}
|
||||
TARGET_PRESET: ${{ matrix.platform.target-cmake-preset }}
|
||||
MACOS_CERTIFICATE_NAME: ${{ secrets.MACOS_CERTIFICATE_NAME }}
|
||||
MACOS_NOTARIZATION_TEAMID: ${{ secrets.MACOS_NOTARIZATION_TEAMID }}
|
||||
- name: "Compress Build Artifact (macOS)"
|
||||
if: runner.os == 'macOS'
|
||||
run: |
|
||||
tar -cvJf ares-${{ matrix.platform.name }}.tar.xz -C build/desktop-ui/RelWithDebInfo/ .
|
||||
- name: "Compress Build Artifacts (Windows)"
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
run: |
|
||||
tar -cvJf ares-${{ matrix.platform.name }}.tar.xz -C build/desktop-ui/rundir/ .
|
||||
- name: Upload Build
|
||||
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02
|
||||
with:
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}
|
||||
path: ares-${{ matrix.platform.name }}.tar.xz
|
||||
- name: Upload Debug Symbols (Windows)
|
||||
if: runner.os != 'macOS' && runner.os != 'Linux'
|
||||
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02
|
||||
with:
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}-PDBs
|
||||
path: build/PDBs/*
|
||||
- name: Upload Debug Symbols (macOS)
|
||||
if: runner.os == 'macOS'
|
||||
uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02
|
||||
with:
|
||||
name: ${{ matrix.program }}-${{ matrix.platform.name }}-dSYMs
|
||||
path: build/dSYMs/*
|
||||
@@ -1,23 +0,0 @@
|
||||
name: Pull Request
|
||||
run-name: ${{ github.event.pull_request.title }} PR run
|
||||
on:
|
||||
pull_request:
|
||||
branches: [ '*' ]
|
||||
types: [ opened, synchronize, reopened ]
|
||||
permissions:
|
||||
contents: read
|
||||
concurrency:
|
||||
group: '${{ github.workflow }} @ ${{ github.event.pull_request.head.label || github.head_ref || github.ref }}'
|
||||
cancel-in-progress: true
|
||||
jobs:
|
||||
build-project:
|
||||
name: Build ares (primary)
|
||||
uses: ./.github/workflows/build.yml
|
||||
permissions:
|
||||
contents: read
|
||||
with:
|
||||
official: false
|
||||
build-aux:
|
||||
name: Build ares (auxiliary)
|
||||
uses: ./.github/workflows/build-aux.yml
|
||||
secrets: inherit
|
||||
@@ -1,27 +0,0 @@
|
||||
name: Push
|
||||
on:
|
||||
push
|
||||
concurrency:
|
||||
group: '${{ github.workflow }} @ ${{ github.head_ref || github.ref }}'
|
||||
cancel-in-progress: true
|
||||
permissions:
|
||||
contents: write
|
||||
jobs:
|
||||
build:
|
||||
name: Build ares (primary)
|
||||
uses: ./.github/workflows/build.yml
|
||||
secrets: inherit
|
||||
with:
|
||||
codesign: true
|
||||
official: ${{ github.ref_name == 'master' || github.ref_type == 'tag' }}
|
||||
build-aux:
|
||||
name: Build ares (auxiliary)
|
||||
uses: ./.github/workflows/build-aux.yml
|
||||
secrets: inherit
|
||||
release:
|
||||
name: Release
|
||||
needs: build
|
||||
secrets: inherit
|
||||
uses: ./.github/workflows/release.yml
|
||||
with:
|
||||
notarize: true
|
||||
@@ -1,84 +0,0 @@
|
||||
name: Release
|
||||
permissions:
|
||||
contents: write
|
||||
on:
|
||||
workflow_call:
|
||||
inputs:
|
||||
notarize:
|
||||
description: Notarize build (macOS only)
|
||||
required: false
|
||||
default: true
|
||||
type: boolean
|
||||
jobs:
|
||||
release:
|
||||
if: github.ref == 'refs/heads/master' || startsWith(github.ref, 'refs/tags/')
|
||||
runs-on: macos-latest
|
||||
steps:
|
||||
- uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683
|
||||
with:
|
||||
path: 'src'
|
||||
- name: Download Artifacts
|
||||
uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093
|
||||
with:
|
||||
path: 'bin'
|
||||
- name: "Decompress Build Artifacts"
|
||||
if: runner.os == 'macOS'
|
||||
run: |
|
||||
for package in macos-universal windows-x64 windows-clang-cl-arm64; do
|
||||
pushd bin/ares-${package}
|
||||
tar -xJf ares-${package}.tar.xz
|
||||
rm -f ares-${package}.tar.xz
|
||||
popd
|
||||
done
|
||||
- name: "macOS: notarize"
|
||||
if: inputs.notarize
|
||||
run: |
|
||||
ditto -c -k --keepParent ${{ github.workspace }}/bin/ares-macos-universal/ares.app /tmp/ares.zip
|
||||
xcrun notarytool submit /tmp/ares.zip --apple-id "$MACOS_NOTARIZATION_USERNAME" --password "$MACOS_NOTARIZATION_PASSWORD" --team-id "$MACOS_NOTARIZATION_TEAMID" --wait
|
||||
xcrun stapler staple ${{ github.workspace }}/bin/ares-macos-universal/ares.app
|
||||
env:
|
||||
MACOS_NOTARIZATION_USERNAME: ${{ secrets.MACOS_NOTARIZATION_USERNAME }}
|
||||
MACOS_NOTARIZATION_PASSWORD: ${{ secrets.MACOS_NOTARIZATION_PASSWORD }}
|
||||
MACOS_NOTARIZATION_TEAMID: ${{ secrets.MACOS_NOTARIZATION_TEAMID }}
|
||||
- name: Package Artifacts
|
||||
run: src/.github/scripts/package_artifacts.sh
|
||||
- name: Check Release Tag ☑️
|
||||
id: check
|
||||
run: |
|
||||
now=$(date +'%Y-%m-%d')
|
||||
subject=$(git -C src log -1 --pretty=%s)
|
||||
if [[ ${GITHUB_REF_NAME} == master ]];
|
||||
then
|
||||
echo "tag=nightly" >> $GITHUB_OUTPUT
|
||||
versionName="nightly ${now}"
|
||||
echo "versionName=${versionName}" >> $GITHUB_OUTPUT
|
||||
echo "description=${subject}" >> $GITHUB_OUTPUT
|
||||
else
|
||||
echo "tag=${GITHUB_REF_NAME}" >> $GITHUB_OUTPUT
|
||||
echo "versionName=${GITHUB_REF_NAME}" >> $GITHUB_OUTPUT
|
||||
description="This is ares ${GITHUB_REF_NAME}, released on ${now}."
|
||||
echo "description=${description}" >> $GITHUB_OUTPUT
|
||||
fi
|
||||
- name: Update Git Tag
|
||||
if: steps.check.outputs.tag == 'nightly'
|
||||
id: update-tag
|
||||
run: |
|
||||
git -C src tag -f ${{ steps.check.outputs.tag }}
|
||||
git -C src push -f origin ${{ steps.check.outputs.tag }}
|
||||
|
||||
- name: Create Release 🛫
|
||||
id: create_release
|
||||
uses: softprops/action-gh-release@c062e08bd532815e2082a85e87e3ef29c3e6d191
|
||||
with:
|
||||
prerelease: ${{ steps.check.outputs.tag == 'nightly' }}
|
||||
tag_name: ${{ steps.check.outputs.tag }}
|
||||
name: ares ${{ steps.check.outputs.versionName }}
|
||||
body: ${{ steps.check.outputs.description }}
|
||||
files: |
|
||||
${{ github.workspace }}/ares-source.tar.gz
|
||||
${{ github.workspace }}/ares-macos-universal.zip
|
||||
${{ github.workspace }}/ares-macos-universal-dSYMs.zip
|
||||
${{ github.workspace }}/ares-windows-x64.zip
|
||||
${{ github.workspace }}/ares-windows-x64-PDBs.zip
|
||||
${{ github.workspace }}/ares-windows-clang-cl-arm64.zip
|
||||
${{ github.workspace }}/ares-windows-clang-cl-arm64-PDBs.zip
|
||||
-53
@@ -1,53 +0,0 @@
|
||||
# Exclude everything
|
||||
/*
|
||||
|
||||
# Except for default project files
|
||||
!/.github
|
||||
!/ares
|
||||
!/desktop-ui
|
||||
!/hiro
|
||||
!/cmake
|
||||
!/libco
|
||||
!/mia
|
||||
!/nall
|
||||
!/ruby
|
||||
!/scripts
|
||||
!/tests
|
||||
!/thirdparty
|
||||
!/tools
|
||||
!/GNUMakefile
|
||||
!/LICENSE
|
||||
!/README.md
|
||||
!.editorconfig
|
||||
!.gitignore
|
||||
!.gitattributes
|
||||
!.gersemirc
|
||||
!deps.json
|
||||
!CMakeLists.txt
|
||||
!CMakePresets.json
|
||||
|
||||
# Exclude old macOS Finder metadata
|
||||
.DS_Store
|
||||
|
||||
# Exclude generated sources that still reside in-tree
|
||||
ruby/video/metal/shaders.metallib
|
||||
ruby/video/metal/shaders.ir
|
||||
ares/ares/resource/resource.cpp
|
||||
ares/ares/resource/resource.hpp
|
||||
hiro/resource/resource.cpp
|
||||
hiro/resource/resource.hpp
|
||||
desktop-ui/resource/resource.cpp
|
||||
desktop-ui/resource/resource.hpp
|
||||
mia/resource/resource.cpp
|
||||
mia/resource/resource.hpp
|
||||
|
||||
# Exclude Qt generated MOC file
|
||||
hiro/qt/qt.moc
|
||||
|
||||
# Exclude fetched third-party processor test binaries
|
||||
tests/arm7tdmi/tests
|
||||
tests/m68000/tests
|
||||
|
||||
# Exclude unused legacy zlib header that is renamed by CMake
|
||||
thirdparty/libchdr/deps/zlib-*/zconf.h
|
||||
thirdparty/libchdr/deps/zlib-*/zconf.h.included
|
||||
@@ -1,57 +0,0 @@
|
||||
cmake_minimum_required(VERSION 3.28...4.1)
|
||||
|
||||
include("${CMAKE_CURRENT_SOURCE_DIR}/cmake/common/bootstrap.cmake" NO_POLICY_SCOPE)
|
||||
|
||||
project(ares VERSION ${ARES_VERSION_CANONICAL})
|
||||
|
||||
include(compilerconfig)
|
||||
include(defaults)
|
||||
include(helpers)
|
||||
|
||||
add_subdirectory(thirdparty)
|
||||
|
||||
add_subdirectory(nall/nall)
|
||||
add_subdirectory(libco)
|
||||
add_subdirectory(ruby)
|
||||
add_subdirectory(hiro)
|
||||
|
||||
# gersemi: off
|
||||
set(
|
||||
ARES_CORES
|
||||
a26 a52 fc sfc sg ms md ps1 pce ng msx cv myvision gb gba ws ngp spec n64
|
||||
CACHE STRING "List of systems to be built by the project"
|
||||
)
|
||||
# gersemi: on
|
||||
|
||||
add_subdirectory(ares)
|
||||
add_subdirectory(mia)
|
||||
add_subdirectory(desktop-ui)
|
||||
|
||||
option(ARES_BUILD_OPTIONAL_TARGETS "Include supplemental tools and tests" OFF)
|
||||
|
||||
if(ARES_BUILD_OPTIONAL_TARGETS)
|
||||
enable_testing()
|
||||
add_subdirectory(tests/arm7tdmi)
|
||||
add_subdirectory(tests/armv6m)
|
||||
add_subdirectory(tests/i8080)
|
||||
add_subdirectory(tests/m68000)
|
||||
if(HIRO_BACKEND STREQUAL "GTK3")
|
||||
add_subdirectory(tools/genius)
|
||||
else()
|
||||
target_disable_subproject(genius "genius (database editor)")
|
||||
endif()
|
||||
else()
|
||||
target_disable_subproject(arm7tdmi "arm7tdmi processor test harness")
|
||||
target_disable_subproject(armv6m "armv6m processor test harness")
|
||||
target_disable_subproject(i8080 "i8080 processor test harness")
|
||||
target_disable_subproject(m68000 "m68000 processor test harness")
|
||||
target_disable_subproject(genius "genius (database editor)")
|
||||
endif()
|
||||
|
||||
add_subdirectory(tools/sourcery)
|
||||
|
||||
message_configuration()
|
||||
|
||||
add_subdirectory(.github)
|
||||
add_subdirectory(cmake)
|
||||
return()
|
||||
@@ -1,200 +0,0 @@
|
||||
{
|
||||
"version": 3,
|
||||
"cmakeMinimumRequired": {
|
||||
"major": 3,
|
||||
"minor": 28,
|
||||
"patch": 0
|
||||
},
|
||||
"configurePresets": [
|
||||
{
|
||||
"name": "baseCacheVars",
|
||||
"hidden": true,
|
||||
"cacheVariables": {
|
||||
"ARES_PROFILE_ACCURACY": false,
|
||||
"ARES_BUILD_LOCAL": true,
|
||||
"ENABLE_CCACHE": true,
|
||||
"ARES_BUILD_OFFICIAL": {"type": "BOOL", "value": "$penv{ARES_BUILD_OFFICIAL}"}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "macos",
|
||||
"displayName": "macOS",
|
||||
"description": "Xcode project (host architecture by default)",
|
||||
"inherits": ["baseCacheVars"],
|
||||
"condition": {
|
||||
"type": "equals",
|
||||
"lhs": "${hostSystemName}",
|
||||
"rhs": "Darwin"
|
||||
},
|
||||
"generator": "Xcode",
|
||||
"binaryDir": "${sourceDir}/build_macos",
|
||||
"cacheVariables": {
|
||||
"ARES_CODESIGN_IDENTITY": {"type": "STRING", "value": "$penv{CODESIGN_IDENT}"},
|
||||
"ARES_CODESIGN_TEAM": {"type": "STRING", "value": "$penv{CODESIGN_TEAM}"},
|
||||
"ARES_BUILD_OPTIONAL_TARGETS": true,
|
||||
"ENABLE_CCACHE": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "windows",
|
||||
"displayName": "Windows (Visual Studio, ClangCL)",
|
||||
"description": "Visual Studio project using ClangCL (host architecture)",
|
||||
"inherits": ["baseCacheVars"],
|
||||
"condition": {
|
||||
"type": "equals",
|
||||
"lhs": "${hostSystemName}",
|
||||
"rhs": "Windows"
|
||||
},
|
||||
"binaryDir": "${sourceDir}/build_vsclang",
|
||||
"generator": "Visual Studio 18 2026",
|
||||
"toolset": "ClangCL",
|
||||
"cacheVariables": {
|
||||
"ENABLE_CCACHE": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "windows-msvc",
|
||||
"displayName": "Windows (Visual Studio, MSVC)",
|
||||
"description": "Visual Studio project using MSVC (host architecture)",
|
||||
"inherits": ["baseCacheVars"],
|
||||
"condition": {
|
||||
"type": "equals",
|
||||
"lhs": "${hostSystemName}",
|
||||
"rhs": "Windows"
|
||||
},
|
||||
"binaryDir": "${sourceDir}/build_msvc",
|
||||
"generator": "Visual Studio 18 2026",
|
||||
"cacheVariables": {
|
||||
"ENABLE_CCACHE": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "macos-ci-universal",
|
||||
"displayName": "macOS for CI",
|
||||
"description": "Universal binary for building on Github Actions",
|
||||
"inherits": ["baseCacheVars"],
|
||||
"condition": {
|
||||
"type": "equals",
|
||||
"lhs": "${hostSystemName}",
|
||||
"rhs": "Darwin"
|
||||
},
|
||||
"generator": "Xcode",
|
||||
"binaryDir": "${sourceDir}/build",
|
||||
"cacheVariables": {
|
||||
"CMAKE_OSX_ARCHITECTURES": {"type": "STRING", "value": "x86_64;arm64"},
|
||||
"CMAKE_OSX_DEPLOYMENT_TARGET": {"type": "STRING", "value": "11.0"},
|
||||
"ARES_CODESIGN_IDENTITY": {"type": "STRING", "value": "$penv{MACOS_CERTIFICATE_NAME}"},
|
||||
"ARES_CODESIGN_TEAM": {"type": "STRING", "value": "$penv{MACOS_NOTARIZATION_TEAMID}"},
|
||||
"ENABLE_CCACHE": true,
|
||||
"ARES_BUILD_LOCAL": false,
|
||||
"ARES_UNITY_CORES": true,
|
||||
"ARES_BUILD_OPTIONAL_TARGETS": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "windows-ci-base",
|
||||
"hidden": true,
|
||||
"inherits": ["baseCacheVars"],
|
||||
"binaryDir": "${sourceDir}/build",
|
||||
"cacheVariables": {
|
||||
"CMAKE_BUILD_TYPE": {"type": "STRING", "value": "RelWithDebInfo"},
|
||||
"ENABLE_CCACHE": true,
|
||||
"ARES_BUILD_LOCAL": false,
|
||||
"ARES_BUILD_OPTIONAL_TARGETS": true,
|
||||
"ARES_UNITY_CORES": true,
|
||||
"ARES_PRECOMPILE_HEADERS": true,
|
||||
"CMAKE_MSVC_RUNTIME_LIBRARY": {"type": "STRING", "value": "MultiThreaded"},
|
||||
"CMAKE_IGNORE_PATH": {"type": "STRING", "value": "C:/Strawberry/c/bin/"}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "windows-ci-mingw-native",
|
||||
"displayName": "Windows for CI (x64 MSYS2/MinGW Clang)",
|
||||
"description": "Single-arch binary for building on Github Actions",
|
||||
"inherits": ["windows-ci-base"],
|
||||
"generator": "Ninja"
|
||||
},
|
||||
{
|
||||
"name": "windows-ci-cl-native",
|
||||
"displayName": "Windows for CI (x64 ClangCL)",
|
||||
"description": "Single-arch binary for building on Github Actions",
|
||||
"generator": "Visual Studio 18 2026",
|
||||
"inherits": ["windows-ci-base"],
|
||||
"toolset": "ClangCL"
|
||||
},
|
||||
{
|
||||
"name": "windows-ci-cl-cross",
|
||||
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"description": "Single-arch binary for building on Github Actions",
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"generator": "Visual Studio 18 2026",
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},
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{
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"name": "windows-ci-msvc-cross",
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"displayName": "Windows for CI (arm64 MSVC)",
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"description": "Single-arch binary for building on Github Actions",
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"generator": "Visual Studio 18 2026",
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"architecture": "arm64",
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"inherits": ["windows-ci-base"],
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}
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},
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{
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"name": "ubuntu-ci",
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"displayName": "Ubuntu CI (x64 gcc)",
|
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"description": "Single-arch binary for building on Github Actions",
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"generator": "Ninja",
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"binaryDir": "${sourceDir}/build",
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"cacheVariables": {
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"CMAKE_BUILD_TYPE": {"type": "STRING", "value": "RelWithDebInfo"},
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"ENABLE_CCACHE": true,
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"ENABLE_IPO": false,
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"ARES_BUILD_LOCAL": false,
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"ARES_BUILD_OPTIONAL_TARGETS": true,
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},
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{
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"name": "ubuntu-ci-clang",
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"CMAKE_CXX_COMPILER": "clang++"
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},
|
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{
|
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"name": "ubuntu-ci-qt",
|
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"displayName": "Ubuntu CI (arm64, gcc, Qt)",
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"ARES_BUILD_OPTIONAL_TARGETS": false
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}
|
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],
|
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"buildPresets": [
|
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{
|
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"name": "windows",
|
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"configurePreset": "windows",
|
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"displayName": "Windows build (host architecture)",
|
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"description": "Windows build (host architecture)",
|
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"configuration": "RelWithDebInfo"
|
||||
}
|
||||
]
|
||||
}
|
||||
@@ -1,893 +0,0 @@
|
||||
----------------------------------------------------------------------
|
||||
ares
|
||||
|
||||
Copyright (c) 2004-2025 ares team, Near et al
|
||||
|
||||
Permission to use, copy, modify, and/or distribute this software for any
|
||||
purpose with or without fee is hereby granted, provided that the above
|
||||
copyright notice and this permission notice appear in all copies.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
MAME-derived ROM decryption and arcade database
|
||||
|
||||
Portions of the ROM decryption code are derived from MAME source files
|
||||
licensed under the BSD 3-Clause License. The arcade database is generated
|
||||
from MAME machine data.
|
||||
|
||||
Copyright (c) 1997-2026 MAMEdev and contributors. All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software
|
||||
without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
Stack-less Just-In-Time compiler
|
||||
|
||||
Copyright Zoltan Herczeg ([email protected]). All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS
|
||||
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
libchdr
|
||||
|
||||
Copyright Romain Tisserand
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the <organization> nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
LZMA SDK is placed in the public domain.
|
||||
|
||||
Anyone is free to copy, modify, publish, use, compile, sell, or distribute
|
||||
the original LZMA SDK code, either in source code form or as a compiled binary,
|
||||
for any purpose, commercial or non-commercial, and by any means.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
zlib
|
||||
|
||||
(C) 1995-2017 Jean-loup Gailly and Mark Adler
|
||||
|
||||
This software is provided 'as-is', without any express or implied
|
||||
warranty. In no event will the authors be held liable for any damages
|
||||
arising from the use of this software.
|
||||
|
||||
Permission is granted to anyone to use this software for any purpose,
|
||||
including commercial applications, and to alter it and redistribute it
|
||||
freely, subject to the following restrictions:
|
||||
|
||||
1. The origin of this software must not be misrepresented; you must not
|
||||
claim that you wrote the original software. If you use this software
|
||||
in a product, an acknowledgment in the product documentation would be
|
||||
appreciated but is not required.
|
||||
2. Altered source versions must be plainly marked as such, and must not be
|
||||
misrepresented as being the original software.
|
||||
3. This notice may not be removed or altered from any source distribution.
|
||||
|
||||
Jean-loup Gailly Mark Adler
|
||||
[email protected] [email protected]
|
||||
|
||||
If you use the zlib library in a product, we would appreciate *not* receiving
|
||||
lengthy legal documents to sign. The sources are provided for free but without
|
||||
warranty of any kind. The library has been entirely written by Jean-loup
|
||||
Gailly and Mark Adler; it does not include third-party code.
|
||||
|
||||
If you redistribute modified sources, we would appreciate that you include in
|
||||
the file ChangeLog history information documenting your changes. Please read
|
||||
the FAQ for more information on the distribution of modified source versions.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
xxHash - Extremely Fast Hash algorithm
|
||||
Header File
|
||||
Copyright (C) 2012-2021 Yann Collet
|
||||
|
||||
BSD 2-Clause License (https://www.opensource.org/licenses/bsd-license.php)
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above
|
||||
copyright notice, this list of conditions and the following disclaimer
|
||||
in the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
You can contact the author at:
|
||||
- xxHash homepage: https://www.xxhash.com
|
||||
- xxHash source repository: https://github.com/Cyan4973/xxHash
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
MoltenVK
|
||||
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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||||
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|
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|
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|
||||
the brackets!) The text should be enclosed in the appropriate
|
||||
comment syntax for the file format. We also recommend that a
|
||||
file or class name and description of purpose be included on the
|
||||
same "printed page" as the copyright notice for easier
|
||||
identification within third-party archives.
|
||||
|
||||
Copyright [yyyy] [name of copyright owner]
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
OpenGL API and Extension Registry
|
||||
https://github.com/KhronosGroup/OpenGL-Registry
|
||||
|
||||
Copyright 2013-2020 The Khronos Group Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and/or associated documentation files (the
|
||||
"Materials"), to deal in the Materials without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Materials, and to
|
||||
permit persons to whom the Materials are furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Materials.
|
||||
|
||||
THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
EGL API and Extension Registry
|
||||
https://github.com/KhronosGroup/EGL-Registry
|
||||
|
||||
Copyright (c) 2008-2018 The Khronos Group Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and/or associated documentation files (the
|
||||
"Materials"), to deal in the Materials without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Materials, and to
|
||||
permit persons to whom the Materials are furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Materials.
|
||||
|
||||
THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
TZXFile
|
||||
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2020 MrReeMachine
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
ymfm
|
||||
|
||||
BSD 3-Clause License
|
||||
|
||||
Copyright (c) 2021, Aaron Giles
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
librashader
|
||||
Mozilla Public License Version 2.0
|
||||
==================================
|
||||
|
||||
### 1. Definitions
|
||||
|
||||
**1.1. “Contributor”**
|
||||
means each individual or legal entity that creates, contributes to
|
||||
the creation of, or owns Covered Software.
|
||||
|
||||
**1.2. “Contributor Version”**
|
||||
means the combination of the Contributions of others (if any) used
|
||||
by a Contributor and that particular Contributor's Contribution.
|
||||
|
||||
**1.3. “Contribution”**
|
||||
means Covered Software of a particular Contributor.
|
||||
|
||||
**1.4. “Covered Software”**
|
||||
means Source Code Form to which the initial Contributor has attached
|
||||
the notice in Exhibit A, the Executable Form of such Source Code
|
||||
Form, and Modifications of such Source Code Form, in each case
|
||||
including portions thereof.
|
||||
|
||||
**1.5. “Incompatible With Secondary Licenses”**
|
||||
means
|
||||
|
||||
* **(a)** that the initial Contributor has attached the notice described
|
||||
in Exhibit B to the Covered Software; or
|
||||
* **(b)** that the Covered Software was made available under the terms of
|
||||
version 1.1 or earlier of the License, but not also under the
|
||||
terms of a Secondary License.
|
||||
|
||||
**1.6. “Executable Form”**
|
||||
means any form of the work other than Source Code Form.
|
||||
|
||||
**1.7. “Larger Work”**
|
||||
means a work that combines Covered Software with other material, in
|
||||
a separate file or files, that is not Covered Software.
|
||||
|
||||
**1.8. “License”**
|
||||
means this document.
|
||||
|
||||
**1.9. “Licensable”**
|
||||
means having the right to grant, to the maximum extent possible,
|
||||
whether at the time of the initial grant or subsequently, any and
|
||||
all of the rights conveyed by this License.
|
||||
|
||||
**1.10. “Modifications”**
|
||||
means any of the following:
|
||||
|
||||
* **(a)** any file in Source Code Form that results from an addition to,
|
||||
deletion from, or modification of the contents of Covered
|
||||
Software; or
|
||||
* **(b)** any new file in Source Code Form that contains any Covered
|
||||
Software.
|
||||
|
||||
**1.11. “Patent Claims” of a Contributor**
|
||||
means any patent claim(s), including without limitation, method,
|
||||
process, and apparatus claims, in any patent Licensable by such
|
||||
Contributor that would be infringed, but for the grant of the
|
||||
License, by the making, using, selling, offering for sale, having
|
||||
made, import, or transfer of either its Contributions or its
|
||||
Contributor Version.
|
||||
|
||||
**1.12. “Secondary License”**
|
||||
means either the GNU General Public License, Version 2.0, the GNU
|
||||
Lesser General Public License, Version 2.1, the GNU Affero General
|
||||
Public License, Version 3.0, or any later versions of those
|
||||
licenses.
|
||||
|
||||
**1.13. “Source Code Form”**
|
||||
means the form of the work preferred for making modifications.
|
||||
|
||||
**1.14. “You” (or “Your”)**
|
||||
means an individual or a legal entity exercising rights under this
|
||||
License. For legal entities, “You” includes any entity that
|
||||
controls, is controlled by, or is under common control with You. For
|
||||
purposes of this definition, “control” means **(a)** the power, direct
|
||||
or indirect, to cause the direction or management of such entity,
|
||||
whether by contract or otherwise, or **(b)** ownership of more than
|
||||
fifty percent (50%) of the outstanding shares or beneficial
|
||||
ownership of such entity.
|
||||
|
||||
|
||||
### 2. License Grants and Conditions
|
||||
|
||||
#### 2.1. Grants
|
||||
|
||||
Each Contributor hereby grants You a world-wide, royalty-free,
|
||||
non-exclusive license:
|
||||
|
||||
* **(a)** under intellectual property rights (other than patent or trademark)
|
||||
Licensable by such Contributor to use, reproduce, make available,
|
||||
modify, display, perform, distribute, and otherwise exploit its
|
||||
Contributions, either on an unmodified basis, with Modifications, or
|
||||
as part of a Larger Work; and
|
||||
* **(b)** under Patent Claims of such Contributor to make, use, sell, offer
|
||||
for sale, have made, import, and otherwise transfer either its
|
||||
Contributions or its Contributor Version.
|
||||
|
||||
#### 2.2. Effective Date
|
||||
|
||||
The licenses granted in Section 2.1 with respect to any Contribution
|
||||
become effective for each Contribution on the date the Contributor first
|
||||
distributes such Contribution.
|
||||
|
||||
#### 2.3. Limitations on Grant Scope
|
||||
|
||||
The licenses granted in this Section 2 are the only rights granted under
|
||||
this License. No additional rights or licenses will be implied from the
|
||||
distribution or licensing of Covered Software under this License.
|
||||
Notwithstanding Section 2.1(b) above, no patent license is granted by a
|
||||
Contributor:
|
||||
|
||||
* **(a)** for any code that a Contributor has removed from Covered Software;
|
||||
or
|
||||
* **(b)** for infringements caused by: **(i)** Your and any other third party's
|
||||
modifications of Covered Software, or **(ii)** the combination of its
|
||||
Contributions with other software (except as part of its Contributor
|
||||
Version); or
|
||||
* **(c)** under Patent Claims infringed by Covered Software in the absence of
|
||||
its Contributions.
|
||||
|
||||
This License does not grant any rights in the trademarks, service marks,
|
||||
or logos of any Contributor (except as may be necessary to comply with
|
||||
the notice requirements in Section 3.4).
|
||||
|
||||
#### 2.4. Subsequent Licenses
|
||||
|
||||
No Contributor makes additional grants as a result of Your choice to
|
||||
distribute the Covered Software under a subsequent version of this
|
||||
License (see Section 10.2) or under the terms of a Secondary License (if
|
||||
permitted under the terms of Section 3.3).
|
||||
|
||||
#### 2.5. Representation
|
||||
|
||||
Each Contributor represents that the Contributor believes its
|
||||
Contributions are its original creation(s) or it has sufficient rights
|
||||
to grant the rights to its Contributions conveyed by this License.
|
||||
|
||||
#### 2.6. Fair Use
|
||||
|
||||
This License is not intended to limit any rights You have under
|
||||
applicable copyright doctrines of fair use, fair dealing, or other
|
||||
equivalents.
|
||||
|
||||
#### 2.7. Conditions
|
||||
|
||||
Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted
|
||||
in Section 2.1.
|
||||
|
||||
|
||||
### 3. Responsibilities
|
||||
|
||||
#### 3.1. Distribution of Source Form
|
||||
|
||||
All distribution of Covered Software in Source Code Form, including any
|
||||
Modifications that You create or to which You contribute, must be under
|
||||
the terms of this License. You must inform recipients that the Source
|
||||
Code Form of the Covered Software is governed by the terms of this
|
||||
License, and how they can obtain a copy of this License. You may not
|
||||
attempt to alter or restrict the recipients' rights in the Source Code
|
||||
Form.
|
||||
|
||||
#### 3.2. Distribution of Executable Form
|
||||
|
||||
If You distribute Covered Software in Executable Form then:
|
||||
|
||||
* **(a)** such Covered Software must also be made available in Source Code
|
||||
Form, as described in Section 3.1, and You must inform recipients of
|
||||
the Executable Form how they can obtain a copy of such Source Code
|
||||
Form by reasonable means in a timely manner, at a charge no more
|
||||
than the cost of distribution to the recipient; and
|
||||
|
||||
* **(b)** You may distribute such Executable Form under the terms of this
|
||||
License, or sublicense it under different terms, provided that the
|
||||
license for the Executable Form does not attempt to limit or alter
|
||||
the recipients' rights in the Source Code Form under this License.
|
||||
|
||||
#### 3.3. Distribution of a Larger Work
|
||||
|
||||
You may create and distribute a Larger Work under terms of Your choice,
|
||||
provided that You also comply with the requirements of this License for
|
||||
the Covered Software. If the Larger Work is a combination of Covered
|
||||
Software with a work governed by one or more Secondary Licenses, and the
|
||||
Covered Software is not Incompatible With Secondary Licenses, this
|
||||
License permits You to additionally distribute such Covered Software
|
||||
under the terms of such Secondary License(s), so that the recipient of
|
||||
the Larger Work may, at their option, further distribute the Covered
|
||||
Software under the terms of either this License or such Secondary
|
||||
License(s).
|
||||
|
||||
#### 3.4. Notices
|
||||
|
||||
You may not remove or alter the substance of any license notices
|
||||
(including copyright notices, patent notices, disclaimers of warranty,
|
||||
or limitations of liability) contained within the Source Code Form of
|
||||
the Covered Software, except that You may alter any license notices to
|
||||
the extent required to remedy known factual inaccuracies.
|
||||
|
||||
#### 3.5. Application of Additional Terms
|
||||
|
||||
You may choose to offer, and to charge a fee for, warranty, support,
|
||||
indemnity or liability obligations to one or more recipients of Covered
|
||||
Software. However, You may do so only on Your own behalf, and not on
|
||||
behalf of any Contributor. You must make it absolutely clear that any
|
||||
such warranty, support, indemnity, or liability obligation is offered by
|
||||
You alone, and You hereby agree to indemnify every Contributor for any
|
||||
liability incurred by such Contributor as a result of warranty, support,
|
||||
indemnity or liability terms You offer. You may include additional
|
||||
disclaimers of warranty and limitations of liability specific to any
|
||||
jurisdiction.
|
||||
|
||||
|
||||
### 4. Inability to Comply Due to Statute or Regulation
|
||||
|
||||
If it is impossible for You to comply with any of the terms of this
|
||||
License with respect to some or all of the Covered Software due to
|
||||
statute, judicial order, or regulation then You must: **(a)** comply with
|
||||
the terms of this License to the maximum extent possible; and **(b)**
|
||||
describe the limitations and the code they affect. Such description must
|
||||
be placed in a text file included with all distributions of the Covered
|
||||
Software under this License. Except to the extent prohibited by statute
|
||||
or regulation, such description must be sufficiently detailed for a
|
||||
recipient of ordinary skill to be able to understand it.
|
||||
|
||||
|
||||
### 5. Termination
|
||||
|
||||
**5.1.** The rights granted under this License will terminate automatically
|
||||
if You fail to comply with any of its terms. However, if You become
|
||||
compliant, then the rights granted under this License from a particular
|
||||
Contributor are reinstated **(a)** provisionally, unless and until such
|
||||
Contributor explicitly and finally terminates Your grants, and **(b)** on an
|
||||
ongoing basis, if such Contributor fails to notify You of the
|
||||
non-compliance by some reasonable means prior to 60 days after You have
|
||||
come back into compliance. Moreover, Your grants from a particular
|
||||
Contributor are reinstated on an ongoing basis if such Contributor
|
||||
notifies You of the non-compliance by some reasonable means, this is the
|
||||
first time You have received notice of non-compliance with this License
|
||||
from such Contributor, and You become compliant prior to 30 days after
|
||||
Your receipt of the notice.
|
||||
|
||||
**5.2.** If You initiate litigation against any entity by asserting a patent
|
||||
infringement claim (excluding declaratory judgment actions,
|
||||
counter-claims, and cross-claims) alleging that a Contributor Version
|
||||
directly or indirectly infringes any patent, then the rights granted to
|
||||
You by any and all Contributors for the Covered Software under Section
|
||||
2.1 of this License shall terminate.
|
||||
|
||||
**5.3.** In the event of termination under Sections 5.1 or 5.2 above, all
|
||||
end user license agreements (excluding distributors and resellers) which
|
||||
have been validly granted by You or Your distributors under this License
|
||||
prior to termination shall survive termination.
|
||||
|
||||
|
||||
### 6. Disclaimer of Warranty
|
||||
|
||||
> Covered Software is provided under this License on an “as is”
|
||||
> basis, without warranty of any kind, either expressed, implied, or
|
||||
> statutory, including, without limitation, warranties that the
|
||||
> Covered Software is free of defects, merchantable, fit for a
|
||||
> particular purpose or non-infringing. The entire risk as to the
|
||||
> quality and performance of the Covered Software is with You.
|
||||
> Should any Covered Software prove defective in any respect, You
|
||||
> (not any Contributor) assume the cost of any necessary servicing,
|
||||
> repair, or correction. This disclaimer of warranty constitutes an
|
||||
> essential part of this License. No use of any Covered Software is
|
||||
> authorized under this License except under this disclaimer.
|
||||
|
||||
### 7. Limitation of Liability
|
||||
|
||||
> Under no circumstances and under no legal theory, whether tort
|
||||
> (including negligence), contract, or otherwise, shall any
|
||||
> Contributor, or anyone who distributes Covered Software as
|
||||
> permitted above, be liable to You for any direct, indirect,
|
||||
> special, incidental, or consequential damages of any character
|
||||
> including, without limitation, damages for lost profits, loss of
|
||||
> goodwill, work stoppage, computer failure or malfunction, or any
|
||||
> and all other commercial damages or losses, even if such party
|
||||
> shall have been informed of the possibility of such damages. This
|
||||
> limitation of liability shall not apply to liability for death or
|
||||
> personal injury resulting from such party's negligence to the
|
||||
> extent applicable law prohibits such limitation. Some
|
||||
> jurisdictions do not allow the exclusion or limitation of
|
||||
> incidental or consequential damages, so this exclusion and
|
||||
> limitation may not apply to You.
|
||||
|
||||
|
||||
### 8. Litigation
|
||||
|
||||
Any litigation relating to this License may be brought only in the
|
||||
courts of a jurisdiction where the defendant maintains its principal
|
||||
place of business and such litigation shall be governed by laws of that
|
||||
jurisdiction, without reference to its conflict-of-law provisions.
|
||||
Nothing in this Section shall prevent a party's ability to bring
|
||||
cross-claims or counter-claims.
|
||||
|
||||
|
||||
### 9. Miscellaneous
|
||||
|
||||
This License represents the complete agreement concerning the subject
|
||||
matter hereof. If any provision of this License is held to be
|
||||
unenforceable, such provision shall be reformed only to the extent
|
||||
necessary to make it enforceable. Any law or regulation which provides
|
||||
that the language of a contract shall be construed against the drafter
|
||||
shall not be used to construe this License against a Contributor.
|
||||
|
||||
|
||||
### 10. Versions of the License
|
||||
|
||||
#### 10.1. New Versions
|
||||
|
||||
Mozilla Foundation is the license steward. Except as provided in Section
|
||||
10.3, no one other than the license steward has the right to modify or
|
||||
publish new versions of this License. Each version will be given a
|
||||
distinguishing version number.
|
||||
|
||||
#### 10.2. Effect of New Versions
|
||||
|
||||
You may distribute the Covered Software under the terms of the version
|
||||
of the License under which You originally received the Covered Software,
|
||||
or under the terms of any subsequent version published by the license
|
||||
steward.
|
||||
|
||||
#### 10.3. Modified Versions
|
||||
|
||||
If you create software not governed by this License, and you want to
|
||||
create a new license for such software, you may create and use a
|
||||
modified version of this License if you rename the license and remove
|
||||
any references to the name of the license steward (except to note that
|
||||
such modified license differs from this License).
|
||||
|
||||
#### 10.4. Distributing Source Code Form that is Incompatible With Secondary Licenses
|
||||
|
||||
If You choose to distribute Source Code Form that is Incompatible With
|
||||
Secondary Licenses under the terms of this version of the License, the
|
||||
notice described in Exhibit B of this License must be attached.
|
||||
|
||||
## Exhibit A - Source Code Form License Notice
|
||||
|
||||
This Source Code Form is subject to the terms of the Mozilla Public
|
||||
License, v. 2.0. If a copy of the MPL was not distributed with this
|
||||
file, You can obtain one at http://mozilla.org/MPL/2.0/.
|
||||
|
||||
If it is not possible or desirable to put the notice in a particular
|
||||
file, then You may include the notice in a location (such as a LICENSE
|
||||
file in a relevant directory) where a recipient would be likely to look
|
||||
for such a notice.
|
||||
|
||||
You may add additional accurate notices of copyright ownership.
|
||||
|
||||
## Exhibit B - “Incompatible With Secondary Licenses” Notice
|
||||
|
||||
This Source Code Form is "Incompatible With Secondary Licenses", as
|
||||
defined by the Mozilla Public License, v. 2.0.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------------------------------------------------------------
|
||||
qoi/qon
|
||||
|
||||
Copyright (c) 2025, Roger Sanders
|
||||
Revised QOI format, achieving higher compression with equivalent performance.
|
||||
|
||||
Based on the "Quite OK Image" format for fast, lossless image compression
|
||||
Copyright (c) 2021, Dominic Szablewski - https://phoboslab.org
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
----------------------------------------------------------------------
|
||||
@@ -1,87 +0,0 @@
|
||||
<img src="https://github.com/ares-emulator/ares/blob/master/ares/ares/resource/logo@2x.png" width="350"/>
|
||||
|
||||
[](https://github.com/higan-emu/ares/blob/master/LICENSE)
|
||||
|
||||
**ares** is a multi-system emulator that began development on October 14th, 2004.
|
||||
It is a descendant of [higan](https://github.com/higan-emu/higan) and [bsnes](https://github.com/bsnes-emu/bsnes/), and focuses on accuracy and preservation.
|
||||
|
||||
It's worth noting that ares takes some uncommon design approaches that essentially trade speed for code clarity. We avoid state machines and bitmasks (when possible). Most cores end up being half the amount of code, but slower. The code is clearer and less spaghettified, especially for systems with lots of processors. C bitfields being non-portable incurs a speedhit. Windows also has a speedhit over Linux due to its ABI needing more instructions to switch contexts.
|
||||
|
||||
Official Releases
|
||||
-----------------
|
||||
|
||||
Official releases are available from
|
||||
[the ares website](https://ares-emu.net).
|
||||
|
||||
Nightly Builds
|
||||
--------------
|
||||
|
||||
Automated, untested builds of ares are available for Windows and macOS as a [pre-release](https://github.com/ares-emulator/ares/releases/tag/nightly).
|
||||
Only the latest nightly build is kept.
|
||||
|
||||
Building ares
|
||||
-------------
|
||||
|
||||
ares supports building on Windows, macOS, and various Linux/BSD distributions. See build instructions for:
|
||||
|
||||
* [Windows](https://github.com/ares-emulator/ares/wiki/Build-Instructions-For-Windows)
|
||||
* [macOS](https://github.com/ares-emulator/ares/wiki/Build-Instructions-For-macOS)
|
||||
* [Linux](https://github.com/ares-emulator/ares/wiki/Build-Instructions-For-Linux)
|
||||
* [BSD](https://github.com/ares-emulator/ares/wiki/Build-Instructions-For-BSD)
|
||||
|
||||
Command-line options
|
||||
--------------------
|
||||
|
||||
When started from the command-line, ares accepts a few options.
|
||||
|
||||
```
|
||||
Usage: ./ares [options] game(s)
|
||||
|
||||
--help Displays available options and exit
|
||||
--version Displays the version string of the application
|
||||
--terminal Create new terminal window (Windows only)
|
||||
--fullscreen Start in full screen mode
|
||||
--pseudofullscreen Start in pseudo full screen mode
|
||||
--kiosk Start in minimal UI mode (implies --no-file-prompt)
|
||||
--system system Specify the system name
|
||||
--shader shader Specify a slang shader to load (requires OpenGL or Metal)
|
||||
--setting name=value Specify a value for a setting
|
||||
--dump-all-settings Show a list of all existing settings and exit
|
||||
--no-file-prompt Do not prompt to load (optional) additional roms (eg: 64DD)
|
||||
--settings-file path Specify a settings file override (settings.bml)
|
||||
--save-state slot Specify a save state slot to load (1-9)
|
||||
```
|
||||
|
||||
The --system option is useful when the system type cannot be auto-detected.
|
||||
--fullscreen will only have an effect if a game is also passed in argument.
|
||||
|
||||
Example:
|
||||
`ares --system MSX examples.rom --fullscreen`
|
||||
|
||||
Specifying multiple games allows for multi-cart support. For example, to load
|
||||
the Super GameBoy BIOS and a game in one command (to avoid a file prompt), you
|
||||
can do:
|
||||
|
||||
`ares "Super GameBoy.sfc" "Super Mario Land.gb"`
|
||||
|
||||
The --no-file-prompt option is useful if you wish to launch a game from CLI
|
||||
without being prompted to load additional roms. For example, some Nintendo 64
|
||||
games optionally support 64DD expansion disks, so this option can be used to
|
||||
suppress the "64DD Disk" file dialog, and assume any secondary content is
|
||||
disconnected.
|
||||
|
||||
High-level Components
|
||||
---------------------
|
||||
|
||||
* __ares__: emulator cores and component implementations
|
||||
* __desktop-ui__: main GUI implementation for this project
|
||||
* __hiro__: cross-platform GUI toolkit that utilizes native APIs on supported platforms
|
||||
* __nall__: Near's alternative to the C++ standard library
|
||||
* __ruby__: interface between a hiro application and platform-specific APIs for emulator video, audio, and input
|
||||
* __mia__: internal ROM database and ROM/image loader
|
||||
* __libco__: cooperative multithreading library
|
||||
|
||||
Contributing
|
||||
------------
|
||||
|
||||
Please join our discord to chat with other ares developers: https://discord.com/invite/gz2quhk2kv
|
||||
@@ -1,333 +0,0 @@
|
||||
add_library(ares STATIC ares/ares.cpp ares/memory/fixed-allocator.cpp)
|
||||
|
||||
configure_file(ares/ares.cpp.in ares/ares.cpp @ONLY)
|
||||
|
||||
add_library(ares::ares ALIAS ares)
|
||||
|
||||
option(ARES_PROFILE_ACCURACY "Build to prefer emulation accuracy over performance in certain specific areas" OFF)
|
||||
option(ARES_PRECOMPILE_HEADERS "Precompile ares/ares.hpp header for performance" OFF)
|
||||
option(
|
||||
ARES_UNITY_CORES
|
||||
"\
|
||||
Build each core as one translation unit. Decreases cold build times but increases incremental build times. Slightly \
|
||||
increases performance.
|
||||
"
|
||||
OFF
|
||||
)
|
||||
|
||||
add_sourcery_command(ares ares/resource)
|
||||
|
||||
if(ARES_PRECOMPILE_HEADERS)
|
||||
target_precompile_headers(ares PRIVATE "$<$<COMPILE_LANGUAGE:CXX>:ares/ares.hpp>")
|
||||
endif()
|
||||
|
||||
target_link_libraries(ares PRIVATE libco ares::nall::headers $<$<BOOL:${ARES_ENABLE_CHD}>:chdr-static> PUBLIC sljit)
|
||||
|
||||
if(ARES_PROFILE_ACCURACY)
|
||||
target_compile_definitions(ares PUBLIC PROFILE_ACCURACY)
|
||||
else()
|
||||
target_compile_definitions(ares PUBLIC PROFILE_PERFORMANCE)
|
||||
endif()
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE ares/ares.cpp ares/ares.cpp.in ares/ares.hpp ares/inline.hpp ares/platform.hpp ares/random.hpp ares/types.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/debug/debug.cpp
|
||||
ares/debug/debug.hpp
|
||||
ares/memory/fixed-allocator.cpp
|
||||
ares/memory/fixed-allocator.hpp
|
||||
ares/memory/memory.hpp
|
||||
ares/memory/readable.hpp
|
||||
ares/memory/writable.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE ares/scheduler/scheduler.cpp ares/scheduler/scheduler.hpp ares/scheduler/thread.cpp ares/scheduler/thread.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/node/attribute.hpp
|
||||
ares/node/class.hpp
|
||||
ares/node/node.cpp
|
||||
ares/node/node.hpp
|
||||
ares/node/object.hpp
|
||||
ares/node/peripheral.hpp
|
||||
ares/node/port.hpp
|
||||
ares/node/system.hpp
|
||||
)
|
||||
|
||||
target_sources(ares PRIVATE ares/node/audio/audio.hpp ares/node/audio/stream.cpp ares/node/audio/stream.hpp)
|
||||
|
||||
target_sources(ares PRIVATE ares/node/component/component.hpp ares/node/component/real-time-clock.hpp)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/node/input/axis.hpp
|
||||
ares/node/input/button.hpp
|
||||
ares/node/input/input.hpp
|
||||
ares/node/input/rumble.hpp
|
||||
ares/node/input/trigger.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/node/setting/boolean.hpp
|
||||
ares/node/setting/integer.hpp
|
||||
ares/node/setting/natural.hpp
|
||||
ares/node/setting/real.hpp
|
||||
ares/node/setting/setting.hpp
|
||||
ares/node/setting/string.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/node/video/screen.cpp
|
||||
ares/node/video/screen.hpp
|
||||
ares/node/video/sprite.cpp
|
||||
ares/node/video/sprite.hpp
|
||||
ares/node/video/video.hpp
|
||||
)
|
||||
|
||||
target_sources(
|
||||
ares
|
||||
PRIVATE
|
||||
ares/node/debugger/debugger.hpp
|
||||
ares/node/debugger/graphics.hpp
|
||||
ares/node/debugger/memory.hpp
|
||||
ares/node/debugger/properties.hpp
|
||||
ares/node/debugger/tracer/tracer.hpp
|
||||
ares/node/debugger/tracer/instruction.hpp
|
||||
ares/node/debugger/tracer/notification.hpp
|
||||
)
|
||||
|
||||
if(OS_WINDOWS)
|
||||
include(cmake/os-windows.cmake)
|
||||
elseif(OS_MACOS)
|
||||
include(cmake/os-macos.cmake)
|
||||
elseif(OS_LINUX OR OS_FREEBSD OR OS_OPENBSD)
|
||||
include(cmake/os-linux.cmake)
|
||||
endif()
|
||||
|
||||
macro(ares_components)
|
||||
list(APPEND ares.components ${ARGV})
|
||||
set(ares.components ${ares.components} PARENT_SCOPE)
|
||||
endmacro()
|
||||
|
||||
macro(ares_add_sources)
|
||||
set(options "")
|
||||
set(oneValueArgs CORE)
|
||||
set(multiValueArgs PRIMARY INCLUDED UNITY)
|
||||
cmake_parse_arguments(AAS "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN})
|
||||
|
||||
target_sources(ares PRIVATE ${AAS_INCLUDED} ${AAS_PRIMARY})
|
||||
|
||||
if(ARES_UNITY_CORES)
|
||||
list(APPEND AAS_INCLUDED ${AAS_PRIMARY})
|
||||
target_sources(ares PRIVATE ${AAS_UNITY})
|
||||
endif()
|
||||
|
||||
foreach(arg IN ITEMS ${AAS_INCLUDED})
|
||||
list(APPEND ARES_HEADER_SOURCES "${AAS_CORE}/${arg}")
|
||||
endforeach()
|
||||
set(ARES_HEADER_SOURCES ${ARES_HEADER_SOURCES} PARENT_SCOPE)
|
||||
endmacro()
|
||||
|
||||
list(TRANSFORM ARES_CORES STRIP)
|
||||
|
||||
if(a26 IN_LIST ARES_CORES)
|
||||
enable_core("Atari 2600")
|
||||
add_subdirectory(a26)
|
||||
else()
|
||||
disable_core("Atari 2600")
|
||||
endif()
|
||||
|
||||
if(a52 IN_LIST ARES_CORES)
|
||||
enable_core("Atari 5200")
|
||||
add_subdirectory(a52)
|
||||
else()
|
||||
disable_core("Atari 5200")
|
||||
endif()
|
||||
|
||||
if(fc IN_LIST ARES_CORES)
|
||||
enable_core("NES / Famicom")
|
||||
add_subdirectory(fc)
|
||||
else()
|
||||
disable_core("NES / Famicom")
|
||||
endif()
|
||||
|
||||
if(sfc IN_LIST ARES_CORES)
|
||||
enable_core("SNES / Super Famicom")
|
||||
add_subdirectory(sfc)
|
||||
else()
|
||||
disable_core("SNES / Super Famicom")
|
||||
endif()
|
||||
|
||||
if(n64 IN_LIST ARES_CORES)
|
||||
enable_core("Nintendo 64")
|
||||
add_subdirectory(n64)
|
||||
else()
|
||||
disable_core("Nintendo 64")
|
||||
endif()
|
||||
|
||||
if(sg IN_LIST ARES_CORES)
|
||||
enable_core("Sega SG-1000")
|
||||
add_subdirectory(sg)
|
||||
else()
|
||||
disable_core("Sega SG-1000")
|
||||
endif()
|
||||
|
||||
if(ms IN_LIST ARES_CORES)
|
||||
enable_core("Sega Master System / Mark III")
|
||||
add_subdirectory(ms)
|
||||
else()
|
||||
disable_core("Sega Master System / Mark III")
|
||||
endif()
|
||||
|
||||
if(md IN_LIST ARES_CORES)
|
||||
enable_core("Sega Mega Drive / Genesis")
|
||||
add_subdirectory(md)
|
||||
else()
|
||||
disable_core("Sega Mega Drive / Genesis")
|
||||
endif()
|
||||
|
||||
if(saturn IN_LIST ARES_CORES)
|
||||
enable_core("Sega Saturn")
|
||||
add_subdirectory(saturn)
|
||||
else()
|
||||
disable_core("Sega Saturn")
|
||||
endif()
|
||||
|
||||
if(ps1 IN_LIST ARES_CORES)
|
||||
enable_core("PlayStation")
|
||||
add_subdirectory(ps1)
|
||||
else()
|
||||
disable_core("Playstation")
|
||||
endif()
|
||||
|
||||
if(pce IN_LIST ARES_CORES)
|
||||
enable_core("PC-Engine / TurboGrafx")
|
||||
add_subdirectory(pce)
|
||||
else()
|
||||
disable_core("PC-Engine / TurboGrafx")
|
||||
endif()
|
||||
|
||||
if(msx IN_LIST ARES_CORES)
|
||||
enable_core("Microsoft MSX")
|
||||
add_subdirectory(msx)
|
||||
else()
|
||||
disable_core("Microsoft MSX")
|
||||
endif()
|
||||
|
||||
if(cv IN_LIST ARES_CORES)
|
||||
enable_core("ColecoVision")
|
||||
add_subdirectory(cv)
|
||||
else()
|
||||
disable_core("ColecoVision")
|
||||
endif()
|
||||
|
||||
if(myvision IN_LIST ARES_CORES)
|
||||
enable_core("My Vision")
|
||||
add_subdirectory(myvision)
|
||||
else()
|
||||
disable_core("My Vision")
|
||||
endif()
|
||||
|
||||
if(gb IN_LIST ARES_CORES)
|
||||
enable_core("Game Boy / Game Boy Color")
|
||||
add_subdirectory(gb)
|
||||
else()
|
||||
disable_core("Game Boy / Game Boy Color")
|
||||
endif()
|
||||
|
||||
if(gba IN_LIST ARES_CORES)
|
||||
enable_core("Game Boy Advance")
|
||||
add_subdirectory(gba)
|
||||
else()
|
||||
disable_core("Game Boy Advance")
|
||||
endif()
|
||||
|
||||
if(ws IN_LIST ARES_CORES)
|
||||
enable_core("WonderSwan / WonderSwan Color")
|
||||
add_subdirectory(ws)
|
||||
else()
|
||||
disable_core("WonderSwan / WonderSwan Color")
|
||||
endif()
|
||||
|
||||
if(ng IN_LIST ARES_CORES)
|
||||
enable_core("Neo Geo (AES/MVS)")
|
||||
add_subdirectory(ng)
|
||||
else()
|
||||
disable_core("Neo Geo (AES/MVS)")
|
||||
endif()
|
||||
|
||||
if(ngp IN_LIST ARES_CORES)
|
||||
enable_core("Neo Geo Pocket / Neo Geo Pocket Color")
|
||||
add_subdirectory(ngp)
|
||||
else()
|
||||
disable_core("Neo Geo Pocket / Neo Geo Pocket Color")
|
||||
endif()
|
||||
|
||||
if(spec IN_LIST ARES_CORES)
|
||||
enable_core("ZX Spectrum")
|
||||
add_subdirectory(spec)
|
||||
else()
|
||||
disable_core("ZX Spectrum")
|
||||
endif()
|
||||
|
||||
add_subdirectory(component)
|
||||
|
||||
foreach(c IN LISTS ARES_CORES)
|
||||
# target_enable_feature(ares "${c} core" CORE_$<UPPER_CASE:${c}>)
|
||||
target_compile_definitions(ares PUBLIC CORE_$<UPPER_CASE:${c}>)
|
||||
endforeach()
|
||||
|
||||
get_target_property(ares_SOURCES ares SOURCES)
|
||||
|
||||
set_source_files_properties(
|
||||
ares
|
||||
ares/debug/debug.cpp
|
||||
ares/node/audio/stream.cpp
|
||||
ares/node/node.cpp
|
||||
ares/node/video/screen.cpp
|
||||
ares/node/video/sprite.cpp
|
||||
ares/scheduler/thread.cpp
|
||||
ares/scheduler/scheduler.cpp
|
||||
PROPERTIES HEADER_FILE_ONLY TRUE
|
||||
)
|
||||
|
||||
set_source_files_properties(
|
||||
n64/vulkan/parallel-rdp/vulkan/shader.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/descriptor_set.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/device.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/command_buffer.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/render_pass.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/context.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/memory_allocator.cpp
|
||||
n64/vulkan/parallel-rdp/vulkan/semaphore.cpp
|
||||
n64/vulkan/parallel-rdp/util/logging.cpp
|
||||
n64/vulkan/parallel-rdp/util/environment.cpp
|
||||
n64/vulkan/parallel-rdp/util/thread_name.cpp
|
||||
n64/vulkan/parallel-rdp/util/timer.cpp
|
||||
PROPERTIES SKIP_PRECOMPILE_HEADERS ON
|
||||
)
|
||||
|
||||
target_sources(ares PRIVATE cmake/os-macos.cmake cmake/os-windows.cmake cmake/os-linux.cmake)
|
||||
|
||||
set_source_files_properties(ares ${ARES_HEADER_SOURCES} PROPERTIES HEADER_FILE_ONLY TRUE)
|
||||
|
||||
set_source_files_properties(ares ares/ares.cpp ares/memory/fixed-allocator.cpp PROPERTIES HEADER_FILE_ONLY FALSE)
|
||||
|
||||
target_include_directories(ares INTERFACE ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
|
||||
source_group(TREE ${CMAKE_CURRENT_SOURCE_DIR} FILES ${ares_SOURCES})
|
||||
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Binary file not shown.
Binary file not shown.
Whitespace-only changes.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Whitespace-only changes.
Whitespace-only changes.
@@ -1,122 +0,0 @@
|
||||
layout
|
||||
name: Japanese
|
||||
|
||||
//row 0
|
||||
key: 0 わ を
|
||||
key: 1 ! ぬ
|
||||
key: 2 " ふ
|
||||
key: 3 # あ ぁ
|
||||
key: 4 $ う ぅ
|
||||
key: 5 % え ぇ
|
||||
key: 6 & お ぉ
|
||||
key: 7 ’ や ゃ
|
||||
|
||||
//row 1
|
||||
key: 8 ( ゆ ゅ
|
||||
key: 9 ) よ ょ
|
||||
key: - = ほ
|
||||
key: ^ ~ へ
|
||||
key: ¥ | ー
|
||||
key: @ ‘ "
|
||||
key: [ { 。
|
||||
key: ; + れ
|
||||
|
||||
//row 2
|
||||
key: : * け
|
||||
key: ] } む
|
||||
key: , < ね `
|
||||
key: . > る 。
|
||||
key: / ? め .
|
||||
key: - ろ
|
||||
key: A ち
|
||||
key: B こ
|
||||
|
||||
//row 3
|
||||
key: C そ
|
||||
key: D し
|
||||
key: E い ぃ
|
||||
key: F は
|
||||
key: G き
|
||||
key: H く
|
||||
key: I に
|
||||
key: J ま
|
||||
|
||||
//row 4
|
||||
key: K の
|
||||
key: L り
|
||||
key: M も
|
||||
key: N み
|
||||
key: O ら
|
||||
key: P せ
|
||||
key: Q た
|
||||
key: R す
|
||||
|
||||
//row 5
|
||||
key: S と
|
||||
key: T か
|
||||
key: U な
|
||||
key: V ひ
|
||||
key: W て
|
||||
key: X さ
|
||||
key: Y ん
|
||||
key: Z つ っ
|
||||
|
||||
//row 6
|
||||
key: SHIFT
|
||||
key: CTRL
|
||||
key: GRAPH
|
||||
key: CAPS
|
||||
key: かな
|
||||
key: F1 F6
|
||||
key: F2 F7
|
||||
key: F3 F8
|
||||
|
||||
//row 7
|
||||
key: F4 F9
|
||||
key: F5 F10
|
||||
key: ESC
|
||||
key: TAB
|
||||
key: STOP
|
||||
key: BS
|
||||
key: SELECT
|
||||
key: RETURN
|
||||
|
||||
//row 8
|
||||
key: SPACE
|
||||
key: CLS/HOME
|
||||
key: INS
|
||||
key: DEL
|
||||
key: ←
|
||||
key: ↑
|
||||
key: ↓
|
||||
key: →
|
||||
|
||||
//row 9
|
||||
key: *
|
||||
key: +
|
||||
key: /
|
||||
key: 0
|
||||
key: 1
|
||||
key: 2
|
||||
key: 3
|
||||
key: 4
|
||||
|
||||
//row 10
|
||||
key: 5
|
||||
key: 6
|
||||
key: 7
|
||||
key: 8
|
||||
key: 9
|
||||
key: -
|
||||
key: ,
|
||||
key: .
|
||||
|
||||
//row 11
|
||||
key:
|
||||
key: 実行
|
||||
key:
|
||||
key: 取消
|
||||
key:
|
||||
key:
|
||||
key:
|
||||
key:
|
||||
Binary file not shown.
Whitespace-only changes.
@@ -1,122 +0,0 @@
|
||||
layout
|
||||
name: Japanese
|
||||
|
||||
//row 0
|
||||
key: 0 わ を
|
||||
key: 1 ! ぬ
|
||||
key: 2 " ふ
|
||||
key: 3 # あ ぁ
|
||||
key: 4 $ う ぅ
|
||||
key: 5 % え ぇ
|
||||
key: 6 & お ぉ
|
||||
key: 7 ’ や ゃ
|
||||
|
||||
//row 1
|
||||
key: 8 ( ゆ ゅ
|
||||
key: 9 ) よ ょ
|
||||
key: - = ほ
|
||||
key: ^ ~ へ
|
||||
key: ¥ | ー
|
||||
key: @ ‘ "
|
||||
key: [ { 。
|
||||
key: ; + れ
|
||||
|
||||
//row 2
|
||||
key: : * け
|
||||
key: ] } む
|
||||
key: , < ね `
|
||||
key: . > る 。
|
||||
key: / ? め .
|
||||
key: - ろ
|
||||
key: A ち
|
||||
key: B こ
|
||||
|
||||
//row 3
|
||||
key: C そ
|
||||
key: D し
|
||||
key: E い ぃ
|
||||
key: F は
|
||||
key: G き
|
||||
key: H く
|
||||
key: I に
|
||||
key: J ま
|
||||
|
||||
//row 4
|
||||
key: K の
|
||||
key: L り
|
||||
key: M も
|
||||
key: N み
|
||||
key: O ら
|
||||
key: P せ
|
||||
key: Q た
|
||||
key: R す
|
||||
|
||||
//row 5
|
||||
key: S と
|
||||
key: T か
|
||||
key: U な
|
||||
key: V ひ
|
||||
key: W て
|
||||
key: X さ
|
||||
key: Y ん
|
||||
key: Z つ っ
|
||||
|
||||
//row 6
|
||||
key: SHIFT
|
||||
key: CTRL
|
||||
key: GRAPH
|
||||
key: CAPS
|
||||
key: かな
|
||||
key: F1 F6
|
||||
key: F2 F7
|
||||
key: F3 F8
|
||||
|
||||
//row 7
|
||||
key: F4 F9
|
||||
key: F5 F10
|
||||
key: ESC
|
||||
key: TAB
|
||||
key: STOP
|
||||
key: BS
|
||||
key: SELECT
|
||||
key: RETURN
|
||||
|
||||
//row 8
|
||||
key: SPACE
|
||||
key: CLS/HOME
|
||||
key: INS
|
||||
key: DEL
|
||||
key: ←
|
||||
key: ↑
|
||||
key: ↓
|
||||
key: →
|
||||
|
||||
//row 9
|
||||
key: *
|
||||
key: +
|
||||
key: /
|
||||
key: 0
|
||||
key: 1
|
||||
key: 2
|
||||
key: 3
|
||||
key: 4
|
||||
|
||||
//row 10
|
||||
key: 5
|
||||
key: 6
|
||||
key: 7
|
||||
key: 8
|
||||
key: 9
|
||||
key: -
|
||||
key: ,
|
||||
key: .
|
||||
|
||||
//row 11
|
||||
key:
|
||||
key: 実行
|
||||
key:
|
||||
key: 取消
|
||||
key:
|
||||
key:
|
||||
key:
|
||||
key:
|
||||
Binary file not shown.
Binary file not shown.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Binary file not shown.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Binary file not shown.
Binary file not shown.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Binary file not shown.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
Whitespace-only changes.
@@ -1,970 +0,0 @@
|
||||
database
|
||||
revision: 2020-11-09
|
||||
|
||||
//Boards (Production)
|
||||
|
||||
database
|
||||
revision: 2020-01-21
|
||||
|
||||
board: BANDAI-PT-923
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
slot type=SufamiTurbo
|
||||
rom
|
||||
map address=20-3f,a0-bf:8000-ffff mask=0x8000
|
||||
ram
|
||||
map address=60-6f,e0-ef:0000-ffff
|
||||
slot type=SufamiTurbo
|
||||
rom
|
||||
map address=40-5f,c0-df:0000-ffff mask=0x8000
|
||||
ram
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
|
||||
board: BSC-1A5B9P-01
|
||||
memory type=RAM content=Save
|
||||
map address=10-17:5000-5fff mask=0xf000
|
||||
processor identifier=MCC
|
||||
map address=00-0f:5000-5fff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
map address=20-3f,a0-bf:6000-7fff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Download
|
||||
slot type=BSMemory
|
||||
|
||||
board: BSC-1A5M-02
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f:8000-ffff mask=0xe08000 base=0x000000
|
||||
map address=20-3f:8000-ffff mask=0xe08000 base=0x100000
|
||||
map address=80-9f:8000-ffff mask=0xe08000 base=0x200000
|
||||
map address=a0-bf:8000-ffff mask=0xe08000 base=0x100000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
slot type=BSMemory
|
||||
map address=c0-ef:0000-ffff
|
||||
|
||||
board: BSC-1A7M-(01,10)
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f:8000-ffff mask=0xe08000 base=0x000000
|
||||
map address=20-3f:8000-ffff mask=0xe08000 base=0x100000
|
||||
map address=80-9f:8000-ffff mask=0xe08000 base=0x200000
|
||||
map address=a0-bf:8000-ffff mask=0xe08000 base=0x100000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
slot type=BSMemory
|
||||
map address=c0-ef:0000-ffff
|
||||
|
||||
board: BSC-1J3M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
slot type=BSMemory
|
||||
map address=20-3f,a0-bf:8000-ffff
|
||||
map address=60-7d,e0-ff:0000-ffff
|
||||
|
||||
board: BSC-1J5M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
slot type=BSMemory
|
||||
map address=20-3f,a0-bf:8000-ffff
|
||||
map address=60-7d,e0-ff:0000-ffff
|
||||
|
||||
board: BSC-1L3B-01
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
slot type=BSMemory
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: BSC-1L5B-01
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
slot type=BSMemory
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SGB-R-10
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
processor identifier=ICD revision=2
|
||||
map address=00-3f,80-bf:6000-67ff,7000-7fff
|
||||
memory type=ROM content=Boot architecture=SM83
|
||||
slot type=GameBoy
|
||||
|
||||
board: SHVC-1A0N-(01,02,10,20,30)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-1A1B-(04,05,06)
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1A1M-(01,10,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-1A3B-(11,12,13)
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1A3B-20
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-1A3M-(10,20,21,30)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-1A5B-(02,04)
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1A5M-(01,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-1B0N-(02,03,10)
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
processor architecture=uPD7725
|
||||
map address=30-3f,b0-bf:8000-ffff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-1B5B-02
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
processor architecture=uPD7725
|
||||
map address=20-3f,a0-bf:8000-ffff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-1C0N
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=60-7d,e0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1C0N5S-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=60-7d,e0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1CA0N5S-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71,f0-f1:0000-ffff
|
||||
|
||||
board: SHVC-1CA0N6S-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71,f0-f1:0000-ffff
|
||||
|
||||
board: SHVC-1CA6B-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71,f0-f1:0000-ffff
|
||||
|
||||
board: SHVC-1CB0N7S-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff mask=0x8000
|
||||
map address=40-5f:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71:0000-ffff
|
||||
|
||||
board: SHVC-1CB5B-(01,20)
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff mask=0x8000
|
||||
map address=40-5f:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71:0000-ffff
|
||||
|
||||
board: SHVC-1CB7B-01
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff mask=0x8000
|
||||
map address=40-5f:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71:0000-ffff
|
||||
|
||||
board: SHVC-1DC0N-01
|
||||
processor architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6c00-6fff,7c00-7fff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-77:0000-7fff
|
||||
memory type=ROM content=Data architecture=HG51BS169
|
||||
memory type=RAM content=Data architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6000-6bff,7000-7bff mask=0xf000
|
||||
oscillator
|
||||
|
||||
board: SHVC-1DS0B-20
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
processor architecture=uPD96050
|
||||
map address=60-67,e0-e7:0000-3fff
|
||||
memory type=ROM content=Program architecture=uPD96050
|
||||
memory type=ROM content=Data architecture=uPD96050
|
||||
memory type=RAM content=Data architecture=uPD96050
|
||||
map address=68-6f,e8-ef:0000-7fff mask=0x8000
|
||||
oscillator
|
||||
|
||||
board: SHVC-1J0N-(01,10,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
|
||||
board: SHVC-1J1M-(11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-1J3B-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-1J3M-(01,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-1J5M-(01,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-1K0N-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
processor architecture=uPD7725
|
||||
map address=00-1f,80-9f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-1K1B-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
processor architecture=uPD7725
|
||||
map address=00-1f,80-9f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-1K1X-10
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
processor architecture=uPD7725
|
||||
map address=00-1f,80-9f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-1L0N3S-01
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SHVC-1L3B-(02,11)
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SHVC-1L5B-(11,20)
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SHVC-1N0N-(01,10)
|
||||
processor identifier=SDD1
|
||||
map address=00-3f,80-bf:4800-480f
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
|
||||
board: SHVC-2A0N-01#A
|
||||
memory type=ROM content=Program
|
||||
map address=00-2f,80-af:8000-ffff mask=0x8000
|
||||
map address=40-6f,c0-ef:0000-ffff mask=0x8000
|
||||
|
||||
board: SHVC-2A0N-(01,10,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2A1M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2A3B-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2A3M-01#A
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2A3M-(01,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2A5M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-2B3B-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
processor architecture=uPD7725
|
||||
map address=60-6f,e0-ef:0000-7fff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: SHVC-2DC0N-01
|
||||
processor architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6c00-6fff,7c00-7fff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-77:0000-7fff
|
||||
memory type=ROM content=Data architecture=HG51BS169
|
||||
memory type=RAM content=Data architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6000-6bff,7000-7bff mask=0xf000
|
||||
oscillator
|
||||
|
||||
board: SHVC-2E3M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
processor identifier=OBC1
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
map address=70-71,f0-f1:6000-7fff,e000-ffff mask=0xe000
|
||||
memory type=RAM content=Save
|
||||
|
||||
board: SHVC-2J0N-(01,10,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
|
||||
board: SHVC-2J3M-(01,11,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=10-1f,30-3f,90-9f,b0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-2J5M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=10-1f,30-3f,90-9f,b0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-3J0N-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-2f,80-af:8000-ffff
|
||||
map address=40-6f,c0-ef:0000-ffff
|
||||
|
||||
board: SHVC-BA0N-(01,10)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-BA1M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-BA3M-(01,10)
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-BJ0N-(01,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
|
||||
board: SHVC-BJ1M-(10,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-BJ3M-(10,20)
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-LDH3C-01
|
||||
processor identifier=SPC7110
|
||||
map address=00-3f,80-bf:4800-483f
|
||||
map address=50,58:0000-ffff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x800000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Data
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
rtc manufacturer=Epson
|
||||
map address=00-3f,80-bf:4840-4842
|
||||
memory type=RTC content=Time manufacturer=Epson
|
||||
|
||||
board: SHVC-LJ3M-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff base=0x400000
|
||||
map address=40-7d:0000-ffff base=0x400000
|
||||
map address=80-bf:8000-ffff mask=0xc00000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=RAM content=Save
|
||||
map address=80-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SHVC-LN3B-01
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
map address=70-73:0000-ffff
|
||||
processor identifier=SDD1
|
||||
map address=00-3f,80-bf:4800-480f
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
|
||||
board: SHVC-SGB2-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
processor identifier=ICD revision=2
|
||||
map address=00-3f,80-bf:6000-67ff,7000-7fff
|
||||
memory type=ROM content=Boot architecture=SM83
|
||||
oscillator
|
||||
slot type=GameBoy
|
||||
|
||||
board: SHVC-YA0N-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: SHVC-YJ0N-01
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
|
||||
//Boards (Generic)
|
||||
|
||||
database
|
||||
revision: 2020-11-09
|
||||
|
||||
board: ARM-LOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-6f,c0-ef:0000-7fff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
processor architecture=ARM6
|
||||
map address=00-3f,80-bf:3800-38ff
|
||||
memory type=ROM content=Program architecture=ARM6
|
||||
memory type=ROM content=Data architecture=ARM6
|
||||
memory type=RAM content=Data architecture=ARM6
|
||||
oscillator
|
||||
|
||||
board: BS-HIROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
slot type=BSMemory
|
||||
map address=20-3f,a0-bf:8000-ffff
|
||||
map address=60-7d,e0-ff:0000-ffff
|
||||
|
||||
board: BS-LOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f:8000-ffff mask=0xe08000 base=0x000000
|
||||
map address=20-3f:8000-ffff mask=0xe08000 base=0x100000
|
||||
map address=80-9f:8000-ffff mask=0xe08000 base=0x200000
|
||||
map address=a0-bf:8000-ffff mask=0xe08000 base=0x100000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
slot type=BSMemory
|
||||
map address=c0-ef:0000-ffff
|
||||
|
||||
board: BS-MCC-RAM
|
||||
memory type=RAM content=Save
|
||||
map address=10-17:5000-5fff mask=0xf000
|
||||
processor identifier=MCC
|
||||
map address=00-0f:5000-5fff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
map address=20-3f,a0-bf:6000-7fff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Download
|
||||
slot type=BSMemory
|
||||
|
||||
board: BS-SA1-RAM
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
slot type=BSMemory
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: EVENT-CC92
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
processor manufacturer=NEC architecture=uPD78214
|
||||
identifier: Campus Challenge '92
|
||||
map address=c0,e0:0000
|
||||
mcu
|
||||
map address=00-1f,80-9f:8000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Level-1
|
||||
memory type=ROM content=Level-2
|
||||
memory type=ROM content=Level-3
|
||||
dip
|
||||
processor manufacturer=NEC architecture=uPD7725
|
||||
map address=20-3f,a0-bf:8000-ffff mask=0x7fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: EVENT-PF94
|
||||
memory type=RAM content=Save
|
||||
map address=30-3f,b0-bf:6000-7fff mask=0xe000
|
||||
processor manufacturer=NEC architecture=uPD78214
|
||||
identifier: PowerFest '94
|
||||
map address=10,20:6000
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Level-1
|
||||
memory type=ROM content=Level-2
|
||||
memory type=ROM content=Level-3
|
||||
dip
|
||||
processor manufacturer=NEC architecture=uPD7725
|
||||
map address=00-0f,80-8f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: EXHIROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff base=0x400000
|
||||
map address=40-7d:0000-ffff base=0x400000
|
||||
map address=80-bf:8000-ffff mask=0xc00000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
|
||||
board: EXHIROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff base=0x400000
|
||||
map address=40-7d:0000-ffff base=0x400000
|
||||
map address=80-bf:8000-ffff mask=0xc00000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: EXHIROM-RAM-SHARPRTC
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f:8000-ffff base=0x400000
|
||||
map address=40-7d:0000-ffff base=0x400000
|
||||
map address=80-bf:8000-ffff mask=0xc00000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
rtc manufacturer=Sharp
|
||||
map address=00-3f,80-bf:2800-2801
|
||||
memory type=RTC content=Time manufacturer=Sharp
|
||||
|
||||
board: EXLOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d:8000-ffff mask=0x808000 base=0x400000
|
||||
map address=80-ff:8000-ffff mask=0x808000 base=0x000000
|
||||
|
||||
board: EXLOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d:8000-ffff mask=0x808000 base=0x400000
|
||||
map address=80-ff:8000-ffff mask=0x808000 base=0x000000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: EXNEC-LOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
processor architecture=uPD96050
|
||||
map address=60-67,e0-e7:0000-3fff
|
||||
memory type=ROM content=Program architecture=uPD96050
|
||||
memory type=ROM content=Data architecture=uPD96050
|
||||
memory type=RAM content=Data architecture=uPD96050
|
||||
map address=68-6f,e8-ef:0000-7fff mask=0x8000
|
||||
oscillator
|
||||
|
||||
board: EXSPC7110-RAM-EPSONRTC
|
||||
memory type=ROM content=Expansion
|
||||
map address=40-4f:0000-ffff
|
||||
processor identifier=SPC7110
|
||||
map address=00-3f,80-bf:4800-483f
|
||||
map address=50,58:0000-ffff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x800000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Data
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
rtc manufacturer=Epson
|
||||
map address=00-3f,80-bf:4840-4842
|
||||
memory type=RTC content=Time manufacturer=Epson
|
||||
|
||||
board: GB-LOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
map address=40-7d,c0-ff:0000-7fff mask=0x8000
|
||||
processor identifier=ICD revision=2
|
||||
map address=00-3f,80-bf:6000-67ff,7000-7fff
|
||||
memory type=ROM content=Boot architecture=SM83
|
||||
oscillator
|
||||
slot type=GameBoy
|
||||
|
||||
board: GSU-RAM
|
||||
processor architecture=GSU
|
||||
map address=00-3f,80-bf:3000-34ff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
map address=40-5f,c0-df:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=70-71,f0-f1:0000-ffff
|
||||
|
||||
board: HIROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
|
||||
board: HIROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: HITACHI-LOROM
|
||||
processor architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6c00-6fff,7c00-7fff
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-77:0000-7fff
|
||||
memory type=ROM content=Data architecture=HG51BS169
|
||||
memory type=RAM content=Data architecture=HG51BS169
|
||||
map address=00-3f,80-bf:6000-6bff,7000-7bff mask=0xf000
|
||||
oscillator
|
||||
|
||||
board: LOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
|
||||
board: LOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-7d,80-ff:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
|
||||
board: LOROM-RAM#A
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff mask=0x8000
|
||||
|
||||
board: NEC-HIROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
processor architecture=uPD7725
|
||||
map address=00-1f,80-9f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: NEC-HIROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=40-7d,c0-ff:0000-ffff
|
||||
memory type=RAM content=Save
|
||||
map address=20-3f,a0-bf:6000-7fff mask=0xe000
|
||||
processor architecture=uPD7725
|
||||
map address=00-1f,80-9f:6000-7fff mask=0xfff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: NEC-LOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
processor architecture=uPD7725
|
||||
map address=30-3f,b0-bf:8000-ffff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: NEC-LOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-7fff mask=0x8000
|
||||
processor architecture=uPD7725
|
||||
map address=60-6f,e0-ef:0000-7fff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: NEC-LOROM-RAM#A
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
memory type=RAM content=Save
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
processor architecture=uPD7725
|
||||
map address=20-3f,a0-bf:8000-ffff mask=0x3fff
|
||||
memory type=ROM content=Program architecture=uPD7725
|
||||
memory type=ROM content=Data architecture=uPD7725
|
||||
memory type=RAM content=Data architecture=uPD7725
|
||||
oscillator
|
||||
|
||||
board: OBC1-LOROM-RAM
|
||||
memory type=ROM content=Program
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x8000
|
||||
processor identifier=OBC1
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
map address=70-71,f0-f1:6000-7fff,e000-ffff mask=0xe000
|
||||
memory type=RAM content=Save
|
||||
|
||||
board: SA1
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SA1-RAM
|
||||
processor architecture=W65C816S
|
||||
map address=00-3f,80-bf:2200-23ff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x408000
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff size=0x2000
|
||||
map address=40-4f:0000-ffff
|
||||
memory type=RAM content=Internal
|
||||
map address=00-3f,80-bf:3000-37ff size=0x800
|
||||
|
||||
board: SDD1
|
||||
processor identifier=SDD1
|
||||
map address=00-3f,80-bf:4800-480f
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
|
||||
board: SDD1-RAM
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
map address=70-73:0000-ffff mask=0x8000
|
||||
processor identifier=SDD1
|
||||
map address=00-3f,80-bf:4800-480f
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff
|
||||
map address=c0-ff:0000-ffff
|
||||
memory type=ROM content=Program
|
||||
|
||||
board: SPC7110-RAM
|
||||
processor identifier=SPC7110
|
||||
map address=00-3f,80-bf:4800-483f
|
||||
map address=50,58:0000-ffff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x800000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Data
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
|
||||
board: SPC7110-RAM-EPSONRTC
|
||||
processor identifier=SPC7110
|
||||
map address=00-3f,80-bf:4800-483f
|
||||
map address=50,58:0000-ffff
|
||||
mcu
|
||||
map address=00-3f,80-bf:8000-ffff mask=0x800000
|
||||
map address=c0-ff:0000-ffff mask=0xc00000
|
||||
memory type=ROM content=Program
|
||||
memory type=ROM content=Data
|
||||
memory type=RAM content=Save
|
||||
map address=00-3f,80-bf:6000-7fff mask=0xe000
|
||||
rtc manufacturer=Epson
|
||||
map address=00-3f,80-bf:4840-4842
|
||||
memory type=RTC content=Time manufacturer=Epson
|
||||
|
||||
board: ST-LOROM
|
||||
memory type=ROM content=Program
|
||||
map address=00-1f,80-9f:8000-ffff mask=0x8000
|
||||
slot type=SufamiTurbo
|
||||
rom
|
||||
map address=20-3f,a0-bf:8000-ffff mask=0x8000
|
||||
ram
|
||||
map address=60-6f,e0-ef:0000-ffff
|
||||
slot type=SufamiTurbo
|
||||
rom
|
||||
map address=40-5f,c0-df:0000-ffff mask=0x8000
|
||||
ram
|
||||
map address=70-7d,f0-ff:0000-ffff
|
||||
|
||||
Binary file not shown.
Whitespace-only changes.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,173 +0,0 @@
|
||||
ares_components(arm7tdmi armv6m m24c mos6502)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
UNITY #
|
||||
a26.cpp
|
||||
PRIMARY #
|
||||
system/system.cpp
|
||||
controller/controller.cpp
|
||||
cartridge/cartridge.cpp
|
||||
cpu/cpu.cpp
|
||||
elf/elf.cpp
|
||||
harmony/harmony.cpp
|
||||
video/video.cpp
|
||||
tia/tia.cpp
|
||||
riot/riot.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
a26.hpp
|
||||
persistent-memory.hpp
|
||||
CMakeLists.txt
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
cartridge/cartridge.hpp
|
||||
cartridge/serialization.cpp
|
||||
cartridge/slot.cpp
|
||||
cartridge/slot.hpp
|
||||
cartridge/board/atari16k.cpp
|
||||
cartridge/board/atari32k.cpp
|
||||
cartridge/board/atari8k.cpp
|
||||
cartridge/board/board.cpp
|
||||
cartridge/board/board.hpp
|
||||
cartridge/board/commavid.cpp
|
||||
cartridge/board/cdf.cpp
|
||||
cartridge/board/bus.cpp
|
||||
cartridge/board/chetiry.cpp
|
||||
cartridge/board/fa2.cpp
|
||||
cartridge/board/dpc-plus.cpp
|
||||
cartridge/board/elf.cpp
|
||||
cartridge/board/linear.cpp
|
||||
cartridge/board/movie-cart.cpp
|
||||
cartridge/board/parker-bros.cpp
|
||||
cartridge/board/tigervision.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
movie-cart/format.hpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
elf/elf.hpp
|
||||
elf/queue.cpp
|
||||
elf/parser.cpp
|
||||
elf/linker.cpp
|
||||
elf/memory.cpp
|
||||
elf/vcslib.cpp
|
||||
elf/runtime.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
harmony/harmony.hpp
|
||||
harmony/memory.cpp
|
||||
harmony/serialization.cpp
|
||||
harmony/timing.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
controller/controller.hpp
|
||||
controller/port.cpp
|
||||
controller/port.hpp
|
||||
controller/gamepad/gamepad.cpp
|
||||
controller/gamepad/gamepad.hpp
|
||||
controller/booster-grip/booster-grip.cpp
|
||||
controller/booster-grip/booster-grip.hpp
|
||||
controller/sega-genesis/sega-genesis.cpp
|
||||
controller/sega-genesis/sega-genesis.hpp
|
||||
controller/joy2b-plus/joy2b-plus.cpp
|
||||
controller/joy2b-plus/joy2b-plus.hpp
|
||||
controller/savekey/savekey.cpp
|
||||
controller/savekey/savekey.hpp
|
||||
controller/atarivox/atarivox.cpp
|
||||
controller/atarivox/atarivox.hpp
|
||||
controller/atarivox/speakjet.cpp
|
||||
controller/atarivox/speakjet.hpp
|
||||
controller/kidvid/audio.cpp
|
||||
controller/kidvid/audio.hpp
|
||||
controller/kidvid/kidvid.cpp
|
||||
controller/kidvid/kidvid.hpp
|
||||
controller/kidvid/tables.hpp
|
||||
controller/quadtari/quadtari.cpp
|
||||
controller/quadtari/quadtari.hpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
cpu/cpu.hpp
|
||||
cpu/debugger.cpp
|
||||
cpu/memory.cpp
|
||||
cpu/serialization.cpp
|
||||
cpu/timing.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
riot/io.cpp
|
||||
riot/riot.hpp
|
||||
riot/serialization.cpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
system/controls.cpp
|
||||
system/serialization.cpp
|
||||
system/system.hpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
video/color.cpp
|
||||
video/receiver.cpp
|
||||
video/serialization.cpp
|
||||
video/video.hpp
|
||||
)
|
||||
|
||||
ares_add_sources(
|
||||
CORE #
|
||||
a26
|
||||
INCLUDED #
|
||||
tia/audio.cpp
|
||||
tia/analog.cpp
|
||||
tia/ball.cpp
|
||||
tia/collision.cpp
|
||||
tia/io.cpp
|
||||
tia/missile.cpp
|
||||
tia/objects.cpp
|
||||
tia/player.cpp
|
||||
tia/playfield.cpp
|
||||
tia/priority.cpp
|
||||
tia/serialization.cpp
|
||||
tia/timing.cpp
|
||||
tia/tia.hpp
|
||||
tia/trigger.cpp
|
||||
tia/write-queue.cpp
|
||||
)
|
||||
@@ -1,9 +0,0 @@
|
||||
#include <a26/cartridge/cartridge.cpp>
|
||||
#include <a26/controller/controller.cpp>
|
||||
#include <a26/cpu/cpu.cpp>
|
||||
#include <a26/elf/elf.cpp>
|
||||
#include <a26/harmony/harmony.cpp>
|
||||
#include <a26/video/video.cpp>
|
||||
#include <a26/riot/riot.cpp>
|
||||
#include <a26/system/system.cpp>
|
||||
#include <a26/tia/tia.cpp>
|
||||
@@ -1,34 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <ares/ares.hpp>
|
||||
#include <array>
|
||||
#include <vector>
|
||||
|
||||
#include <component/processor/mos6502/mos6502.hpp>
|
||||
#include <component/processor/arm7tdmi/arm7tdmi.hpp>
|
||||
#include <component/processor/armv6m/armv6m.hpp>
|
||||
#include <component/eeprom/m24c/m24c.hpp>
|
||||
|
||||
namespace ares::Atari2600 {
|
||||
#include <ares/inline.hpp>
|
||||
auto enumerate() -> std::vector<string>;
|
||||
auto load(Node::System& node, string name) -> bool;
|
||||
|
||||
struct Region {
|
||||
static inline auto NTSC() -> bool;
|
||||
static inline auto PAL() -> bool;
|
||||
static inline auto SECAM() -> bool;
|
||||
};
|
||||
|
||||
#include <a26/movie-cart/format.hpp>
|
||||
#include <a26/persistent-memory.hpp>
|
||||
#include <a26/controller/controller.hpp>
|
||||
#include <a26/system/system.hpp>
|
||||
#include <a26/elf/elf.hpp>
|
||||
#include <a26/harmony/harmony.hpp>
|
||||
#include <a26/cartridge/cartridge.hpp>
|
||||
#include <a26/cpu/cpu.hpp>
|
||||
#include <a26/video/video.hpp>
|
||||
#include <a26/tia/tia.hpp>
|
||||
#include <a26/riot/riot.hpp>
|
||||
}
|
||||
@@ -1,48 +0,0 @@
|
||||
struct Activision8k : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n1 bank;
|
||||
bool lastAccessWasFE;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address.bit(12)) data = rom.read((bank * 0x1000) + (address & 0xfff));
|
||||
access(address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
access(address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 0;
|
||||
lastAccessWasFE = false;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
s(lastAccessWasFE);
|
||||
}
|
||||
|
||||
private:
|
||||
auto access(n16 address, n8 data) -> void {
|
||||
if(lastAccessWasFE) {
|
||||
//Released 8 KiB FE cartridges ignore D7-D6 and invert D5 to select one of two banks.
|
||||
bank = data.bit(5) ^ 1;
|
||||
lastAccessWasFE = false;
|
||||
return;
|
||||
}
|
||||
lastAccessWasFE = address == 0x01fe;
|
||||
}
|
||||
};
|
||||
@@ -1,47 +0,0 @@
|
||||
struct AmigaFC : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
u32 bankCount = 0;
|
||||
u8 activeBank = 0;
|
||||
u8 targetBank = 0;
|
||||
|
||||
auto load() -> void override {
|
||||
if(!Interface::load(rom, "program.rom")) return;
|
||||
bankCount = rom.size() / 4_KiB;
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address == 0x1ffc) activeBank = targetBank % bankCount;
|
||||
if(address.bit(12)) return rom.read(activeBank * 0x1000 + (address & 0xfff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address == 0x1ff8) {
|
||||
targetBank = data & 3;
|
||||
} else if(address == 0x1ff9) {
|
||||
auto highBank = (u32)data << 2;
|
||||
if(highBank < bankCount) {
|
||||
targetBank += highBank;
|
||||
targetBank %= bankCount;
|
||||
} else {
|
||||
targetBank = data % bankCount;
|
||||
}
|
||||
} else if(address == 0x1ffc) {
|
||||
activeBank = targetBank % bankCount;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
activeBank = 0;
|
||||
targetBank = 0;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(activeBank);
|
||||
s(targetBank);
|
||||
}
|
||||
};
|
||||
@@ -1,30 +0,0 @@
|
||||
struct Atari32In1 : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n5 game;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address.bit(12)) return rom.read(game * 0x800 + (address & 0x07ff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
//MAME's verified software-list contract cycles 32 2 KiB games on machine reset.
|
||||
//Stella instead presents the same image as frontend-selected slices; no PCB or schematic
|
||||
//presently proves the physical counter or latch behavior.
|
||||
if(reset) game++;
|
||||
else game = 0;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(game);
|
||||
}
|
||||
};
|
||||
@@ -1,50 +0,0 @@
|
||||
struct Atari16k : Interface {
|
||||
Atari16k(Cartridge& cartridge, bool hasSaraRam = false) : Interface(cartridge), saraRam(hasSaraRam) {}
|
||||
Memory::Readable<n8> rom;
|
||||
SaraRam saraRam;
|
||||
n2 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff6) bank = 0;
|
||||
if(address == 0x1ff7) bank = 1;
|
||||
if(address == 0x1ff8) bank = 2;
|
||||
if(address == 0x1ff9) bank = 3;
|
||||
|
||||
if(address.bit(12)) {
|
||||
if(saraRam.readable(address)) return saraRam.read(address, data);
|
||||
return rom.read((bank * 0x1000) + (address & 0xfff));
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff6) bank = 0;
|
||||
if(address == 0x1ff7) bank = 1;
|
||||
if(address == 0x1ff8) bank = 2;
|
||||
if(address == 0x1ff9) bank = 3;
|
||||
|
||||
saraRam.write(address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 0;
|
||||
saraRam.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
saraRam.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,58 +0,0 @@
|
||||
struct Atari32k : Interface {
|
||||
Atari32k(Cartridge& cartridge, bool hasSaraRam = false) : Interface(cartridge), saraRam(hasSaraRam) {}
|
||||
Memory::Readable<n8> rom;
|
||||
SaraRam saraRam;
|
||||
n3 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff4) bank = 0;
|
||||
if(address == 0x1ff5) bank = 1;
|
||||
if(address == 0x1ff6) bank = 2;
|
||||
if(address == 0x1ff7) bank = 3;
|
||||
if(address == 0x1ff8) bank = 4;
|
||||
if(address == 0x1ff9) bank = 5;
|
||||
if(address == 0x1ffa) bank = 6;
|
||||
if(address == 0x1ffb) bank = 7;
|
||||
|
||||
if(address.bit(12)) {
|
||||
if(saraRam.readable(address)) return saraRam.read(address, data);
|
||||
return rom.read((bank * 0x1000) + (address & 0xfff));
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff4) bank = 0;
|
||||
if(address == 0x1ff5) bank = 1;
|
||||
if(address == 0x1ff6) bank = 2;
|
||||
if(address == 0x1ff7) bank = 3;
|
||||
if(address == 0x1ff8) bank = 4;
|
||||
if(address == 0x1ff9) bank = 5;
|
||||
if(address == 0x1ffa) bank = 6;
|
||||
if(address == 0x1ffb) bank = 7;
|
||||
|
||||
saraRam.write(address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 0;
|
||||
saraRam.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
saraRam.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,46 +0,0 @@
|
||||
struct Atari8k : Interface {
|
||||
Atari8k(Cartridge& cartridge, bool hasSaraRam = false) : Interface(cartridge), saraRam(hasSaraRam) {}
|
||||
Memory::Readable<n8> rom;
|
||||
SaraRam saraRam;
|
||||
n1 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff8) bank = 0;
|
||||
if(address == 0x1ff9) bank = 1;
|
||||
|
||||
if(address.bit(12)) {
|
||||
if(saraRam.readable(address)) return saraRam.read(address, data);
|
||||
return rom.read((bank * 0x1000) + (address & 0xfff));
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
if(address == 0x1ff8) bank = 0;
|
||||
if(address == 0x1ff9) bank = 1;
|
||||
|
||||
saraRam.write(address, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 1;
|
||||
saraRam.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
saraRam.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,101 +0,0 @@
|
||||
namespace Board {
|
||||
|
||||
#include "sara-ram.cpp"
|
||||
#include "linear.cpp"
|
||||
#include "activision.cpp"
|
||||
#include "atari8k.cpp"
|
||||
#include "atari16k.cpp"
|
||||
#include "atari32k.cpp"
|
||||
#include "commavid.cpp"
|
||||
#include "parker-bros.cpp"
|
||||
#include "parker-bros-03e0.cpp"
|
||||
#include "jvp.cpp"
|
||||
#include "tigervision.cpp"
|
||||
#include "ua.cpp"
|
||||
#include "cbs-ram-plus.cpp"
|
||||
#include "m-network.cpp"
|
||||
#include "amiga-fc.cpp"
|
||||
#include "wickstead.cpp"
|
||||
#include "jane.cpp"
|
||||
#include "dpc.cpp"
|
||||
#include "mega-boy.cpp"
|
||||
#include "atari-32-in-1.cpp"
|
||||
|
||||
//Homebrew
|
||||
#include "dpc-plus.cpp"
|
||||
#include "cdf.cpp"
|
||||
#include "bus.cpp"
|
||||
#include "chetiry.cpp"
|
||||
#include "fa2.cpp"
|
||||
#include "elf.cpp"
|
||||
#include "movie-cart.cpp"
|
||||
#include "cpuwiz-4ksc.cpp"
|
||||
#include "three-e.cpp"
|
||||
#include "three-ex.cpp"
|
||||
#include "three-e-plus.cpp"
|
||||
#include "enhanced-3f.cpp"
|
||||
#include "four-a50.cpp"
|
||||
#include "ef.cpp"
|
||||
#include "mdm.cpp"
|
||||
#include "x07.cpp"
|
||||
#include "econo-banking.cpp"
|
||||
#include "superbanking.cpp"
|
||||
|
||||
auto Interface::load(Memory::Readable<n8>& memory, string name) -> bool {
|
||||
if(auto fp = pak->read(name)) {
|
||||
memory.allocate(fp->size());
|
||||
memory.load(fp);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
auto Interface::load(Memory::Writable<n8>& memory, string name) -> bool {
|
||||
if(auto fp = pak->read(name)) {
|
||||
memory.allocate(fp->size());
|
||||
memory.load(fp);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
auto Interface::save(Memory::Writable<n8>& memory, string name) -> bool {
|
||||
if(auto fp = pak->write(name)) {
|
||||
memory.save(fp);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
auto Interface::readARMMemory(Memory::Readable<n8>& rom, Memory::Writable<n8>& ram,
|
||||
u32 mode, n32 address, u32 romBase, u32 ramLimit, n32& data) -> Harmony::Access {
|
||||
u32 size = mode & ARM7TDMI::Byte ? 1 : mode & ARM7TDMI::Half ? 2 : 4;
|
||||
u32 location = address;
|
||||
auto read = [&](auto& memory, u32 offset) -> Harmony::Access {
|
||||
if(offset > memory.size() || size > memory.size() - offset) return Harmony::Access::Fault;
|
||||
data = 0;
|
||||
for(u32 byte : range(size)) data |= memory.read(offset + byte) << byte * 8;
|
||||
return Harmony::Access::Granted;
|
||||
};
|
||||
|
||||
if(location >= romBase && location < rom.size()) return read(rom, location);
|
||||
if(location >= 0x40000000 && location - 0x40000000 < ramLimit) {
|
||||
return read(ram, location - 0x40000000);
|
||||
}
|
||||
return Harmony::Access::Unmapped;
|
||||
}
|
||||
|
||||
auto Interface::writeARMMemory(Memory::Writable<n8>& ram, u32 mode, n32 address,
|
||||
u32 ramLimit, n32 data) -> Harmony::Access {
|
||||
u32 size = mode & ARM7TDMI::Byte ? 1 : mode & ARM7TDMI::Half ? 2 : 4;
|
||||
u32 location = address;
|
||||
if(location < 0x40000000 || location - 0x40000000 >= ramLimit) return Harmony::Access::Unmapped;
|
||||
auto offset = location - 0x40000000;
|
||||
if(offset > ram.size() || size > ram.size() - offset || size > ramLimit - offset) {
|
||||
return Harmony::Access::Fault;
|
||||
}
|
||||
for(u32 byte : range(size)) ram.write(offset + byte, data >> byte * 8);
|
||||
return Harmony::Access::Granted;
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,38 +0,0 @@
|
||||
namespace Board {
|
||||
|
||||
struct Interface {
|
||||
VFS::Pak pak;
|
||||
|
||||
Interface(Cartridge& cartridge) : cartridge(cartridge) {}
|
||||
virtual ~Interface() = default;
|
||||
virtual auto load() -> void {}
|
||||
virtual auto save() -> void {}
|
||||
virtual auto unload() -> void {}
|
||||
virtual auto read(n16 address, n8 data) -> n8 { return data; }
|
||||
virtual auto write(n16 address, n8 data) -> n8 { return data; }
|
||||
virtual auto power(bool reset) -> void {}
|
||||
virtual auto serialize(serializer&) -> void {}
|
||||
|
||||
virtual auto armInvocation() const -> Harmony::Invocation { return {}; }
|
||||
virtual auto readARM(u32 mode, n32 address, n32& data) -> Harmony::Access {
|
||||
return Harmony::Access::Unmapped;
|
||||
}
|
||||
virtual auto writeARM(u32 mode, n32 address, n32 data) -> Harmony::Access {
|
||||
return Harmony::Access::Unmapped;
|
||||
}
|
||||
virtual auto trapARM(u32 address, n32& value, n32 argument) -> bool { return false; }
|
||||
virtual auto stepARM(u32 clocks) -> void {}
|
||||
|
||||
auto load(Memory::Readable<n8>&, string name) -> bool;
|
||||
auto load(Memory::Writable<n8>&, string name) -> bool;
|
||||
auto save(Memory::Writable<n8>&, string name) -> bool;
|
||||
|
||||
auto readARMMemory(Memory::Readable<n8>& rom, Memory::Writable<n8>& ram,
|
||||
u32 mode, n32 address, u32 romBase, u32 ramLimit, n32& data) -> Harmony::Access;
|
||||
auto writeARMMemory(Memory::Writable<n8>& ram, u32 mode, n32 address,
|
||||
u32 ramLimit, n32 data) -> Harmony::Access;
|
||||
|
||||
Cartridge& cartridge;
|
||||
};
|
||||
|
||||
}
|
||||
@@ -1,354 +0,0 @@
|
||||
struct BUS : Interface {
|
||||
using Interface::Interface;
|
||||
|
||||
enum class Revision : u32 { BUS0, BUS1, BUS2, BUS3 };
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
Revision revision = Revision::BUS0;
|
||||
n3 bank;
|
||||
n8 mode;
|
||||
n2 fastJumpActive;
|
||||
n16 styOperand;
|
||||
n16 busOverdriveAddress;
|
||||
n16 jumpOperand;
|
||||
n32 musicCounter[3];
|
||||
n32 musicFrequency[3];
|
||||
n8 waveformShift[3];
|
||||
u16 datastreamBase = 0;
|
||||
u16 incrementBase = 0;
|
||||
u16 mapBase = 0;
|
||||
u16 waveformBase = 0;
|
||||
u32 audioPhase = 0;
|
||||
|
||||
static constexpr u8 CommunicationStream = 0x10;
|
||||
static constexpr u8 JumpStream = 0x11;
|
||||
|
||||
template<typename MemoryType>
|
||||
auto read32(u32 address, const MemoryType& memory) const -> u32 {
|
||||
if(address + 3 >= memory.size()) return 0;
|
||||
return memory.read(address + 0) << 0 | memory.read(address + 1) << 8
|
||||
| memory.read(address + 2) << 16 | memory.read(address + 3) << 24;
|
||||
}
|
||||
|
||||
auto write32(u32 address, u32 data) -> void {
|
||||
if(address + 3 >= ram.size()) return;
|
||||
for(u32 byte : range(4)) ram.write(address + byte, data >> byte * 8);
|
||||
}
|
||||
|
||||
auto scan(u32 value) const -> u32 {
|
||||
for(u32 offset = 0; offset + 3 < min<u32>(rom.size(), 3_KiB); offset += 4) {
|
||||
if(read32(offset, rom) == value) return offset;
|
||||
}
|
||||
return ~0u;
|
||||
}
|
||||
|
||||
auto detectRevision() -> void {
|
||||
auto signature = scan(0x00535542);
|
||||
if(signature == 0x07f4) revision = Revision::BUS1;
|
||||
else if(signature == 0x0778) revision = Revision::BUS2;
|
||||
else if(signature == 0x0770) revision = Revision::BUS3;
|
||||
else revision = Revision::BUS0;
|
||||
|
||||
if(revision == Revision::BUS0) {
|
||||
datastreamBase = 0x0ae0;
|
||||
incrementBase = 0x0b20;
|
||||
mapBase = 0x0b64;
|
||||
waveformBase = 0;
|
||||
} else {
|
||||
datastreamBase = revision == Revision::BUS3 ? 0x06d8 : 0x06e0;
|
||||
incrementBase = 0x0720;
|
||||
mapBase = 0x0760;
|
||||
waveformBase = 0x07f4;
|
||||
}
|
||||
}
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
detectRevision();
|
||||
ram.allocate(8_KiB, 0x00);
|
||||
harmony.load(cartridge.node);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
harmony.unload();
|
||||
}
|
||||
|
||||
auto armInvocation() const -> Harmony::Invocation override {
|
||||
if(revision == Revision::BUS0) return {.pc = 0x0c08, .lr = 0x0c00, .sp = 0x40001ffc};
|
||||
return {.pc = 0x0808, .lr = 0x0800, .sp = 0x40001ffc};
|
||||
}
|
||||
|
||||
auto readARM(u32 mode, n32 address, n32& data) -> Harmony::Access override {
|
||||
auto romBase = mode & ARM7TDMI::Prefetch ? 0x50u : 0x0750u;
|
||||
return readARMMemory(rom, ram, mode, address, romBase, min<u32>(8_KiB, ram.size()), data);
|
||||
}
|
||||
|
||||
auto writeARM(u32 mode, n32 address, n32 data) -> Harmony::Access override {
|
||||
u32 location = address;
|
||||
if(location >= 0x40000000 && location - 0x40000000 < min<u32>(8_KiB, ram.size())) {
|
||||
auto offset = location - 0x40000000;
|
||||
if(offset > 0x28 && offset < 0x06d8) return Harmony::Access::Fault;
|
||||
}
|
||||
return writeARMMemory(ram, mode, address, min<u32>(8_KiB, ram.size()), data);
|
||||
}
|
||||
|
||||
auto trapARM(u32 address, n32& voice, n32 value) -> bool override {
|
||||
constexpr u32 base = 0x06da;
|
||||
if(address < base || address > base + 12 || (address - base) % 4) return false;
|
||||
if(voice >= 3) {
|
||||
if(address == base + 8) voice = 0;
|
||||
return true;
|
||||
}
|
||||
if(address == base + 0) musicFrequency[voice] = value;
|
||||
if(address == base + 4) musicCounter[voice] = 0;
|
||||
if(address == base + 8) voice = musicCounter[voice];
|
||||
if(address == base + 12) waveformShift[voice] = min<u32>(value, 31);
|
||||
return true;
|
||||
}
|
||||
|
||||
auto stepARM(u32 clocks) -> void override {
|
||||
stepAudio(clocks);
|
||||
}
|
||||
|
||||
auto programBase() const -> u32 {
|
||||
return revision == Revision::BUS0 ? 3_KiB : 4_KiB;
|
||||
}
|
||||
|
||||
auto displayBase() const -> u32 {
|
||||
return revision == Revision::BUS0 ? 3_KiB : 2_KiB;
|
||||
}
|
||||
|
||||
auto program(u32 address) const -> n8 {
|
||||
auto offset = programBase() + u32{bank} * 4_KiB + (address & 0x0fff);
|
||||
if(offset < rom.size()) return rom.read(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
auto displayRead(u32 address) const -> u8 {
|
||||
if(displayBase() + address < ram.size()) return ram.read(displayBase() + address);
|
||||
return 0;
|
||||
}
|
||||
|
||||
auto displayWrite(u32 address, u8 data) -> void {
|
||||
if(displayBase() + address < ram.size()) ram.write(displayBase() + address, data);
|
||||
}
|
||||
|
||||
auto streamPointer(u8 index) const -> u32 {
|
||||
return read32(datastreamBase + index * 4, ram);
|
||||
}
|
||||
|
||||
auto setStreamPointer(u8 index, u32 value) -> void {
|
||||
write32(datastreamBase + index * 4, value);
|
||||
}
|
||||
|
||||
auto streamIncrement(u8 index) const -> u32 {
|
||||
return read32(incrementBase + index * 4, ram);
|
||||
}
|
||||
|
||||
auto setStreamIncrement(u8 index, u32 value) -> void {
|
||||
write32(incrementBase + index * 4, value);
|
||||
}
|
||||
|
||||
auto addressMap(u8 index) const -> u32 {
|
||||
return read32(mapBase + index * 4, ram);
|
||||
}
|
||||
|
||||
auto setAddressMap(u8 index, u32 value) -> void {
|
||||
write32(mapBase + index * 4, value);
|
||||
}
|
||||
|
||||
auto nextStreamByte(u8 index) -> u8 {
|
||||
auto pointer = streamPointer(index);
|
||||
auto result = displayRead(pointer >> 20);
|
||||
pointer += streamIncrement(index) << 12;
|
||||
setStreamPointer(index, pointer);
|
||||
return result;
|
||||
}
|
||||
|
||||
auto stepAudio(u32 clocks) -> void {
|
||||
audioPhase += clocks;
|
||||
auto ticks = audioPhase / 3500;
|
||||
audioPhase %= 3500;
|
||||
for(u32 voice : range(3)) musicCounter[voice] += u32{musicFrequency[voice]} * ticks;
|
||||
}
|
||||
|
||||
auto waveform(u32 voice) const -> u32 {
|
||||
auto address = read32(waveformBase + voice * 4, ram);
|
||||
if(address < 0x40000800) return 0;
|
||||
address -= 0x40000800;
|
||||
return address < 4_KiB ? address : 0;
|
||||
}
|
||||
|
||||
auto amplitude() -> u8 {
|
||||
if((mode & 0xf0) == 0) {
|
||||
auto address = read32(waveformBase, ram) + (u32{musicCounter[0]} >> 21);
|
||||
u8 sample = 0;
|
||||
if(address < rom.size()) sample = rom.read(address);
|
||||
else if(address >= 0x40000000 && address - 0x40000000 < ram.size()) {
|
||||
sample = ram.read(address - 0x40000000);
|
||||
}
|
||||
if(!(u32{musicCounter[0]} & 1 << 20)) sample >>= 4;
|
||||
return sample & 15;
|
||||
}
|
||||
|
||||
u32 result = 0;
|
||||
for(u32 voice : range(3)) {
|
||||
result += displayRead(waveform(voice) + (u32{musicCounter[voice]} >> waveformShift[voice]));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
auto switchBank(u32 address) -> void {
|
||||
if(revision == Revision::BUS0) {
|
||||
if(address >= 0x0ff6 && address <= 0x0ffb) bank = address - 0x0ff6;
|
||||
return;
|
||||
}
|
||||
if(address >= 0x0ff5 && address <= 0x0ffb) bank = address - 0x0ff5;
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
u32 offset = address & 0x0fff;
|
||||
u8 value = program(offset);
|
||||
|
||||
if(revision == Revision::BUS3) {
|
||||
if(fastJumpActive && jumpOperand == offset) {
|
||||
fastJumpActive--;
|
||||
jumpOperand++;
|
||||
auto pointer = streamPointer(JumpStream);
|
||||
auto result = displayRead(pointer >> 20);
|
||||
setStreamPointer(JumpStream, pointer + 0x00100000);
|
||||
return result;
|
||||
}
|
||||
if((mode & 15) == 0 && value == 0x4c && offset <= 0x0ffd
|
||||
&& program(offset + 1) == 0 && program(offset + 2) == 0) {
|
||||
fastJumpActive = 2;
|
||||
jumpOperand = offset + 1;
|
||||
return value;
|
||||
}
|
||||
jumpOperand = 0;
|
||||
}
|
||||
|
||||
if((mode & 15) == 0 && styOperand == offset) busOverdriveAddress = value;
|
||||
styOperand = 0;
|
||||
|
||||
if(revision == Revision::BUS0 && offset < 0x10) return nextStreamByte(offset);
|
||||
if((revision == Revision::BUS1 || revision == Revision::BUS2) && offset < 0x20) {
|
||||
if(offset < 0x10) return nextStreamByte(offset);
|
||||
if(offset == 0x18) return amplitude();
|
||||
return 0;
|
||||
}
|
||||
if(revision == Revision::BUS3 && offset >= 0x0fee && offset <= 0x0ff3) {
|
||||
if(offset == 0x0fee) return amplitude();
|
||||
if(offset == 0x0fef) return nextStreamByte(CommunicationStream);
|
||||
}
|
||||
|
||||
switchBank(offset);
|
||||
if((mode & 15) == 0 && value == 0x84) styOperand = offset + 1;
|
||||
return value;
|
||||
}
|
||||
|
||||
auto writeBelowCartridge(n16 address, n8 data) -> n8 {
|
||||
bool matches = address == busOverdriveAddress;
|
||||
busOverdriveAddress = 0xff;
|
||||
if(!matches) return data;
|
||||
auto target = u8(address & 0x7f);
|
||||
if(target > 0x24) return data;
|
||||
auto mappings = addressMap(target);
|
||||
auto stream = u8(mappings & 15);
|
||||
auto stuffed = u8(data) & nextStreamByte(stream);
|
||||
setAddressMap(target, mappings >> 4 | u32{stream} << 28);
|
||||
return stuffed;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return writeBelowCartridge(address, data);
|
||||
u32 offset = address & 0x0fff;
|
||||
|
||||
if(revision == Revision::BUS0) {
|
||||
auto index = u8(offset & 15);
|
||||
if(offset >= 0x10 && offset <= 0x13) {
|
||||
auto pointer = streamPointer(index);
|
||||
displayWrite(pointer >> 20, data);
|
||||
setStreamPointer(index, pointer + 0x00100000);
|
||||
}
|
||||
if(offset == 0x1b && (data == 254 || data == 255)) harmony.call(data == 254);
|
||||
if(offset == 0x1c) mode = data == 0 ? 0 : 0x0f;
|
||||
if(offset >= 0x20 && offset <= 0x2f) {
|
||||
auto pointer = streamPointer(index) << 8;
|
||||
setStreamPointer(index, pointer & 0xf0000000 | u32{data} << 20);
|
||||
}
|
||||
if(offset >= 0x30 && offset <= 0x3f) setStreamIncrement(index, data);
|
||||
switchBank(offset);
|
||||
return data;
|
||||
}
|
||||
|
||||
switchBank(offset);
|
||||
if(revision == Revision::BUS3) {
|
||||
if(offset == 0x0ff0) {
|
||||
auto pointer = streamPointer(CommunicationStream);
|
||||
displayWrite(pointer >> 20, data);
|
||||
setStreamPointer(CommunicationStream, pointer + 0x00100000);
|
||||
}
|
||||
if(offset == 0x0ff1) {
|
||||
auto pointer = streamPointer(CommunicationStream) << 8;
|
||||
setStreamPointer(CommunicationStream, pointer & 0xf0000000 | u32{data} << 20);
|
||||
}
|
||||
if(offset == 0x0ff2) mode = data;
|
||||
if(offset == 0x0ff3 && (data == 254 || data == 255)) harmony.call(data == 254);
|
||||
return data;
|
||||
}
|
||||
|
||||
if(offset >= 0x10 && offset <= 0x1f) {
|
||||
auto index = u8(offset & 15);
|
||||
if(index <= 3) {
|
||||
auto pointer = streamPointer(index);
|
||||
displayWrite(pointer >> 20, data);
|
||||
setStreamPointer(index, pointer + 0x00100000);
|
||||
}
|
||||
if(index >= 4 && index <= 7) {
|
||||
index &= 3;
|
||||
auto pointer = streamPointer(index) << 8;
|
||||
setStreamPointer(index, pointer & 0xf0000000 | u32{data} << 20);
|
||||
}
|
||||
if(index == 9) mode = data == 0 ? 0 : 0x0f;
|
||||
if(index == 10 && (data == 254 || data == 255)) harmony.call(data == 254);
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
ram.fill(0x00);
|
||||
auto driverSize = revision == Revision::BUS0 ? 3_KiB : 2_KiB;
|
||||
for(u32 offset : range(min<u32>(driverSize, rom.size()))) ram.write(offset, rom.read(offset));
|
||||
bank = revision == Revision::BUS0 ? 5 : 6;
|
||||
mode = 0xff;
|
||||
fastJumpActive = 0;
|
||||
styOperand = 0;
|
||||
busOverdriveAddress = 0;
|
||||
jumpOperand = 0;
|
||||
for(auto& item : musicCounter) item = 0;
|
||||
for(auto& item : musicFrequency) item = 0;
|
||||
for(auto& item : waveformShift) item = 27;
|
||||
audioPhase = 0;
|
||||
harmony.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
s(bank);
|
||||
s(mode);
|
||||
s(fastJumpActive);
|
||||
s(styOperand);
|
||||
s(busOverdriveAddress);
|
||||
s(jumpOperand);
|
||||
for(auto& item : musicCounter) s(item);
|
||||
for(auto& item : musicFrequency) s(item);
|
||||
for(auto& item : waveformShift) s(item);
|
||||
s(audioPhase);
|
||||
harmony.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,40 +0,0 @@
|
||||
struct CbsRamPlus : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
n2 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address >= 0x1ff8 && address <= 0x1ffa) bank = address - 0x1ff8;
|
||||
if(address >= 0x1000 && address <= 0x10ff) {
|
||||
ram.write(address & 0xff, data);
|
||||
return data;
|
||||
}
|
||||
if(address >= 0x1100 && address <= 0x11ff) return ram.read(address & 0xff);
|
||||
if(address.bit(12)) return rom.read((bank * 0x1000) + (address & 0x0fff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
if(address >= 0x1ff8 && address <= 0x1ffa) bank = address - 0x1ff8;
|
||||
if(address >= 0x1000 && address <= 0x10ff) {
|
||||
ram.write(address & 0xff, data);
|
||||
return data;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 2;
|
||||
ram.allocate(256, 0x00);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
s(ram);
|
||||
}
|
||||
};
|
||||
@@ -1,354 +0,0 @@
|
||||
struct CDF : Interface {
|
||||
using Interface::Interface;
|
||||
|
||||
enum class Revision : u32 { CDF0, CDF1, CDFJ, CDFJPlus };
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
Revision revision = Revision::CDF0;
|
||||
n3 bank;
|
||||
n8 mode;
|
||||
n2 fastJumpActive;
|
||||
n6 fastJumpStream;
|
||||
n16 immediateOperand;
|
||||
n16 jumpOperand;
|
||||
n32 musicCounter[3];
|
||||
n32 musicFrequency[3];
|
||||
n8 waveformShift[3];
|
||||
u16 datastreamBase = 0;
|
||||
u16 incrementBase = 0;
|
||||
u16 waveformBase = 0;
|
||||
u16 fastFetcherOffset = 0;
|
||||
u8 amplitudeStream = 0;
|
||||
u8 fastJumpMask = 0;
|
||||
bool ldxEnabled = false;
|
||||
bool ldyEnabled = false;
|
||||
u32 audioPhase = 0;
|
||||
|
||||
static constexpr u8 CommunicationStream = 0x20;
|
||||
static constexpr u8 JumpStreamBase = 0x21;
|
||||
static constexpr u16 NoImmediate = 0xffff;
|
||||
|
||||
template<typename MemoryType>
|
||||
auto read32(u32 address, const MemoryType& memory) const -> u32 {
|
||||
if(address + 3 >= memory.size()) return 0;
|
||||
return memory.read(address + 0) << 0 | memory.read(address + 1) << 8
|
||||
| memory.read(address + 2) << 16 | memory.read(address + 3) << 24;
|
||||
}
|
||||
|
||||
auto write32(u32 address, u32 data) -> void {
|
||||
if(address + 3 >= ram.size()) return;
|
||||
for(u32 byte : range(4)) ram.write(address + byte, data >> byte * 8);
|
||||
}
|
||||
|
||||
auto scan(u32 value) const -> u32 {
|
||||
if(rom.size() < 2_KiB) return ~0u;
|
||||
for(u32 offset = 0; offset < 2_KiB; offset += 4) {
|
||||
if(read32(offset, rom) == value) return offset;
|
||||
}
|
||||
return ~0u;
|
||||
}
|
||||
|
||||
auto detectRevision() -> void {
|
||||
auto plusSignature = scan(0x53554c50);
|
||||
if(plusSignature != ~0u && read32(plusSignature + 4, rom) == 0x4a464443
|
||||
&& read32(plusSignature + 8, rom) == 1) {
|
||||
revision = Revision::CDFJPlus;
|
||||
amplitudeStream = 0x23;
|
||||
fastJumpMask = 0xfe;
|
||||
datastreamBase = 0x0098;
|
||||
incrementBase = 0x0124;
|
||||
waveformBase = 0x01b0;
|
||||
for(u32 offset = 0; offset < 2_KiB; offset += 4) {
|
||||
auto word = read32(offset, rom);
|
||||
if(word == 0x135200a2) ldxEnabled = true;
|
||||
if(word == 0x135200a0) ldyEnabled = true;
|
||||
if((word & 0xffffff00) == 0xe2422000) fastFetcherOffset = offset;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
u8 subversion = 0;
|
||||
for(u32 offset = 0; offset + 11 < min<u32>(rom.size(), 2_KiB); offset += 4) {
|
||||
if(rom.read(offset + 0) == 'C' && rom.read(offset + 1) == 'D' && rom.read(offset + 2) == 'F'
|
||||
&& rom.read(offset + 4) == 'C' && rom.read(offset + 5) == 'D' && rom.read(offset + 6) == 'F'
|
||||
&& rom.read(offset + 8) == 'C' && rom.read(offset + 9) == 'D' && rom.read(offset + 10) == 'F') {
|
||||
subversion = rom.read(offset + 3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(subversion == 0x4a) {
|
||||
revision = Revision::CDFJ;
|
||||
amplitudeStream = 0x23;
|
||||
fastJumpMask = 0xfe;
|
||||
datastreamBase = 0x0098;
|
||||
incrementBase = 0x0124;
|
||||
waveformBase = 0x01b0;
|
||||
} else if(subversion == 0) {
|
||||
revision = Revision::CDF0;
|
||||
amplitudeStream = 0x22;
|
||||
fastJumpMask = 0xff;
|
||||
datastreamBase = 0x06e0;
|
||||
incrementBase = 0x0768;
|
||||
waveformBase = 0x07f0;
|
||||
} else {
|
||||
revision = Revision::CDF1;
|
||||
amplitudeStream = 0x22;
|
||||
fastJumpMask = 0xff;
|
||||
datastreamBase = 0x00a0;
|
||||
incrementBase = 0x0128;
|
||||
waveformBase = 0x01b0;
|
||||
}
|
||||
}
|
||||
|
||||
auto isPlus() const -> bool {
|
||||
return revision == Revision::CDFJPlus;
|
||||
}
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
detectRevision();
|
||||
ram.allocate(isPlus() ? 32_KiB : 8_KiB, 0x00);
|
||||
harmony.load(cartridge.node);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
harmony.unload();
|
||||
}
|
||||
|
||||
auto armInvocation() const -> Harmony::Invocation override {
|
||||
if(isPlus()) {
|
||||
auto address = read32(0x17f8, rom) & ~1u;
|
||||
return {.pc = address, .lr = address, .sp = read32(0x17f4, rom)};
|
||||
}
|
||||
return {.pc = 0x0808, .lr = 0x0800, .sp = 0x40001ffc};
|
||||
}
|
||||
|
||||
auto armRamLimit() const -> u32 {
|
||||
if(!isPlus()) return min<u32>(8_KiB, ram.size());
|
||||
if(rom.size() == 64_KiB || rom.size() == 128_KiB) return min<u32>(16_KiB, ram.size());
|
||||
if(rom.size() == 256_KiB || rom.size() == 512_KiB) return min<u32>(32_KiB, ram.size());
|
||||
return min<u32>(8_KiB, ram.size());
|
||||
}
|
||||
|
||||
auto readARM(u32 mode, n32 address, n32& data) -> Harmony::Access override {
|
||||
auto romBase = mode & ARM7TDMI::Prefetch ? 0x50u : 0x0750u;
|
||||
return readARMMemory(rom, ram, mode, address, romBase, armRamLimit(), data);
|
||||
}
|
||||
|
||||
auto writeProtectedARM(u32 offset) const -> bool {
|
||||
if(revision == Revision::CDF0) {
|
||||
return offset > 0x28 && offset < 0x0800 && !(offset >= 0x06e0 && offset < 0x07fc);
|
||||
}
|
||||
if(revision == Revision::CDF1) {
|
||||
return offset > 0x28 && offset < 0x0800 && !(offset >= 0x00a0 && offset < 0x01bc);
|
||||
}
|
||||
return offset > 0x28 && offset < 0x0800 && !(offset >= 0x0098 && offset < 0x01bc)
|
||||
&& !(isPlus() && offset == 0x03e0);
|
||||
}
|
||||
|
||||
auto writeARM(u32 mode, n32 address, n32 data) -> Harmony::Access override {
|
||||
u32 location = address;
|
||||
if(location >= 0x40000000 && location - 0x40000000 < armRamLimit()) {
|
||||
if(writeProtectedARM(location - 0x40000000)) return Harmony::Access::Fault;
|
||||
}
|
||||
return writeARMMemory(ram, mode, address, armRamLimit(), data);
|
||||
}
|
||||
|
||||
auto trapARM(u32 address, n32& voice, n32 value) -> bool override {
|
||||
u32 base = revision == Revision::CDF0 ? 0x06e2 : 0x0752;
|
||||
if(address < base || address > base + 12 || (address - base) % 4) return false;
|
||||
if(voice >= 3) {
|
||||
if(address == base + 8) voice = 0;
|
||||
return true;
|
||||
}
|
||||
if(address == base + 0) musicFrequency[voice] = value;
|
||||
if(address == base + 4) musicCounter[voice] = 0;
|
||||
if(address == base + 8) voice = musicCounter[voice];
|
||||
if(address == base + 12) waveformShift[voice] = min<u32>(value, 31);
|
||||
return true;
|
||||
}
|
||||
|
||||
auto stepARM(u32 clocks) -> void override {
|
||||
stepAudio(clocks);
|
||||
}
|
||||
|
||||
auto programBase() const -> u32 {
|
||||
return isPlus() ? 2_KiB : 4_KiB;
|
||||
}
|
||||
|
||||
auto program(u32 address) const -> n8 {
|
||||
u32 offset = programBase() + u32{bank} * 4_KiB + (address & 0x0fff);
|
||||
if(offset < rom.size()) return rom.read(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
auto displaySize() const -> u32 {
|
||||
return ram.size() > 2_KiB ? ram.size() - 2_KiB : 0;
|
||||
}
|
||||
|
||||
auto displayRead(u32 address) const -> u8 {
|
||||
if(address < displaySize()) return ram.read(2_KiB + address);
|
||||
return 0;
|
||||
}
|
||||
|
||||
auto displayWrite(u32 address, u8 data) -> void {
|
||||
if(address < displaySize()) ram.write(2_KiB + address, data);
|
||||
}
|
||||
|
||||
auto streamPointer(u8 index) const -> u32 {
|
||||
return read32(datastreamBase + index * 4, ram);
|
||||
}
|
||||
|
||||
auto setStreamPointer(u8 index, u32 value) -> void {
|
||||
write32(datastreamBase + index * 4, value);
|
||||
}
|
||||
|
||||
auto streamIncrement(u8 index) const -> u32 {
|
||||
return read32(incrementBase + index * 4, ram);
|
||||
}
|
||||
|
||||
auto nextStreamByte(u8 index) -> u8 {
|
||||
if(index > amplitudeStream) return 0;
|
||||
auto pointer = streamPointer(index);
|
||||
u32 location = isPlus() ? pointer >> 16 : pointer >> 20;
|
||||
auto data = displayRead(location);
|
||||
pointer += streamIncrement(index) << (isPlus() ? 8 : 12);
|
||||
setStreamPointer(index, pointer);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto waveform(u32 voice) const -> u32 {
|
||||
u32 address = read32(waveformBase + voice * 4, ram);
|
||||
address -= 0x40000800;
|
||||
if(!isPlus() && address >= 4_KiB) address &= 0x0fff;
|
||||
if(isPlus() && address >= displaySize()) return 0;
|
||||
return address;
|
||||
}
|
||||
|
||||
auto stepAudio(u32 clocks) -> void {
|
||||
audioPhase += clocks;
|
||||
auto ticks = audioPhase / 3500;
|
||||
audioPhase %= 3500;
|
||||
for(u32 voice : range(3)) musicCounter[voice] += u32{musicFrequency[voice]} * ticks;
|
||||
}
|
||||
|
||||
auto audioValue() -> u8 {
|
||||
if((mode & 0xf0) == 0) {
|
||||
u32 address = read32(waveformBase, ram) + (u32{musicCounter[0]} >> (isPlus() ? 13 : 21));
|
||||
u8 sample = 0;
|
||||
if(address < rom.size()) sample = rom.read(address);
|
||||
else if(address >= 0x40000000 && address - 0x40000000 < ram.size()) sample = ram.read(address - 0x40000000);
|
||||
if(!(u32{musicCounter[0]} & 1 << (isPlus() ? 12 : 20))) sample >>= 4;
|
||||
return sample & 15;
|
||||
}
|
||||
|
||||
u32 result = 0;
|
||||
for(u32 voice : range(3)) {
|
||||
auto location = waveform(voice) + (u32{musicCounter[voice]} >> waveformShift[voice]);
|
||||
result += displayRead(location);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
auto switchBank(u32 address) -> void {
|
||||
if(address < 0x0ff4 || address > 0x0ffb) return;
|
||||
if(isPlus()) bank = address == 0x0ffb ? 0 : address - 0x0ff4;
|
||||
else bank = address == 0x0ff4 || address == 0x0ffb ? 6 : address - 0x0ff5;
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
u32 offset = address & 0x0fff;
|
||||
u8 value = program(offset);
|
||||
|
||||
if(fastJumpActive && jumpOperand == offset) {
|
||||
fastJumpActive--;
|
||||
jumpOperand++;
|
||||
auto pointer = streamPointer(fastJumpStream);
|
||||
auto result = displayRead(isPlus() ? pointer >> 16 : pointer >> 20);
|
||||
pointer += isPlus() ? 0x00010000 : 0x00100000;
|
||||
setStreamPointer(fastJumpStream, pointer);
|
||||
return result;
|
||||
}
|
||||
|
||||
if((mode & 15) == 0 && value == 0x4c && offset <= 0x0ffd
|
||||
&& !(program(offset + 1) & fastJumpMask) && program(offset + 2) == 0) {
|
||||
fastJumpActive = 2;
|
||||
jumpOperand = offset + 1;
|
||||
fastJumpStream = program(offset + 1) + JumpStreamBase;
|
||||
return value;
|
||||
}
|
||||
jumpOperand = 0;
|
||||
|
||||
bool fastFetch = false;
|
||||
if((mode & 15) == 0 && immediateOperand == offset) {
|
||||
u8 base = 0;
|
||||
if(fastFetcherOffset && fastFetcherOffset < ram.size()) base = ram.read(fastFetcherOffset);
|
||||
fastFetch = value >= base && u32{value} <= u32{base} + amplitudeStream;
|
||||
if(fastFetch && fastFetcherOffset) value -= base;
|
||||
}
|
||||
immediateOperand = NoImmediate;
|
||||
if(fastFetch) return value == amplitudeStream ? audioValue() : nextStreamByte(value);
|
||||
|
||||
switchBank(offset);
|
||||
if((mode & 15) == 0 && (value == 0xa9 || (ldxEnabled && value == 0xa2) || (ldyEnabled && value == 0xa0))) {
|
||||
immediateOperand = offset + 1;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
u32 offset = address & 0x0fff;
|
||||
if(offset == 0x0ff0) {
|
||||
auto pointer = streamPointer(CommunicationStream);
|
||||
displayWrite(isPlus() ? pointer >> 16 : pointer >> 20, data);
|
||||
setStreamPointer(CommunicationStream, pointer + (isPlus() ? 0x00010000 : 0x00100000));
|
||||
}
|
||||
if(offset == 0x0ff1) {
|
||||
auto pointer = streamPointer(CommunicationStream) << 8;
|
||||
pointer = isPlus() ? (pointer & 0xff000000) | u32{data} << 16
|
||||
: (pointer & 0xf0000000) | u32{data} << 20;
|
||||
setStreamPointer(CommunicationStream, pointer);
|
||||
}
|
||||
if(offset == 0x0ff2) mode = data;
|
||||
if(offset == 0x0ff3 && (data == 254 || data == 255)) harmony.call(data == 254);
|
||||
switchBank(offset);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
ram.fill(0x00);
|
||||
for(u32 offset : range(min<u32>(2_KiB, rom.size()))) ram.write(offset, rom.read(offset));
|
||||
bank = isPlus() ? 0 : 6;
|
||||
mode = 0xff;
|
||||
fastJumpActive = 0;
|
||||
fastJumpStream = 0;
|
||||
immediateOperand = NoImmediate;
|
||||
jumpOperand = 0;
|
||||
for(auto& item : musicCounter) item = 0;
|
||||
for(auto& item : musicFrequency) item = 0;
|
||||
for(auto& item : waveformShift) item = 27;
|
||||
audioPhase = 0;
|
||||
harmony.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
s(bank);
|
||||
s(mode);
|
||||
s(fastJumpActive);
|
||||
s(fastJumpStream);
|
||||
s(immediateOperand);
|
||||
s(jumpOperand);
|
||||
for(auto& item : musicCounter) s(item);
|
||||
for(auto& item : musicFrequency) s(item);
|
||||
for(auto& item : waveformShift) s(item);
|
||||
s(audioPhase);
|
||||
harmony.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,212 +0,0 @@
|
||||
struct Chetiry : Interface, Thread {
|
||||
using Interface::Interface;
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Readable<n8> tunes;
|
||||
Memory::Writable<n8> ram;
|
||||
PersistentMemory persistent;
|
||||
n3 bank;
|
||||
n8 operation;
|
||||
n16 tunePosition;
|
||||
n1 ldaImmediate;
|
||||
n32 random = 0x2b435044;
|
||||
n32 musicCounter[3];
|
||||
n32 musicFrequency[3];
|
||||
n15 busyTicks;
|
||||
n1 operationCompleted;
|
||||
n1 operationSucceeded;
|
||||
n3 tune;
|
||||
|
||||
auto load() -> void override {
|
||||
Memory::Readable<n8> image;
|
||||
Interface::load(image, "program.rom");
|
||||
rom.allocate(32_KiB, 0x00);
|
||||
for(u32 offset : range(min<u32>(image.size(), 32_KiB))) rom.program(offset, image.read(offset));
|
||||
tunes.allocate(28_KiB, 0x00);
|
||||
if(image.size() > 32_KiB) {
|
||||
for(u32 offset : range(min<u32>(image.size() - 32_KiB, 28_KiB))) {
|
||||
tunes.program(offset, image.read(32_KiB + offset));
|
||||
}
|
||||
}
|
||||
persistent.load(pak, "save.eeprom", 256, 0x00);
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
auto value = rom.read(bank * 4_KiB + (address & 0x0fff));
|
||||
if(ldaImmediate && value == 0xf2) {
|
||||
ldaImmediate = 0;
|
||||
return (musicCounter[0] >> 31) + (musicCounter[1] >> 31) + (musicCounter[2] >> 31) << 2;
|
||||
}
|
||||
ldaImmediate = 0;
|
||||
|
||||
if(address <= 0x103f) {
|
||||
ram.write(address & 0x3f, data);
|
||||
return data;
|
||||
}
|
||||
if(address <= 0x107f) return readRAM(address & 0x3f);
|
||||
if(address == 0x1ff4) return operate(value);
|
||||
bankswitch(address);
|
||||
ldaImmediate = value == 0xa9;
|
||||
return value;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
if(address <= 0x103f) {
|
||||
writeRAM(address & 0x3f, data);
|
||||
return data;
|
||||
}
|
||||
if(address == 0x1ff4) {
|
||||
operate(rom.read(bank * 4_KiB + 0x0ff4));
|
||||
return data;
|
||||
}
|
||||
bankswitch(address);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto main() -> void {
|
||||
for(u32 channel : range(3)) musicCounter[channel] += musicFrequency[channel];
|
||||
if(busyTicks && !--busyTicks) {
|
||||
operationCompleted = 1;
|
||||
ram.write(0, operationSucceeded ? 0x00 : 0xff);
|
||||
}
|
||||
step(1);
|
||||
Thread::synchronize(cpu);
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
Thread::create(20'000, std::bind_front(&Chetiry::main, this));
|
||||
bank = 1;
|
||||
operation = 0;
|
||||
tunePosition = 0;
|
||||
ldaImmediate = 0;
|
||||
random = 0x2b435044;
|
||||
busyTicks = 0;
|
||||
operationCompleted = 0;
|
||||
operationSucceeded = 0;
|
||||
tune = 0;
|
||||
for(auto& counter : musicCounter) counter = 0;
|
||||
for(auto& frequency : musicFrequency) frequency = 0;
|
||||
ram.allocate(64, 0x00);
|
||||
for(u32 offset : range(4)) ram.write(offset, 0xff);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
Thread::serialize(s);
|
||||
s(bank);
|
||||
s(operation);
|
||||
s(tunePosition);
|
||||
s(ldaImmediate);
|
||||
s(random);
|
||||
s(musicCounter);
|
||||
s(musicFrequency);
|
||||
s(busyTicks);
|
||||
s(operationCompleted);
|
||||
s(operationSucceeded);
|
||||
s(tune);
|
||||
s(ram);
|
||||
}
|
||||
|
||||
private:
|
||||
static auto noteFrequency(u32 note) -> u32 {
|
||||
static constexpr u32 table[63] = {
|
||||
0, 0, 0, 11811160, 12513387, 13257490, 14045832, 14881203, 15765966,
|
||||
16703557, 17696768, 18749035, 19864009, 21045125, 22296464, 23622320,
|
||||
25026989, 26515195, 28091878, 29762191, 31531932, 33406900, 35393537,
|
||||
37498071, 39727803, 42090250, 44592927, 47244640, 50053978, 53030391,
|
||||
56183756, 59524596, 63064079, 66814014, 70787074, 74996142, 79455606,
|
||||
84180285, 89186069, 94489281, 100107957, 106060567, 112367297,
|
||||
119048977, 126128157, 133628029, 141573933, 149992288, 158911428,
|
||||
168360785, 178371925, 188978561, 200215913, 212121348, 224734593,
|
||||
238098169, 252256099, 267256058, 283147866, 299984783, 317822855,
|
||||
336721571, 356744064,
|
||||
};
|
||||
return note < 63 ? table[note] : 0;
|
||||
}
|
||||
|
||||
auto bankswitch(n16 address) -> void {
|
||||
if(address >= 0x1ff5 && address <= 0x1ffb) bank = address - 0x1ff4;
|
||||
}
|
||||
|
||||
auto readRAM(u32 address) -> n8 {
|
||||
if(address == 0) return ram.read(0);
|
||||
if(address == 1) {
|
||||
random = (random.bit(10) ? 0x10adab1e : 0) ^ (u32{random} >> 11 | u32{random} << 21);
|
||||
return random.byte(0);
|
||||
}
|
||||
if(address == 2) return tunePosition.byte(0);
|
||||
if(address == 3) return tunePosition.byte(1);
|
||||
return ram.read(address);
|
||||
}
|
||||
|
||||
auto writeRAM(u32 address, n8 data) -> void {
|
||||
if(address == 0) operation = data;
|
||||
else if(address == 1) random = 0x2b435044;
|
||||
else if(address == 2) {
|
||||
tunePosition = 0;
|
||||
for(auto& counter : musicCounter) counter = 0;
|
||||
for(auto& frequency : musicFrequency) frequency = 0;
|
||||
} else if(address == 3) {
|
||||
updateTune();
|
||||
} else {
|
||||
ram.write(address, data);
|
||||
}
|
||||
}
|
||||
|
||||
auto updateTune() -> void {
|
||||
auto position = u32{tune} * 4_KiB + u32{tunePosition} * 3;
|
||||
if(position + 2 >= tunes.size() || position + 2 >= (u32{tune} + 1) * 4_KiB) {
|
||||
tunePosition = 0;
|
||||
return;
|
||||
}
|
||||
tunePosition++;
|
||||
auto note0 = tunes.read(position + 0);
|
||||
auto note1 = tunes.read(position + 1);
|
||||
auto note2 = tunes.read(position + 2);
|
||||
if(note0) musicFrequency[0] = noteFrequency(note0);
|
||||
if(note1) musicFrequency[1] = noteFrequency(note1);
|
||||
if(note2 == 1) tunePosition = 0;
|
||||
else musicFrequency[2] = noteFrequency(note2);
|
||||
}
|
||||
|
||||
auto operate(n8 value) -> n8 {
|
||||
if(busyTicks) return value | 0x40;
|
||||
if(operationCompleted) {
|
||||
operationCompleted = 0;
|
||||
return value & ~0x40;
|
||||
}
|
||||
auto index = u32{operation} >> 4;
|
||||
auto command = u32{operation} & 15;
|
||||
operationSucceeded = 1;
|
||||
if(command == 1 && index < 7) {
|
||||
tune = index;
|
||||
tunePosition = 0;
|
||||
busyTicks = 10'000;
|
||||
} else if(command == 2 && index < 4) {
|
||||
for(u32 offset : range(4, 64)) ram.write(offset, persistent.read(index * 64 + offset));
|
||||
busyTicks = 10'000;
|
||||
} else if(command == 3 && index < 4) {
|
||||
for(u32 offset : range(4, 64)) persistent.write(index * 64 + offset, ram.read(offset));
|
||||
busyTicks = 20'000;
|
||||
} else if(command == 4) {
|
||||
persistent.erase();
|
||||
busyTicks = 20'000;
|
||||
} else {
|
||||
operationSucceeded = 0;
|
||||
ram.write(0, 0xff);
|
||||
return value & ~0x40;
|
||||
}
|
||||
return value | 0x40;
|
||||
}
|
||||
};
|
||||
@@ -1,41 +0,0 @@
|
||||
struct Commavid : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
if(address.bit(12)) {
|
||||
if(address >= 0x1000 && address <= 0x13ff) return ram.read(address & 0x3ff);
|
||||
return rom.read(address & 0xfff);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
if(address >= 0x1400 && address <= 0x17ff) {
|
||||
ram.write(address & 0x3ff, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
ram.allocate(1_KiB);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
}
|
||||
};
|
||||
@@ -1,41 +0,0 @@
|
||||
struct CPUWiz4KSC : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address < 0x1000) return data;
|
||||
if(address <= 0x107f) {
|
||||
ram.write(address & 0x7f, data);
|
||||
return data;
|
||||
}
|
||||
if(address <= 0x10ff) return ram.read(address & 0x7f);
|
||||
return rom.read(address & 0xfff);
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address < 0x1000 || address > 0x107f) return data;
|
||||
ram.write(address & 0x7f, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
ram.allocate(128, 0x00);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
}
|
||||
};
|
||||
@@ -1,276 +0,0 @@
|
||||
struct DPCPlus : Interface {
|
||||
using Interface::Interface;
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
n3 bank;
|
||||
n8 top[8];
|
||||
n8 bottom[8];
|
||||
n12 counter[8];
|
||||
n20 fractionalCounter[8];
|
||||
n8 fractionalIncrement[8];
|
||||
n32 musicCounter[3];
|
||||
n32 musicFrequency[3];
|
||||
n7 musicWaveform[3];
|
||||
n32 random;
|
||||
n1 fastFetch;
|
||||
n1 ldaImmediate;
|
||||
n8 parameter[8];
|
||||
n4 parameterPointer;
|
||||
u32 fractionalLowMask = 0x0f00ff;
|
||||
u32 audioPhase = 0;
|
||||
|
||||
auto load() -> void override {
|
||||
Memory::Readable<n8> image;
|
||||
Interface::load(image, "program.rom");
|
||||
auto size = min<u32>(image.size(), 32_KiB);
|
||||
rom.allocate(32_KiB, 0x00);
|
||||
auto destination = 32_KiB - size;
|
||||
for(u32 offset : range(size)) rom.program(destination + offset, image.read(offset));
|
||||
|
||||
if(image.size() >= 3_KiB) {
|
||||
Hash::SHA256 hash;
|
||||
for(u32 offset : range(3_KiB)) hash.input((u8)image.read(offset));
|
||||
auto driver = hash.digest();
|
||||
if(driver == "bcbe33dc02ad5104f3a3a53a856a23c57f435344790843f4fb6e746193468d0c"
|
||||
|| driver == "445ca7866a0efdf0e35076a25e963708dc630f80fd82dcdaf775fb80c8b0c58d") {
|
||||
fractionalLowMask = 0x0f0000;
|
||||
}
|
||||
}
|
||||
ram.allocate(8_KiB, 0x00);
|
||||
harmony.load(cartridge.node);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
harmony.unload();
|
||||
}
|
||||
|
||||
auto armInvocation() const -> Harmony::Invocation override {
|
||||
return {.pc = 0x0c08, .lr = 0x0c00, .sp = 0x40001ffc};
|
||||
}
|
||||
|
||||
auto readARM(u32 mode, n32 address, n32& data) -> Harmony::Access override {
|
||||
auto romBase = mode & ARM7TDMI::Prefetch ? 0x50u : 0x0c00u;
|
||||
return readARMMemory(rom, ram, mode, address, romBase, min<u32>(8_KiB, ram.size()), data);
|
||||
}
|
||||
|
||||
auto writeARM(u32 mode, n32 address, n32 data) -> Harmony::Access override {
|
||||
u32 location = address;
|
||||
if(location >= 0x40000000 && location - 0x40000000 < min<u32>(8_KiB, ram.size())) {
|
||||
auto offset = location - 0x40000000;
|
||||
if(offset > 0x28 && offset < 0x0c00) return Harmony::Access::Fault;
|
||||
}
|
||||
return writeARMMemory(ram, mode, address, min<u32>(8_KiB, ram.size()), data);
|
||||
}
|
||||
|
||||
auto stepARM(u32 clocks) -> void override {
|
||||
stepAudio(clocks);
|
||||
}
|
||||
|
||||
auto program(u32 address) const -> n8 {
|
||||
return rom.read(3_KiB + bank * 4_KiB + (address & 0x0fff));
|
||||
}
|
||||
|
||||
auto displayRead(u32 address) const -> n8 {
|
||||
return ram.read(3_KiB + (address & 0x0fff));
|
||||
}
|
||||
|
||||
auto displayWrite(u32 address, n8 data) -> void {
|
||||
ram.write(3_KiB + (address & 0x0fff), data);
|
||||
}
|
||||
|
||||
auto frequency(u32 note) const -> u32 {
|
||||
u32 address = 7_KiB + (note << 2);
|
||||
return ram.read(address + 0) << 0 | ram.read(address + 1) << 8
|
||||
| ram.read(address + 2) << 16 | ram.read(address + 3) << 24;
|
||||
}
|
||||
|
||||
auto clockRandom() -> void {
|
||||
random = (random.bit(10) ? 0x10adab1e : 0) ^ (u32{random} >> 11 | u32{random} << 21);
|
||||
}
|
||||
|
||||
auto priorRandom() -> void {
|
||||
u32 value = random;
|
||||
if(value >> 31) value ^= 0x10adab1e;
|
||||
random = value << 11 | value >> 21;
|
||||
}
|
||||
|
||||
auto stepAudio(u32 clocks) -> void {
|
||||
audioPhase += clocks;
|
||||
auto ticks = audioPhase / 3500;
|
||||
audioPhase %= 3500;
|
||||
for(u32 channel : range(3)) musicCounter[channel] += u32{musicFrequency[channel]} * ticks;
|
||||
}
|
||||
|
||||
auto amplitude() -> n8 {
|
||||
u32 value = 0;
|
||||
for(u32 channel : range(3)) {
|
||||
value += displayRead((u32{musicWaveform[channel]} << 5) + (u32{musicCounter[channel]} >> 27));
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
auto readRegister(u32 address) -> n8 {
|
||||
u32 index = address & 7;
|
||||
u32 function = address >> 3 & 7;
|
||||
u8 topDistance = u8(u32{top[index]} - (u32{counter[index]} & 0xff));
|
||||
u8 window = u8(u32{top[index]} - u32{bottom[index]});
|
||||
n8 flag = topDistance > window ? 0xff : 0x00;
|
||||
|
||||
if(function == 0) {
|
||||
if(index == 0) return clockRandom(), random.byte(0);
|
||||
if(index == 1) return priorRandom(), random.byte(0);
|
||||
if(index == 2) return random.byte(1);
|
||||
if(index == 3) return random.byte(2);
|
||||
if(index == 4) return random.byte(3);
|
||||
if(index == 5) return amplitude();
|
||||
return 0;
|
||||
}
|
||||
if(function == 1) {
|
||||
auto data = displayRead(counter[index]);
|
||||
counter[index]++;
|
||||
return data;
|
||||
}
|
||||
if(function == 2) {
|
||||
auto data = displayRead(counter[index]) & flag;
|
||||
counter[index]++;
|
||||
return data;
|
||||
}
|
||||
if(function == 3) {
|
||||
auto data = displayRead(u32{fractionalCounter[index]} >> 8);
|
||||
fractionalCounter[index] += fractionalIncrement[index];
|
||||
return data;
|
||||
}
|
||||
if(function == 4 && index < 4) return flag;
|
||||
return 0;
|
||||
}
|
||||
|
||||
auto callFunction(n8 function) -> void {
|
||||
u32 source = parameter[0] | parameter[1] << 8;
|
||||
if(function == 0) parameterPointer = 0;
|
||||
if(function == 1 || function == 2) {
|
||||
u32 destination = counter[parameter[2] & 7];
|
||||
u32 count = parameter[3];
|
||||
if(destination < 4_KiB) {
|
||||
count = min(count, 4_KiB - destination);
|
||||
if(function == 1 && source < rom.size() - 3_KiB) {
|
||||
count = min(count, rom.size() - 3_KiB - source);
|
||||
for(u32 offset : range(count)) displayWrite(destination + offset, rom.read(3_KiB + source + offset));
|
||||
}
|
||||
if(function == 2) {
|
||||
for(u32 offset : range(count)) displayWrite(destination + offset, parameter[0]);
|
||||
}
|
||||
}
|
||||
parameterPointer = 0;
|
||||
}
|
||||
if(function == 254 || function == 255) {
|
||||
harmony.call(function == 254);
|
||||
}
|
||||
}
|
||||
|
||||
auto writeRegister(u32 address, n8 data) -> void {
|
||||
u32 index = address & 7;
|
||||
u32 function = (address - 0x28) >> 3 & 15;
|
||||
if(function == 0) fractionalCounter[index] =
|
||||
(u32{fractionalCounter[index]} & fractionalLowMask) | u32{data} << 8;
|
||||
if(function == 1) fractionalCounter[index] =
|
||||
((u32{data} & 15) << 16) | (u32{fractionalCounter[index]} & 0xffff);
|
||||
if(function == 2) {
|
||||
fractionalIncrement[index] = data;
|
||||
fractionalCounter[index] = u32{fractionalCounter[index]} & 0x0fff00;
|
||||
}
|
||||
if(function == 3) top[index] = data;
|
||||
if(function == 4) bottom[index] = data;
|
||||
if(function == 5) counter[index] = (u32{counter[index]} & 0x0f00) | data;
|
||||
if(function == 6) {
|
||||
if(index == 0) fastFetch = data == 0;
|
||||
if(index == 1 && parameterPointer < 8) parameter[parameterPointer++] = data;
|
||||
if(index == 2) callFunction(data);
|
||||
if(index >= 5) musicWaveform[index - 5] = data & 0x7f;
|
||||
}
|
||||
if(function == 7) {
|
||||
counter[index]--;
|
||||
displayWrite(counter[index], data);
|
||||
}
|
||||
if(function == 8) counter[index] = ((u32{data} & 15) << 8) | (u32{counter[index]} & 0xff);
|
||||
if(function == 9) {
|
||||
if(index == 0) random = 0x2b435044;
|
||||
if(index >= 1 && index <= 4) random.byte(index - 1) = data;
|
||||
if(index >= 5) musicFrequency[index - 5] = frequency(data);
|
||||
}
|
||||
if(function == 10) {
|
||||
displayWrite(counter[index], data);
|
||||
counter[index]++;
|
||||
}
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
u32 offset = address & 0x0fff;
|
||||
n8 result = program(offset);
|
||||
|
||||
if(fastFetch && ldaImmediate && result < 0x28) offset = result;
|
||||
ldaImmediate = 0;
|
||||
if(offset < 0x28) return readRegister(offset);
|
||||
|
||||
if(offset >= 0x0ff6 && offset <= 0x0ffb) bank = offset - 0x0ff6;
|
||||
if(fastFetch) ldaImmediate = result == 0xa9;
|
||||
return result;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
u32 offset = address & 0x0fff;
|
||||
if(offset >= 0x28 && offset < 0x80) {
|
||||
writeRegister(offset, data);
|
||||
return data;
|
||||
}
|
||||
if(offset >= 0x0ff6 && offset <= 0x0ffb) bank = offset - 0x0ff6;
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
ram.fill(0x00);
|
||||
if(rom.size() >= 32_KiB) {
|
||||
for(u32 offset : range(5_KiB)) ram.write(3_KiB + offset, rom.read(27_KiB + offset));
|
||||
}
|
||||
bank = 5;
|
||||
for(auto& item : top) item = 0;
|
||||
for(auto& item : bottom) item = 0;
|
||||
for(auto& item : counter) item = 0;
|
||||
for(auto& item : fractionalCounter) item = 0;
|
||||
for(auto& item : fractionalIncrement) item = 0;
|
||||
for(auto& item : musicCounter) item = 0;
|
||||
for(auto& item : musicFrequency) item = 0;
|
||||
for(auto& item : musicWaveform) item = 0;
|
||||
for(auto& item : parameter) item = 0;
|
||||
random = 0x2b435044;
|
||||
fastFetch = 0;
|
||||
ldaImmediate = 0;
|
||||
parameterPointer = 0;
|
||||
audioPhase = 0;
|
||||
harmony.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
s(bank);
|
||||
for(auto& item : top) s(item);
|
||||
for(auto& item : bottom) s(item);
|
||||
for(auto& item : counter) s(item);
|
||||
for(auto& item : fractionalCounter) s(item);
|
||||
for(auto& item : fractionalIncrement) s(item);
|
||||
for(auto& item : musicCounter) s(item);
|
||||
for(auto& item : musicFrequency) s(item);
|
||||
for(auto& item : musicWaveform) s(item);
|
||||
s(random);
|
||||
s(fastFetch);
|
||||
s(ldaImmediate);
|
||||
for(auto& item : parameter) s(item);
|
||||
s(parameterPointer);
|
||||
s(audioPhase);
|
||||
harmony.serialize(s);
|
||||
}
|
||||
};
|
||||
@@ -1,190 +0,0 @@
|
||||
struct DPC : Interface, Thread {
|
||||
using Interface::Interface;
|
||||
|
||||
struct Fetcher {
|
||||
n8 top;
|
||||
n8 bottom;
|
||||
n8 low;
|
||||
n3 high;
|
||||
n1 flag;
|
||||
n1 musicMode;
|
||||
n1 oscillatorClock;
|
||||
} fetcher[8];
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
n1 bank;
|
||||
n8 random;
|
||||
n4 movement;
|
||||
n8 drawLatch;
|
||||
n8 drawOperand;
|
||||
n1 drawCarry;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto clockRandom() -> void {
|
||||
n1 input = !((random.bit(7) ^ random.bit(5)) ^ (random.bit(4) ^ random.bit(3)));
|
||||
random = random << 1 | input;
|
||||
}
|
||||
|
||||
auto checkFlag(u32 index) -> void {
|
||||
if(fetcher[index].low == fetcher[index].top) fetcher[index].flag = 1;
|
||||
if(fetcher[index].low == fetcher[index].bottom) fetcher[index].flag = 0;
|
||||
}
|
||||
|
||||
auto decrement(u32 index) -> void {
|
||||
if(--fetcher[index].low == 0xff) {
|
||||
fetcher[index].high--;
|
||||
if(index >= 5 && fetcher[index].musicMode) fetcher[index].low = fetcher[index].top;
|
||||
}
|
||||
checkFlag(index);
|
||||
}
|
||||
|
||||
auto display(u32 index) -> n8 {
|
||||
auto counter = fetcher[index].high << 8 | fetcher[index].low;
|
||||
return rom.read(8_KiB + (0x7ff - counter));
|
||||
}
|
||||
|
||||
auto music() -> n4 {
|
||||
static constexpr u8 amplitude[] = {0x0, 0x4, 0x5, 0x9, 0x6, 0xa, 0xb, 0xf};
|
||||
u32 state = 0;
|
||||
if(fetcher[5].musicMode && fetcher[5].flag) state |= 1;
|
||||
if(fetcher[6].musicMode && fetcher[6].flag) state |= 2;
|
||||
if(fetcher[7].musicMode && fetcher[7].flag) state |= 4;
|
||||
return amplitude[state];
|
||||
}
|
||||
|
||||
auto reverse(n8 data) -> n8 {
|
||||
n8 result;
|
||||
for(u32 bit : range(8)) result.bit(7 - bit) = data.bit(bit);
|
||||
return result;
|
||||
}
|
||||
|
||||
auto readRegister(n16 address) -> n8 {
|
||||
auto index = address & 7;
|
||||
auto function = address.bit(3, 5);
|
||||
|
||||
if(function == 0) {
|
||||
if(index < 4) return random;
|
||||
if(index <= 5) {
|
||||
drawOperand = drawLatch;
|
||||
auto sum = u32{drawOperand} + u32{fetcher[4].top};
|
||||
drawLatch = sum;
|
||||
drawCarry = sum > 0xff;
|
||||
}
|
||||
return n8{drawCarry ? movement << 4 : 0} | music();
|
||||
}
|
||||
|
||||
checkFlag(index);
|
||||
auto data = display(index);
|
||||
n8 result;
|
||||
if(function == 1) result = data;
|
||||
if(function == 2) result = fetcher[index].flag ? data : n8{0};
|
||||
if(function == 3) result = fetcher[index].flag ? n8{data << 4 | data >> 4} : n8{0};
|
||||
if(function == 4) result = fetcher[index].flag ? reverse(data) : n8{0};
|
||||
if(function == 5) result = fetcher[index].flag ? n8{data >> 1} : n8{0};
|
||||
if(function == 6) result = fetcher[index].flag ? n8{data << 1} : n8{0};
|
||||
if(function == 7) result = fetcher[index].flag ? 0xff : 0x00;
|
||||
|
||||
if(index < 5 || !fetcher[index].oscillatorClock) decrement(index);
|
||||
return result;
|
||||
}
|
||||
|
||||
auto writeRegister(n16 address, n8 data) -> void {
|
||||
auto index = address & 7;
|
||||
auto function = address.bit(3, 5);
|
||||
|
||||
if(function == 0) {
|
||||
fetcher[index].top = data;
|
||||
fetcher[index].flag = 0;
|
||||
}
|
||||
if(function == 1) {
|
||||
fetcher[index].bottom = data;
|
||||
checkFlag(index);
|
||||
}
|
||||
if(function == 2) {
|
||||
fetcher[index].low = index >= 5 && fetcher[index].musicMode ? fetcher[index].top : data;
|
||||
if(index == 4) drawLatch = data;
|
||||
checkFlag(index);
|
||||
}
|
||||
if(function == 3) {
|
||||
fetcher[index].high = data.bit(0, 2);
|
||||
if(index >= 5) {
|
||||
fetcher[index].musicMode = data.bit(4);
|
||||
fetcher[index].oscillatorClock = data.bit(5);
|
||||
if(fetcher[index].musicMode && fetcher[index].low == 0xff) {
|
||||
fetcher[index].low = fetcher[index].top;
|
||||
checkFlag(index);
|
||||
}
|
||||
}
|
||||
}
|
||||
if(function == 4) movement = data.bit(4, 7);
|
||||
if(function == 6) random = 0;
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
clockRandom();
|
||||
|
||||
if(address == 0x1ff8) bank = 0;
|
||||
if(address == 0x1ff9) bank = 1;
|
||||
if(address <= 0x103f) return readRegister(address);
|
||||
return rom.read(bank * 4_KiB + (address & 0xfff));
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
clockRandom();
|
||||
|
||||
if(address == 0x1ff8) bank = 0;
|
||||
if(address == 0x1ff9) bank = 1;
|
||||
if(address >= 0x1040 && address <= 0x107f) {
|
||||
writeRegister(address, data);
|
||||
return data;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
auto main() -> void {
|
||||
for(u32 index = 5; index < 8; index++) {
|
||||
if(fetcher[index].oscillatorClock) decrement(index);
|
||||
}
|
||||
step(1);
|
||||
Thread::synchronize(cpu);
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
Thread::create(20'000, std::bind_front(&DPC::main, this));
|
||||
//Stella latch bank 1.
|
||||
//MAME latch bank 0.
|
||||
bank = 1;
|
||||
random = 0;
|
||||
movement = 0;
|
||||
drawLatch = 0;
|
||||
drawOperand = 0;
|
||||
drawCarry = 0;
|
||||
for(auto& item : fetcher) item = {};
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
Thread::serialize(s);
|
||||
s(bank);
|
||||
s(random);
|
||||
s(movement);
|
||||
s(drawLatch);
|
||||
s(drawOperand);
|
||||
s(drawCarry);
|
||||
for(auto& item : fetcher) {
|
||||
s(item.top);
|
||||
s(item.bottom);
|
||||
s(item.low);
|
||||
s(item.high);
|
||||
s(item.flag);
|
||||
s(item.musicMode);
|
||||
s(item.oscillatorClock);
|
||||
}
|
||||
}
|
||||
};
|
||||
@@ -1,36 +0,0 @@
|
||||
struct EconoBanking : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n1 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
if(address.bit(12)) return rom.read(bank * 0x1000 + (address & 0x0fff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 0;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
}
|
||||
|
||||
private:
|
||||
auto select(n16 address) -> void {
|
||||
if((address & 0x1840) == 0x0800) bank = 0;
|
||||
if((address & 0x1840) == 0x0840) bank = 1;
|
||||
}
|
||||
};
|
||||
@@ -1,156 +0,0 @@
|
||||
struct EFBase : Interface {
|
||||
EFBase(Cartridge& cartridge, n16 hotspotMask, n16 hotspot, n6 startupBank, bool hasRam = false)
|
||||
: Interface(cartridge), hotspotMask(hotspotMask), hotspot(hotspot), startupBank(startupBank), hasRam(hasRam) {}
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
const n16 hotspotMask;
|
||||
const n16 hotspot;
|
||||
const n6 startupBank;
|
||||
const bool hasRam;
|
||||
n6 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
bankswitch(address);
|
||||
if(!address.bit(12)) return data;
|
||||
if(hasRam && address <= 0x107f) {
|
||||
ram.write(address & 0x7f, data);
|
||||
return data;
|
||||
}
|
||||
if(hasRam && address <= 0x10ff) return ram.read(address & 0x7f);
|
||||
return rom.read(bank * 0x1000 + (address & 0x0fff));
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
bankswitch(address);
|
||||
if(hasRam && address >= 0x1000 && address <= 0x107f) {
|
||||
ram.write(address & 0x7f, data);
|
||||
return data;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = startupBank;
|
||||
if(hasRam) ram.allocate(128, 0x00);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
if(hasRam) s(ram);
|
||||
}
|
||||
|
||||
private:
|
||||
auto bankswitch(n16 address) -> void {
|
||||
if((address & hotspotMask) == hotspot) bank = address - hotspot;
|
||||
}
|
||||
};
|
||||
|
||||
struct EF : EFBase {
|
||||
EF(Cartridge& cartridge) : EFBase(cartridge, 0x1ff0, 0x1fe0, 1) {}
|
||||
};
|
||||
|
||||
struct EFF : EFBase {
|
||||
EFF(Cartridge& cartridge) : EFBase(cartridge, 0x1ff0, 0x1fe0, 1) {}
|
||||
|
||||
M24C eeprom;
|
||||
PersistentMemory persistent;
|
||||
|
||||
auto load() -> void override {
|
||||
EFBase::load();
|
||||
persistent.load(pak, "save.eeprom", 2_KiB, 0xff);
|
||||
eeprom.load(M24C::Type::M24C16);
|
||||
std::copy(persistent.memory.begin(), persistent.memory.end(), std::begin(eeprom.memory));
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address >= 0x1ff0 && address <= 0x1ff4) {
|
||||
if(address == 0x1ff0) setClock(0);
|
||||
if(address == 0x1ff1) setClock(1);
|
||||
if(address == 0x1ff2) setData(0);
|
||||
if(address == 0x1ff3) setData(1);
|
||||
if(address == 0x1ff4) return rom.read(bank * 0x1000 + 0x0ff4 + eeprom.read());
|
||||
}
|
||||
return EFBase::read(address, data);
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address >= 0x1ff0 && address <= 0x1ff3) {
|
||||
if(address == 0x1ff0) setClock(0);
|
||||
if(address == 0x1ff1) setClock(1);
|
||||
if(address == 0x1ff2) setData(0);
|
||||
if(address == 0x1ff3) setData(1);
|
||||
}
|
||||
return EFBase::write(address, data);
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
EFBase::power(reset);
|
||||
eeprom.power();
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
EFBase::serialize(s);
|
||||
eeprom.serialize(s, false);
|
||||
if(s.reading()) {
|
||||
std::copy(persistent.memory.begin(), persistent.memory.end(), std::begin(eeprom.memory));
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
auto synchronizePersistent() -> void {
|
||||
persistent.replace({(const u8*)eeprom.memory, eeprom.size()});
|
||||
}
|
||||
|
||||
auto setClock(bool value) -> void {
|
||||
eeprom.clock = eeprom.clock();
|
||||
eeprom.data = eeprom.data();
|
||||
eeprom.clock = value;
|
||||
eeprom.write();
|
||||
synchronizePersistent();
|
||||
}
|
||||
|
||||
auto setData(bool value) -> void {
|
||||
eeprom.clock = eeprom.clock();
|
||||
eeprom.data = eeprom.data();
|
||||
eeprom.data = value;
|
||||
eeprom.write();
|
||||
synchronizePersistent();
|
||||
}
|
||||
};
|
||||
|
||||
struct DF : EFBase {
|
||||
DF(Cartridge& cartridge) : EFBase(cartridge, 0x1fe0, 0x1fc0, 15) {}
|
||||
};
|
||||
|
||||
struct BF : EFBase {
|
||||
BF(Cartridge& cartridge) : EFBase(cartridge, 0x1fc0, 0x1f80, 1) {}
|
||||
};
|
||||
|
||||
struct EFSC : EFBase {
|
||||
EFSC(Cartridge& cartridge) : EFBase(cartridge, 0x1ff0, 0x1fe0, 15, true) {}
|
||||
};
|
||||
|
||||
struct DFSC : EFBase {
|
||||
DFSC(Cartridge& cartridge) : EFBase(cartridge, 0x1fe0, 0x1fc0, 15, true) {}
|
||||
};
|
||||
|
||||
struct BFSC : EFBase {
|
||||
BFSC(Cartridge& cartridge) : EFBase(cartridge, 0x1fc0, 0x1f80, 15, true) {}
|
||||
};
|
||||
@@ -1,89 +0,0 @@
|
||||
struct ELFCartridge : Interface {
|
||||
ELFCartridge(Cartridge& cartridge) : Interface(cartridge) {}
|
||||
|
||||
auto fail(string reason) -> void {
|
||||
runtime.unload();
|
||||
publishedError = std::move(reason);
|
||||
ready = false;
|
||||
cartridge.node->setAttribute("error", publishedError);
|
||||
}
|
||||
|
||||
auto clearError() -> void {
|
||||
publishedError = {};
|
||||
cartridge.node->setAttribute("error");
|
||||
}
|
||||
|
||||
auto publishRuntimeError() -> bool {
|
||||
if(!runtime.faulted()) return false;
|
||||
auto error = runtime.error();
|
||||
if(error != publishedError) {
|
||||
publishedError = std::move(error);
|
||||
cartridge.node->setAttribute("error", publishedError);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
auto access(n16 address, n8 value) -> n8 {
|
||||
if(!ready || publishRuntimeError()) return value;
|
||||
return runtime.access(address, value);
|
||||
}
|
||||
|
||||
auto load() -> void override {
|
||||
image.clear();
|
||||
object = {};
|
||||
linker = {};
|
||||
ready = false;
|
||||
clearError();
|
||||
if(auto fp = pak->read("program.elf")) {
|
||||
if(fp->size() > ELF::MaximumImageSize) return fail("ELF image exceeds 16 MiB");
|
||||
image.resize(fp->size());
|
||||
fp->read({image.data(), image.size()});
|
||||
} else {
|
||||
return fail("ELF package is missing program.elf");
|
||||
}
|
||||
if(!object.parse(image)) return fail(object.error());
|
||||
if(!linker.link(object, ELF::externalSymbols(Region::NTSC()))) return fail(linker.error());
|
||||
ready = true;
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
runtime.unload();
|
||||
image.clear();
|
||||
object = {};
|
||||
linker = {};
|
||||
ready = false;
|
||||
publishedError = {};
|
||||
}
|
||||
|
||||
auto power(bool) -> void override {
|
||||
if(!ready) return;
|
||||
if(!linker.link(object, ELF::externalSymbols(Region::NTSC()))) return fail(linker.error());
|
||||
runtime.power(linker.result(), Region::NTSC());
|
||||
clearError();
|
||||
publishRuntimeError();
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 value) -> n8 override {
|
||||
return access(address, value);
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 value) -> n8 override {
|
||||
return access(address, value);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
if(!ready) return;
|
||||
runtime.serialize(s);
|
||||
if(s.reading()) {
|
||||
clearError();
|
||||
publishRuntimeError();
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<u8> image;
|
||||
ELF::Object object;
|
||||
ELF::Linker linker;
|
||||
ELF::Runtime runtime;
|
||||
bool ready = false;
|
||||
string publishedError;
|
||||
};
|
||||
@@ -1,31 +0,0 @@
|
||||
struct Enhanced3F : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n8 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
if(!address.bit(11)) return rom.read(bank * 0x800 + (address & 0x07ff));
|
||||
return rom.read(rom.size() - 0x800 + (address & 0x07ff));
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(address <= 0x003f) bank = data % (rom.size() >> 11);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
//Stella powers bank 0; MAME powers the final bank.
|
||||
bank = 0;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
}
|
||||
};
|
||||
@@ -1,118 +0,0 @@
|
||||
struct FA2 : Interface, Thread {
|
||||
using Interface::Interface;
|
||||
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
PersistentMemory persistent;
|
||||
n3 bank;
|
||||
n9 busyTicks;
|
||||
n1 operationCompleted;
|
||||
n1 operationSucceeded;
|
||||
|
||||
auto load() -> void override {
|
||||
Memory::Readable<n8> image;
|
||||
Interface::load(image, "program.rom");
|
||||
if(image.size() >= 29_KiB) {
|
||||
rom.allocate(28_KiB, 0x00);
|
||||
for(u32 offset : range(28_KiB)) rom.program(offset, image.read(1_KiB + offset));
|
||||
} else {
|
||||
rom.allocate(image.size(), 0x00);
|
||||
for(u32 offset : range(image.size())) rom.program(offset, image.read(offset));
|
||||
}
|
||||
persistent.load(pak, "save.flash", 256, 0x00);
|
||||
}
|
||||
|
||||
auto save() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto unload() -> void override {
|
||||
persistent.flush(pak);
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
if(address == 0x1ff4 && rom.size() == 28_KiB) return operate();
|
||||
bankswitch(address);
|
||||
if(address <= 0x10ff) {
|
||||
ram.write(address & 0xff, data);
|
||||
return data;
|
||||
}
|
||||
if(address <= 0x11ff) return ram.read(address & 0xff);
|
||||
return rom.read(bank * 4_KiB + (address & 0x0fff));
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) return data;
|
||||
if(address == 0x1ff4 && rom.size() == 28_KiB) {
|
||||
operate();
|
||||
return data;
|
||||
}
|
||||
bankswitch(address);
|
||||
if(address <= 0x10ff) ram.write(address & 0xff, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto main() -> void {
|
||||
if(busyTicks && !--busyTicks) {
|
||||
operationCompleted = 1;
|
||||
ram.write(255, operationSucceeded ? 0x00 : 0xff);
|
||||
}
|
||||
step(1);
|
||||
Thread::synchronize(cpu);
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
Thread::create(2'000, std::bind_front(&FA2::main, this));
|
||||
bank = 0;
|
||||
busyTicks = 0;
|
||||
operationCompleted = 0;
|
||||
operationSucceeded = 0;
|
||||
ram.allocate(256, 0x00);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
Thread::serialize(s);
|
||||
s(bank);
|
||||
s(busyTicks);
|
||||
s(operationCompleted);
|
||||
s(operationSucceeded);
|
||||
s(ram);
|
||||
}
|
||||
|
||||
private:
|
||||
auto bankswitch(n16 address) -> void {
|
||||
if(address < 0x1ff5 || address > 0x1ffb) return;
|
||||
auto selected = address - 0x1ff5;
|
||||
if(selected < rom.size() / 4_KiB) bank = selected;
|
||||
}
|
||||
|
||||
auto operate() -> n8 {
|
||||
auto value = rom.read(bank * 4_KiB + 0x0ff4);
|
||||
if(busyTicks) return value | 0x40;
|
||||
if(operationCompleted) {
|
||||
operationCompleted = 0;
|
||||
return value & ~0x40;
|
||||
}
|
||||
|
||||
operationSucceeded = 1;
|
||||
auto command = ram.read(255);
|
||||
if(command == 0) {
|
||||
persistent.erase();
|
||||
busyTicks = 202;
|
||||
} else if(command == 1) {
|
||||
for(u32 offset : range(256)) ram.write(offset, persistent.read(offset));
|
||||
busyTicks = 1;
|
||||
} else if(command == 2) {
|
||||
persistent.replace({(const u8*)ram.data(), 256});
|
||||
busyTicks = 202;
|
||||
} else {
|
||||
operationSucceeded = 0;
|
||||
ram.write(255, 0xff);
|
||||
return value & ~0x40;
|
||||
}
|
||||
return value | 0x40;
|
||||
}
|
||||
};
|
||||
@@ -1,124 +0,0 @@
|
||||
struct FourA50 : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
Memory::Writable<n8> ram;
|
||||
n16 sliceLow;
|
||||
n16 sliceMiddle;
|
||||
n16 sliceHigh;
|
||||
n1 romLow;
|
||||
n1 romMiddle;
|
||||
n1 romHigh;
|
||||
n16 lastAddress;
|
||||
n8 lastData;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) {
|
||||
checkBankSwitch(address, data);
|
||||
} else if((address & 0x1800) == 0x1000) {
|
||||
data = romLow ? readRom(sliceLow + (address & 0x07ff)) : ram.read(sliceLow + (address & 0x07ff));
|
||||
} else if(address <= 0x1dff) {
|
||||
data = romMiddle ? readRom(0x10000 + sliceMiddle + (address & 0x07ff))
|
||||
: ram.read(sliceMiddle + (address & 0x07ff));
|
||||
} else if(address <= 0x1eff) {
|
||||
data = romHigh ? readRom(0x10000 + sliceHigh + (address & 0x00ff))
|
||||
: ram.read(sliceHigh + (address & 0x00ff));
|
||||
} else {
|
||||
data = readRom(0x1ff00 + (address & 0x00ff));
|
||||
if((lastData & 0xe0) == 0x60 && (lastAddress >= 0x1000 || lastAddress < 0x0200)) {
|
||||
sliceHigh = (sliceHigh & 0xf0ff) | ((address & 0x0008) << 8) | ((address & 0x0070) << 4);
|
||||
}
|
||||
}
|
||||
lastData = data;
|
||||
lastAddress = address;
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
if(!address.bit(12)) {
|
||||
checkBankSwitch(address, data);
|
||||
} else if((address & 0x1800) == 0x1000) {
|
||||
if(!romLow) {
|
||||
ram.write(sliceLow + (address & 0x07ff), data);
|
||||
}
|
||||
} else if(address <= 0x1dff) {
|
||||
if(!romMiddle) {
|
||||
ram.write(sliceMiddle + (address & 0x07ff), data);
|
||||
}
|
||||
} else if(address <= 0x1eff) {
|
||||
if(!romHigh) {
|
||||
ram.write(sliceHigh + (address & 0x00ff), data);
|
||||
}
|
||||
} else if((lastData & 0xe0) == 0x60 && (lastAddress >= 0x1000 || lastAddress < 0x0200)) {
|
||||
sliceHigh = (sliceHigh & 0xf0ff) | ((address & 0x0008) << 8) | ((address & 0x0070) << 4);
|
||||
}
|
||||
lastData = data;
|
||||
lastAddress = address;
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
sliceLow = 0;
|
||||
sliceMiddle = 0;
|
||||
sliceHigh = 0;
|
||||
romLow = 1;
|
||||
romMiddle = 1;
|
||||
romHigh = 1;
|
||||
lastAddress = 0xffff;
|
||||
lastData = 0xff;
|
||||
ram.allocate(32_KiB, 0x00);
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(ram);
|
||||
s(sliceLow);
|
||||
s(sliceMiddle);
|
||||
s(sliceHigh);
|
||||
s(romLow);
|
||||
s(romMiddle);
|
||||
s(romHigh);
|
||||
s(lastAddress);
|
||||
s(lastData);
|
||||
}
|
||||
|
||||
private:
|
||||
auto readRom(u32 address) -> n8 {
|
||||
return rom.read(address % rom.size());
|
||||
}
|
||||
|
||||
auto bankROMLower(u16 value) -> void { romLow = 1; sliceLow = value << 11; }
|
||||
auto bankRAMLower(u16 value) -> void { romLow = 0; sliceLow = value << 11; }
|
||||
auto bankROMMiddle(u16 value) -> void { romMiddle = 1; sliceMiddle = value << 11; }
|
||||
auto bankRAMMiddle(u16 value) -> void { romMiddle = 0; sliceMiddle = value << 11; }
|
||||
auto bankROMHigh(u16 value) -> void { romHigh = 1; sliceHigh = value << 8; }
|
||||
auto bankRAMHigh(u16 value) -> void { romHigh = 0; sliceHigh = value << 8; }
|
||||
|
||||
auto checkBankSwitch(n16 address, n8 data) -> void {
|
||||
if((lastData & 0xe0) == 0x60 && (lastAddress >= 0x1000 || lastAddress < 0x0200)) {
|
||||
if((address & 0x0f00) == 0x0c00) bankROMHigh(address & 0x00ff);
|
||||
else if((address & 0x0f00) == 0x0d00) bankRAMHigh(address & 0x007f);
|
||||
else if((address & 0x0f40) == 0x0e00) bankROMLower(address & 0x001f);
|
||||
else if((address & 0x0f40) == 0x0e40) bankRAMLower(address & 0x000f);
|
||||
else if((address & 0x0f40) == 0x0f00) bankROMMiddle(address & 0x001f);
|
||||
else if((address & 0x0f50) == 0x0f40) bankRAMMiddle(address & 0x000f);
|
||||
else if((address & 0x0f00) == 0x0400) sliceLow ^= 0x0800;
|
||||
else if((address & 0x0f00) == 0x0500) sliceLow ^= 0x1000;
|
||||
else if((address & 0x0f00) == 0x0800) sliceMiddle ^= 0x0800;
|
||||
else if((address & 0x0f00) == 0x0900) sliceMiddle ^= 0x1000;
|
||||
}
|
||||
|
||||
if((address & 0x0f75) == 0x0074) bankROMHigh(data);
|
||||
else if((address & 0x0f75) == 0x0075) bankRAMHigh(data & 0x7f);
|
||||
else if((address & 0x0f7c) == 0x0078) {
|
||||
if((data & 0xf0) == 0x00) bankROMLower(data & 0x0f);
|
||||
else if((data & 0xf0) == 0x40) bankRAMLower(data & 0x0f);
|
||||
else if((data & 0xf0) == 0x90) bankROMMiddle((data & 0x0f) | 0x10);
|
||||
else if((data & 0xf0) == 0xc0) bankRAMMiddle(data & 0x0f);
|
||||
}
|
||||
}
|
||||
};
|
||||
@@ -1,38 +0,0 @@
|
||||
struct Jane : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n2 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
if(address.bit(12)) return rom.read(bank * 0x1000 + (address & 0x0fff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
bank = 1;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
}
|
||||
|
||||
private:
|
||||
auto select(n16 address) -> void {
|
||||
if(address == 0x1ff0) bank = 0;
|
||||
if(address == 0x1ff1) bank = 1;
|
||||
if(address == 0x1ff8) bank = 2;
|
||||
if(address == 0x1ff9) bank = 3;
|
||||
}
|
||||
};
|
||||
@@ -1,38 +0,0 @@
|
||||
struct JVP : Interface {
|
||||
using Interface::Interface;
|
||||
Memory::Readable<n8> rom;
|
||||
n1 bank;
|
||||
|
||||
auto load() -> void override {
|
||||
Interface::load(rom, "program.rom");
|
||||
}
|
||||
|
||||
auto read(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
if(address.bit(12)) return rom.read(bank * 0x1000 + (address & 0x0fff));
|
||||
return data;
|
||||
}
|
||||
|
||||
auto write(n16 address, n8 data) -> n8 override {
|
||||
address &= 0x1fff;
|
||||
select(address);
|
||||
return data;
|
||||
}
|
||||
|
||||
auto power(bool reset) -> void override {
|
||||
//Stella powers bank 1; MAME powers bank 0.
|
||||
bank = 0;
|
||||
}
|
||||
|
||||
auto serialize(serializer& s) -> void override {
|
||||
s(bank);
|
||||
}
|
||||
|
||||
private:
|
||||
auto select(n16 address) -> void {
|
||||
//Stella selects directly; MAME toggles either hotspot.
|
||||
if((address & 0x16e0) == 0x06a0) bank = 0;
|
||||
if((address & 0x16e0) == 0x06c0) bank = 1;
|
||||
}
|
||||
};
|
||||
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