2004-01-09 02:34:04 +00:00
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@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
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@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
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2001-03-08 23:24:26 +00:00
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@c Free Software Foundation, Inc.
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1999-05-03 07:29:11 +00:00
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MIPS-Dependent
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@chapter MIPS Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MIPS Dependent Features
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@end ifclear
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@cindex MIPS processor
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2013-06-22 16:18:45 +00:00
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@sc{gnu} @code{@value{AS}} for MIPS architectures supports several
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different MIPS processors, and MIPS ISA levels I through V, MIPS32,
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and MIPS64. For information about the MIPS instruction set, see
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@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
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For an overview of MIPS assembly conventions, see ``Appendix D:
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Assembly Language Programming'' in the same work.
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1999-05-03 07:29:11 +00:00
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@menu
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2013-06-22 16:18:45 +00:00
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* MIPS Options:: Assembler options
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2013-06-22 16:09:55 +00:00
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* MIPS Macros:: High-level assembly macros
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2013-06-22 16:02:24 +00:00
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* MIPS Symbol Sizes:: Directives to override the size of symbols
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2013-06-22 16:09:55 +00:00
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* MIPS Small Data:: Controlling the use of small data accesses
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1999-05-03 07:29:11 +00:00
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* MIPS ISA:: Directives to override the ISA level
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bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-25 18:02:34 +00:00
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* MIPS assembly options:: Directives to control code generation
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* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
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* MIPS insn:: Directive to mark data as an instruction
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2013-06-22 16:18:45 +00:00
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* MIPS Option Stack:: Directives to save and restore options
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* MIPS ASE Instruction Generation Overrides:: Directives to control
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generation of MIPS ASE instructions
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* MIPS Floating-Point:: Directives to override floating-point options
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2011-01-18 13:37:39 +00:00
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* MIPS Syntax:: MIPS specific syntactical considerations
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@end menu
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@node MIPS Options
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@section Assembler options
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The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@table @code
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@cindex @code{-G} option (MIPS)
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@item -G @var{num}
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Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
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@xref{MIPS Small Data,, Controlling the use of small data accesses}.
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1999-05-03 07:29:11 +00:00
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@cindex @code{-EB} option (MIPS)
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@cindex @code{-EL} option (MIPS)
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@cindex MIPS big-endian output
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@cindex MIPS little-endian output
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@cindex big-endian output, MIPS
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@cindex little-endian output, MIPS
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@item -EB
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@itemx -EL
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2013-06-22 16:18:45 +00:00
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Any MIPS configuration of @code{@value{AS}} can select big-endian or
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little-endian output at run time (unlike the other @sc{gnu} development
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tools, which must be configured for one or the other). Use @samp{-EB}
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to select big-endian output, and @samp{-EL} for little-endian.
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2007-04-02 14:25:27 +00:00
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@item -KPIC
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@cindex PIC selection, MIPS
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@cindex @option{-KPIC} option, MIPS
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Generate SVR4-style PIC. This option tells the assembler to generate
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SVR4-style position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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@item -mvxworks-pic
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@cindex @option{-mvxworks-pic} option, MIPS
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Generate VxWorks PIC. This option tells the assembler to generate
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VxWorks-style position-independent macro expansions.
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1999-05-03 07:29:11 +00:00
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@cindex MIPS architecture options
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@item -mips1
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@itemx -mips2
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@itemx -mips3
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@itemx -mips4
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2012-08-31 19:15:59 +00:00
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@itemx -mips5
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2000-12-01 21:35:38 +00:00
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@itemx -mips32
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[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 07:29:29 +00:00
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@itemx -mips32r2
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2000-12-02 00:55:22 +00:00
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@itemx -mips64
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 16:17:15 +00:00
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@itemx -mips64r2
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1999-05-03 07:29:11 +00:00
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Generate code for a particular MIPS Instruction Set Architecture level.
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2013-06-22 16:18:45 +00:00
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@samp{-mips1} corresponds to the R2000 and R3000 processors,
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@samp{-mips2} to the R6000 processor, @samp{-mips3} to the
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R4000 processor, and @samp{-mips4} to the R8000 and
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R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 16:17:15 +00:00
|
|
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@samp{-mips64}, and @samp{-mips64r2}
|
|
|
|
correspond to generic
|
|
|
|
@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
|
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|
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and @sc{MIPS64 Release 2}
|
|
|
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ISA processors, respectively. You can also switch
|
2000-12-12 19:36:32 +00:00
|
|
|
instruction sets during the assembly; see @ref{MIPS ISA, Directives to
|
2001-06-29 21:27:43 +00:00
|
|
|
override the ISA level}.
|
1999-05-03 07:29:11 +00:00
|
|
|
|
2000-02-22 18:55:30 +00:00
|
|
|
@item -mgp32
|
2001-08-02 10:15:24 +00:00
|
|
|
@itemx -mfp32
|
|
|
|
Some macros have different expansions for 32-bit and 64-bit registers.
|
|
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|
The register sizes are normally inferred from the ISA and ABI, but these
|
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flags force a certain group of registers to be treated as 32 bits wide at
|
|
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all times. @samp{-mgp32} controls the size of general-purpose registers
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|
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and @samp{-mfp32} controls the size of floating-point registers.
|
|
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|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
The @code{.set gp=32} and @code{.set fp=32} directives allow the size
|
|
|
|
of registers to be changed for parts of an object. The default value is
|
|
|
|
restored by @code{.set gp=default} and @code{.set fp=default}.
|
|
|
|
|
2001-08-02 10:15:24 +00:00
|
|
|
On some MIPS variants there is a 32-bit mode flag; when this flag is
|
|
|
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
|
|
|
|
save the 32-bit registers on a context switch, so it is essential never
|
|
|
|
to use the 64-bit registers.
|
2000-02-22 18:55:30 +00:00
|
|
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|
|
|
|
@item -mgp64
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
@itemx -mfp64
|
|
|
|
Assume that 64-bit registers are available. This is provided in the
|
|
|
|
interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
|
|
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|
|
The @code{.set gp=64} and @code{.set fp=64} directives allow the size
|
|
|
|
of registers to be changed for parts of an object. The default value is
|
|
|
|
restored by @code{.set gp=default} and @code{.set fp=default}.
|
2000-02-22 18:55:30 +00:00
|
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|
1999-05-03 07:29:11 +00:00
|
|
|
@item -mips16
|
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@itemx -no-mips16
|
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Generate code for the MIPS 16 processor. This is equivalent to putting
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
|
1999-05-03 07:29:11 +00:00
|
|
|
turns off this option.
|
|
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|
bfd/
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
|
|
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@item -mmicromips
|
|
|
|
@itemx -mno-micromips
|
|
|
|
Generate code for the microMIPS processor. This is equivalent to putting
|
|
|
|
@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
|
|
|
|
turns off this option. This is equivalent to putting @code{.set nomicromips}
|
|
|
|
at the start of the assembly file.
|
|
|
|
|
2006-05-08 15:57:05 +00:00
|
|
|
@item -msmartmips
|
|
|
|
@itemx -mno-smartmips
|
|
|
|
Enables the SmartMIPS extensions to the MIPS32 instruction set, which
|
|
|
|
provides a number of new instructions which target smartcard and
|
|
|
|
cryptographic applications. This is equivalent to putting
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
@code{.set smartmips} at the start of the assembly file.
|
2006-05-08 15:57:05 +00:00
|
|
|
@samp{-mno-smartmips} turns off this option.
|
|
|
|
|
2002-03-16 03:09:19 +00:00
|
|
|
@item -mips3d
|
|
|
|
@itemx -no-mips3d
|
|
|
|
Generate code for the MIPS-3D Application Specific Extension.
|
|
|
|
This tells the assembler to accept MIPS-3D instructions.
|
|
|
|
@samp{-no-mips3d} turns off this option.
|
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|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 01:17:18 +00:00
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@item -mdmx
|
|
|
|
@itemx -no-mdmx
|
|
|
|
Generate code for the MDMX Application Specific Extension.
|
|
|
|
This tells the assembler to accept MDMX instructions.
|
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|
@samp{-no-mdmx} turns off this option.
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2005-09-08 18:05:15 +00:00
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@item -mdsp
|
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@itemx -mno-dsp
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 13:28:56 +00:00
|
|
|
Generate code for the DSP Release 1 Application Specific Extension.
|
|
|
|
This tells the assembler to accept DSP Release 1 instructions.
|
2005-09-08 18:05:15 +00:00
|
|
|
@samp{-mno-dsp} turns off this option.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 13:28:56 +00:00
|
|
|
@item -mdspr2
|
|
|
|
@itemx -mno-dspr2
|
|
|
|
Generate code for the DSP Release 2 Application Specific Extension.
|
|
|
|
This option implies -mdsp.
|
|
|
|
This tells the assembler to accept DSP Release 2 instructions.
|
|
|
|
@samp{-mno-dspr2} turns off this option.
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
2005-09-06 18:53:03 +00:00
|
|
|
@item -mmt
|
|
|
|
@itemx -mno-mt
|
|
|
|
Generate code for the MT Application Specific Extension.
|
|
|
|
This tells the assembler to accept MT instructions.
|
|
|
|
@samp{-mno-mt} turns off this option.
|
|
|
|
|
gas/
* config/tc-mips.c (mips_set_options): Add ase_mcu.
(mips_opts): Initialise ase_mcu to -1.
(ISA_SUPPORTS_MCU_ASE): New macro.
(MIPS_CPU_ASE_MCU): Likewise.
(is_opcode_valid): Handle MCU.
(macro_build, macro): Likewise.
(validate_mips_insn, validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_MCU and OPTION_NO_MCU.
(md_longopts): Add mmcu and mno-mcu.
(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
(mips_after_parse_args): Handle MCU.
(s_mipsset): Likewise.
(md_show_usage): Handle MCU options.
* doc/as.texinfo: Document -mmcu and -mno-mcu options.
* doc/c-mips.texi: Likewise, and document ".set mcu" and
".set nomcu" directives.
gas/testsuite/
* gas/mips/micromips@mcu.d: New test.
* gas/mips/mcu.d: Likewise.
* gas/mips/mcu.s: New test source.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
opcodes/
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
and "mips64r2".
(print_insn_args, print_insn_micromips): Handle MCU.
* micromips-opc.c (MC): New macro.
(micromips_opcodes): Add "aclr", "aset" and "iret".
* mips-opc.c (MC): New macro.
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-08-09 15:20:03 +00:00
|
|
|
@item -mmcu
|
|
|
|
@itemx -mno-mcu
|
|
|
|
Generate code for the MCU Application Specific Extension.
|
|
|
|
This tells the assembler to accept MCU instructions.
|
|
|
|
@samp{-mno-mcu} turns off this option.
|
|
|
|
|
binutils/ChangeLog:
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 01:08:48 +00:00
|
|
|
@item -mvirt
|
|
|
|
@itemx -mno-virt
|
|
|
|
Generate code for the Virtualization Application Specific Extension.
|
|
|
|
This tells the assembler to accept Virtualization instructions.
|
|
|
|
@samp{-mno-virt} turns off this option.
|
|
|
|
|
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-25 18:02:34 +00:00
|
|
|
@item -minsn32
|
|
|
|
@itemx -mno-insn32
|
|
|
|
Only use 32-bit instruction encodings when generating code for the
|
|
|
|
microMIPS processor. This option inhibits the use of any 16-bit
|
|
|
|
instructions. This is equivalent to putting @code{.set insn32} at
|
|
|
|
the start of the assembly file. @samp{-mno-insn32} turns off this
|
|
|
|
option. This is equivalent to putting @code{.set noinsn32} at the
|
|
|
|
start of the assembly file. By default @samp{-mno-insn32} is
|
|
|
|
selected, allowing all instructions to be used.
|
|
|
|
|
2000-02-21 20:00:33 +00:00
|
|
|
@item -mfix7000
|
2002-05-30 23:38:19 +00:00
|
|
|
@itemx -mno-fix7000
|
2000-02-21 20:00:33 +00:00
|
|
|
Cause nops to be inserted if the read of the destination register
|
|
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
|
|
|
2010-02-25 11:15:48 +00:00
|
|
|
@item -mfix-loongson2f-jump
|
|
|
|
@itemx -mno-fix-loongson2f-jump
|
|
|
|
Eliminate instruction fetch from outside 256M region to work around the
|
|
|
|
Loongson2F @samp{jump} instructions. Without it, under extreme cases,
|
|
|
|
the kernel may crash. The issue has been solved in latest processor
|
|
|
|
batches, but this fix has no side effect to them.
|
|
|
|
|
|
|
|
@item -mfix-loongson2f-nop
|
|
|
|
@itemx -mno-fix-loongson2f-nop
|
|
|
|
Replace nops by @code{or at,at,zero} to work around the Loongson2F
|
2013-06-22 16:18:45 +00:00
|
|
|
@samp{nop} errata. Without it, under extreme cases, the CPU might
|
|
|
|
deadlock. The issue has been solved in later Loongson2F batches, but
|
2010-02-25 11:15:48 +00:00
|
|
|
this fix has no side effect to them.
|
|
|
|
|
2004-04-14 07:48:49 +00:00
|
|
|
@item -mfix-vr4120
|
2009-10-25 02:11:13 +00:00
|
|
|
@itemx -mno-fix-vr4120
|
2004-04-14 07:48:49 +00:00
|
|
|
Insert nops to work around certain VR4120 errata. This option is
|
|
|
|
intended to be used on GCC-generated code: it is not designed to catch
|
|
|
|
all problems in hand-written assembler code.
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 12:04:54 +00:00
|
|
|
|
2005-03-09 09:53:50 +00:00
|
|
|
@item -mfix-vr4130
|
2009-10-25 02:11:13 +00:00
|
|
|
@itemx -mno-fix-vr4130
|
2005-03-09 09:53:50 +00:00
|
|
|
Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
|
|
|
|
|
2009-04-09 15:55:59 +00:00
|
|
|
@item -mfix-24k
|
2012-04-06 22:02:43 +00:00
|
|
|
@itemx -mno-fix-24k
|
2009-04-09 15:55:59 +00:00
|
|
|
Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
|
|
|
|
|
2010-10-04 15:24:49 +00:00
|
|
|
@item -mfix-cn63xxp1
|
|
|
|
@itemx -mno-fix-cn63xxp1
|
|
|
|
Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
|
|
|
|
certain CN63XXP1 errata.
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
@item -m4010
|
|
|
|
@itemx -no-m4010
|
2013-06-22 16:18:45 +00:00
|
|
|
Generate code for the LSI R4010 chip. This tells the assembler to
|
|
|
|
accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
|
1999-05-03 07:29:11 +00:00
|
|
|
etc.), and to not schedule @samp{nop} instructions around accesses to
|
|
|
|
the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
|
|
|
|
option.
|
|
|
|
|
|
|
|
@item -m4650
|
|
|
|
@itemx -no-m4650
|
2013-06-22 16:18:45 +00:00
|
|
|
Generate code for the MIPS R4650 chip. This tells the assembler to accept
|
1999-05-03 07:29:11 +00:00
|
|
|
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
|
|
|
|
instructions around accesses to the @samp{HI} and @samp{LO} registers.
|
|
|
|
@samp{-no-m4650} turns off this option.
|
|
|
|
|
2013-01-06 17:50:21 +00:00
|
|
|
@item -m3900
|
1999-05-03 07:29:11 +00:00
|
|
|
@itemx -no-m3900
|
|
|
|
@itemx -m4100
|
|
|
|
@itemx -no-m4100
|
|
|
|
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
|
2013-06-22 16:18:45 +00:00
|
|
|
R@var{nnnn} chip. This tells the assembler to accept instructions
|
1999-05-03 07:29:11 +00:00
|
|
|
specific to that chip, and to schedule for that chip's hazards.
|
|
|
|
|
2001-06-29 21:27:43 +00:00
|
|
|
@item -march=@var{cpu}
|
2013-06-22 16:18:45 +00:00
|
|
|
Generate code for a particular MIPS CPU. It is exactly equivalent to
|
1999-05-03 07:29:11 +00:00
|
|
|
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
|
|
|
|
understood. Valid @var{cpu} value are:
|
|
|
|
|
|
|
|
@quotation
|
|
|
|
2000,
|
|
|
|
3000,
|
|
|
|
3900,
|
|
|
|
4000,
|
|
|
|
4010,
|
|
|
|
4100,
|
|
|
|
4111,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 12:04:54 +00:00
|
|
|
vr4120,
|
|
|
|
vr4130,
|
|
|
|
vr4181,
|
1999-05-03 07:29:11 +00:00
|
|
|
4300,
|
|
|
|
4400,
|
|
|
|
4600,
|
|
|
|
4650,
|
|
|
|
5000,
|
2000-06-16 19:11:27 +00:00
|
|
|
rm5200,
|
|
|
|
rm5230,
|
|
|
|
rm5231,
|
|
|
|
rm5261,
|
|
|
|
rm5721,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 12:04:54 +00:00
|
|
|
vr5400,
|
|
|
|
vr5500,
|
1999-05-03 07:29:11 +00:00
|
|
|
6000,
|
2000-06-16 19:11:27 +00:00
|
|
|
rm7000,
|
1999-05-03 07:29:11 +00:00
|
|
|
8000,
|
2003-07-15 09:02:59 +00:00
|
|
|
rm9000,
|
2000-12-01 21:35:38 +00:00
|
|
|
10000,
|
2001-07-04 12:32:07 +00:00
|
|
|
12000,
|
* aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
bfd_mach_mips16000.
* archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd-in2.h: Regenerate.
* cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* doc/c-mips.texi: Add entries for 14000, 16000.
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
2008-11-28 18:02:17 +00:00
|
|
|
14000,
|
|
|
|
16000,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
4kc,
|
|
|
|
4km,
|
|
|
|
4kp,
|
|
|
|
4ksc,
|
|
|
|
4kec,
|
|
|
|
4kem,
|
|
|
|
4kep,
|
|
|
|
4ksd,
|
|
|
|
m4k,
|
|
|
|
m4kp,
|
2011-08-09 15:25:32 +00:00
|
|
|
m14k,
|
|
|
|
m14kc,
|
2011-11-16 12:21:35 +00:00
|
|
|
m14ke,
|
|
|
|
m14kec,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
24kc,
|
2007-07-04 19:55:18 +00:00
|
|
|
24kf2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
24kf,
|
2007-07-04 19:55:18 +00:00
|
|
|
24kf1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
24kec,
|
2007-07-04 19:55:18 +00:00
|
|
|
24kef2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
24kef,
|
2007-07-04 19:55:18 +00:00
|
|
|
24kef1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
34kc,
|
2007-07-04 19:55:18 +00:00
|
|
|
34kf2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
34kf,
|
2007-07-04 19:55:18 +00:00
|
|
|
34kf1_1,
|
2012-08-01 19:59:43 +00:00
|
|
|
34kn,
|
2007-02-20 15:03:45 +00:00
|
|
|
74kc,
|
2007-07-04 19:55:18 +00:00
|
|
|
74kf2_1,
|
2007-02-20 15:03:45 +00:00
|
|
|
74kf,
|
2007-07-04 19:55:18 +00:00
|
|
|
74kf1_1,
|
|
|
|
74kf3_2,
|
2009-08-05 00:44:01 +00:00
|
|
|
1004kc,
|
|
|
|
1004kf2_1,
|
|
|
|
1004kf,
|
|
|
|
1004kf1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
5kc,
|
|
|
|
5kf,
|
|
|
|
20kc,
|
|
|
|
25kf,
|
2006-11-06 15:05:40 +00:00
|
|
|
sb1,
|
2007-11-29 12:23:44 +00:00
|
|
|
sb1a,
|
|
|
|
loongson2e,
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
|
|
|
loongson2f,
|
2010-11-11 10:23:39 +00:00
|
|
|
loongson3a,
|
bfd:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
* archures.c (bfd_mach_mips_xlr): Define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_xlr): Define.
(arch_info_struct): Add XLR entry.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
(mips_set_isa_flags): Handle bfd_mach_mips_xlr
(mips_mach_extensions): Add XLR entry.
binutils:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
gas:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
M_MSGWAIT and M_MSGWAIT_T.
(mips_cpu_info_table): Add XLR entry.
* doc/c-mips.texi (-march): Document xlr.
gas/testsuite:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* gas/mips/mips.exp (xlr): New architecture.
(xlr-ext): Run test.
* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
include/elf:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (E_MIPS_MACH_XLR): Define.
include/opcode:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
opcodes:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
(mips_arch_choices): Add XLR entry.
* mips-opc.c (XLR): Define.
(mips_builtin_opcodes): Add XLR instructions.
2009-02-03 18:16:04 +00:00
|
|
|
octeon,
|
2011-11-29 20:28:55 +00:00
|
|
|
octeon+,
|
bfd:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* archures.c (bfd_mach_mips_octeon2): New macro
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsocteon2): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeon2.
* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
(mips_mach_extensions): Add bfd_mach_mips_octeon2.
gas:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
(mips_cpu_info_table): Add Octeon2.
* doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.
gas/testsuite:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips.exp: Add Octeon2 for an architecture.
Run octeon2 test.
* gas/mips/octeon2.d: New file.
* gas/mips/octeon2.s: New file.
include/opcode:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
(CPU_OCTEON2): New macro.
(OPCODE_IS_MEMBER): Add Octeon2.
opcodes:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add Octeon2.
For "octeon+", just include OcteonP for the insn.
* mips-opc.c (IOCT): Include Octeon2.
(IOCTP): Include Octeon2.
(IOCT2): New macro.
(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
loads are, and add IOCT2 to them.
Add "lbx" and "lhux".
Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
Add "zcb" and "zcbt".
2011-12-08 20:47:27 +00:00
|
|
|
octeon2,
|
2012-03-24 01:09:28 +00:00
|
|
|
xlr,
|
|
|
|
xlp
|
1999-05-03 07:29:11 +00:00
|
|
|
@end quotation
|
|
|
|
|
2007-07-04 19:55:18 +00:00
|
|
|
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
|
|
|
|
accepted as synonyms for @samp{@var{n}f1_1}. These values are
|
|
|
|
deprecated.
|
|
|
|
|
2001-06-29 21:27:43 +00:00
|
|
|
@item -mtune=@var{cpu}
|
2013-06-22 16:18:45 +00:00
|
|
|
Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
|
2001-06-29 21:27:43 +00:00
|
|
|
identical to @samp{-march=@var{cpu}}.
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 09:48:07 +00:00
|
|
|
@item -mabi=@var{abi}
|
|
|
|
Record which ABI the source code uses. The recognized arguments
|
|
|
|
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
|
1999-05-03 07:29:11 +00:00
|
|
|
|
2005-03-04 09:51:11 +00:00
|
|
|
@item -msym32
|
|
|
|
@itemx -mno-sym32
|
|
|
|
@cindex -msym32
|
|
|
|
@cindex -mno-sym32
|
|
|
|
Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
|
2013-06-22 16:02:24 +00:00
|
|
|
the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
|
2005-03-04 09:51:11 +00:00
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
@cindex @code{-nocpp} ignored (MIPS)
|
|
|
|
@item -nocpp
|
|
|
|
This option is ignored. It is accepted for command-line compatibility with
|
|
|
|
other assemblers, which use it to turn off C style preprocessing. With
|
|
|
|
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
|
|
|
|
@sc{gnu} assembler itself never runs the C preprocessor.
|
|
|
|
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
|
|
|
@item -msoft-float
|
|
|
|
@itemx -mhard-float
|
|
|
|
Disable or enable floating-point instructions. Note that by default
|
|
|
|
floating-point instructions are always allowed even with CPU targets
|
|
|
|
that don't have support for these instructions.
|
|
|
|
|
|
|
|
@item -msingle-float
|
|
|
|
@itemx -mdouble-float
|
|
|
|
Disable or enable double-precision floating-point operations. Note
|
|
|
|
that by default double-precision floating-point operations are always
|
|
|
|
allowed even with CPU targets that don't have support for these
|
|
|
|
operations.
|
|
|
|
|
2000-07-14 22:23:33 +00:00
|
|
|
@item --construct-floats
|
|
|
|
@itemx --no-construct-floats
|
|
|
|
The @code{--no-construct-floats} option disables the construction of
|
|
|
|
double width floating point constants by loading the two halves of the
|
|
|
|
value into the two single width floating point registers that make up
|
|
|
|
the double width register. This feature is useful if the processor
|
|
|
|
support the FR bit in its status register, and this bit is known (by
|
|
|
|
the programmer) to be set. This bit prevents the aliasing of the double
|
|
|
|
width register by the single width registers.
|
|
|
|
|
2000-07-15 15:09:13 +00:00
|
|
|
By default @code{--construct-floats} is selected, allowing construction
|
2000-07-14 22:23:33 +00:00
|
|
|
of these floating point constants.
|
|
|
|
|
2013-06-10 18:15:48 +00:00
|
|
|
@item --relax-branch
|
|
|
|
@itemx --no-relax-branch
|
|
|
|
The @samp{--relax-branch} option enables the relaxation of out-of-range
|
|
|
|
branches. Any branches whose target cannot be reached directly are
|
|
|
|
converted to a small instruction sequence including an inverse-condition
|
|
|
|
branch to the physically next instruction, and a jump to the original
|
|
|
|
target is inserted between the two instructions. In PIC code the jump
|
|
|
|
will involve further instructions for address calculation.
|
|
|
|
|
|
|
|
The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
|
|
|
|
@code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
|
|
|
|
relaxation, because they have no complementing counterparts. They could
|
|
|
|
be relaxed with the use of a longer sequence involving another branch,
|
|
|
|
however this has not been implemented and if their target turns out of
|
|
|
|
reach, they produce an error even if branch relaxation is enabled.
|
|
|
|
|
|
|
|
Also no @sc{mips16} branches are ever relaxed.
|
|
|
|
|
|
|
|
By default @samp{--no-relax-branch} is selected, causing any out-of-range
|
|
|
|
branches to produce an error.
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
@item --trap
|
|
|
|
@itemx --no-break
|
|
|
|
@c FIXME! (1) reflect these options (next item too) in option summaries;
|
|
|
|
@c (2) stop teasing, say _which_ instructions expanded _how_.
|
|
|
|
@code{@value{AS}} automatically macro expands certain division and
|
|
|
|
multiplication instructions to check for overflow and division by zero. This
|
|
|
|
option causes @code{@value{AS}} to generate code to take a trap exception
|
|
|
|
rather than a break exception when an error is detected. The trap instructions
|
|
|
|
are only supported at Instruction Set Architecture level 2 and higher.
|
|
|
|
|
|
|
|
@item --break
|
|
|
|
@itemx --no-trap
|
|
|
|
Generate code to take a break exception rather than a trap exception when an
|
|
|
|
error is detected. This is the default.
|
2001-06-11 20:40:36 +00:00
|
|
|
|
2003-07-28 20:06:27 +00:00
|
|
|
@item -mpdr
|
|
|
|
@itemx -mno-pdr
|
|
|
|
Control generation of @code{.pdr} sections. Off by default on IRIX, on
|
|
|
|
elsewhere.
|
2004-12-10 19:48:21 +00:00
|
|
|
|
|
|
|
@item -mshared
|
|
|
|
@itemx -mno-shared
|
|
|
|
When generating code using the Unix calling conventions (selected by
|
|
|
|
@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
|
|
|
|
which can go into a shared library. The @samp{-mno-shared} option
|
|
|
|
tells gas to generate code which uses the calling convention, but can
|
|
|
|
not go into a shared library. The resulting code is slightly more
|
|
|
|
efficient. This option only affects the handling of the
|
|
|
|
@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
|
1999-05-03 07:29:11 +00:00
|
|
|
@end table
|
|
|
|
|
2013-06-22 16:09:55 +00:00
|
|
|
@node MIPS Macros
|
|
|
|
@section High-level assembly macros
|
|
|
|
|
|
|
|
MIPS assemblers have traditionally provided a wider range of
|
|
|
|
instructions than the MIPS architecture itself. These extra
|
|
|
|
instructions are usually referred to as ``macro'' instructions
|
|
|
|
@footnote{The term ``macro'' is somewhat overloaded here, since
|
|
|
|
these macros have no relation to those defined by @code{.macro},
|
|
|
|
@pxref{Macro,, @code{.macro}}.}.
|
|
|
|
|
|
|
|
Some MIPS macro instructions extend an underlying architectural instruction
|
|
|
|
while others are entirely new. An example of the former type is @code{and},
|
|
|
|
which allows the third operand to be either a register or an arbitrary
|
|
|
|
immediate value. Examples of the latter type include @code{bgt}, which
|
|
|
|
branches to the third operand when the first operand is greater than
|
|
|
|
the second operand, and @code{ulh}, which implements an unaligned
|
|
|
|
2-byte load.
|
|
|
|
|
|
|
|
One of the most common extensions provided by macros is to expand
|
|
|
|
memory offsets to the full address range (32 or 64 bits) and to allow
|
|
|
|
symbolic offsets such as @samp{my_data + 4} to be used in place of
|
|
|
|
integer constants. For example, the architectural instruction
|
|
|
|
@code{lbu} allows only a signed 16-bit offset, whereas the macro
|
|
|
|
@code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
|
|
|
|
The implementation of these symbolic offsets depends on several factors,
|
2013-06-22 16:18:45 +00:00
|
|
|
such as whether the assembler is generating SVR4-style PIC (selected by
|
|
|
|
@option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
|
2013-06-22 16:09:55 +00:00
|
|
|
(@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
|
|
|
|
and the small data limit (@pxref{MIPS Small Data,, Controlling the use
|
|
|
|
of small data accesses}).
|
|
|
|
|
|
|
|
@kindex @code{.set macro}
|
|
|
|
@kindex @code{.set nomacro}
|
|
|
|
Sometimes it is undesirable to have one assembly instruction expand
|
|
|
|
to several machine instructions. The directive @code{.set nomacro}
|
|
|
|
tells the assembler to warn when this happens. @code{.set macro}
|
|
|
|
restores the default behavior.
|
|
|
|
|
|
|
|
@cindex @code{at} register, MIPS
|
|
|
|
@kindex @code{.set at=@var{reg}}
|
|
|
|
Some macro instructions need a temporary register to store intermediate
|
|
|
|
results. This register is usually @code{$1}, also known as @code{$at},
|
|
|
|
but it can be changed to any core register @var{reg} using
|
|
|
|
@code{.set at=@var{reg}}. Note that @code{$at} always refers
|
|
|
|
to @code{$1} regardless of which register is being used as the
|
|
|
|
temporary register.
|
|
|
|
|
|
|
|
@kindex @code{.set at}
|
|
|
|
@kindex @code{.set noat}
|
|
|
|
Implicit uses of the temporary register in macros could interfere with
|
|
|
|
explicit uses in the assembly code. The assembler therefore warns
|
|
|
|
whenever it sees an explicit use of the temporary register. The directive
|
|
|
|
@code{.set noat} silences this warning while @code{.set at} restores
|
|
|
|
the default behavior. It is safe to use @code{.set noat} while
|
|
|
|
@code{.set nomacro} is in effect since single-instruction macros
|
|
|
|
never need a temporary register.
|
|
|
|
|
|
|
|
Note that while the @sc{gnu} assembler provides these macros for compatibility,
|
|
|
|
it does not make any attempt to optimize them with the surrounding code.
|
|
|
|
|
2013-06-22 16:02:24 +00:00
|
|
|
@node MIPS Symbol Sizes
|
2005-03-04 09:51:11 +00:00
|
|
|
@section Directives to override the size of symbols
|
|
|
|
|
2013-06-22 16:02:24 +00:00
|
|
|
@kindex @code{.set sym32}
|
|
|
|
@kindex @code{.set nosym32}
|
2005-03-04 09:51:11 +00:00
|
|
|
The n64 ABI allows symbols to have any 64-bit value. Although this
|
|
|
|
provides a great deal of flexibility, it means that some macros have
|
|
|
|
much longer expansions than their 32-bit counterparts. For example,
|
|
|
|
the non-PIC expansion of @samp{dla $4,sym} is usually:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
lui $4,%highest(sym)
|
|
|
|
lui $1,%hi(sym)
|
|
|
|
daddiu $4,$4,%higher(sym)
|
|
|
|
daddiu $1,$1,%lo(sym)
|
|
|
|
dsll32 $4,$4,0
|
|
|
|
daddu $4,$4,$1
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
whereas the 32-bit expansion is simply:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
lui $4,%hi(sym)
|
|
|
|
daddiu $4,$4,%lo(sym)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
n64 code is sometimes constructed in such a way that all symbolic
|
|
|
|
constants are known to have 32-bit values, and in such cases, it's
|
|
|
|
preferable to use the 32-bit expansion instead of the 64-bit
|
|
|
|
expansion.
|
|
|
|
|
|
|
|
You can use the @code{.set sym32} directive to tell the assembler
|
|
|
|
that, from this point on, all expressions of the form
|
|
|
|
@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
|
|
|
|
have 32-bit values. For example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
.set sym32
|
|
|
|
dla $4,sym
|
|
|
|
lw $4,sym+16
|
|
|
|
sw $4,sym+0x8000($4)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
will cause the assembler to treat @samp{sym}, @code{sym+16} and
|
|
|
|
@code{sym+0x8000} as 32-bit values. The handling of non-symbolic
|
|
|
|
addresses is not affected.
|
|
|
|
|
|
|
|
The directive @code{.set nosym32} ends a @code{.set sym32} block and
|
|
|
|
reverts to the normal behavior. It is also possible to change the
|
|
|
|
symbol size using the command-line options @option{-msym32} and
|
|
|
|
@option{-mno-sym32}.
|
|
|
|
|
|
|
|
These options and directives are always accepted, but at present,
|
|
|
|
they have no effect for anything other than n64.
|
|
|
|
|
2013-06-22 16:09:55 +00:00
|
|
|
@node MIPS Small Data
|
|
|
|
@section Controlling the use of small data accesses
|
2013-06-22 16:02:24 +00:00
|
|
|
|
2013-06-22 16:09:55 +00:00
|
|
|
@c This section deliberately glosses over the possibility of using -G
|
|
|
|
@c in SVR4-style PIC, as could be done on IRIX. We don't support that.
|
|
|
|
@cindex small data, MIPS
|
2013-06-22 16:02:24 +00:00
|
|
|
@cindex @code{gp} register, MIPS
|
2013-06-22 16:09:55 +00:00
|
|
|
It often takes several instructions to load the address of a symbol.
|
|
|
|
For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
|
|
|
|
of @samp{dla $4,addr} is usually:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
lui $4,%hi(addr)
|
|
|
|
daddiu $4,$4,%lo(addr)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The sequence is much longer when @samp{addr} is a 64-bit symbol.
|
|
|
|
@xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
|
|
|
|
|
|
|
|
In order to cut down on this overhead, most embedded MIPS systems
|
|
|
|
set aside a 64-kilobyte ``small data'' area and guarantee that all
|
|
|
|
data of size @var{n} and smaller will be placed in that area.
|
|
|
|
The limit @var{n} is passed to both the assembler and the linker
|
2013-06-22 16:18:45 +00:00
|
|
|
using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
|
2013-06-22 16:09:55 +00:00
|
|
|
Assembler options}. Note that the same value of @var{n} must be used
|
|
|
|
when linking and when assembling all input files to the link; any
|
|
|
|
inconsistency could cause a relocation overflow error.
|
|
|
|
|
|
|
|
The size of an object in the @code{.bss} section is set by the
|
|
|
|
@code{.comm} or @code{.lcomm} directive that defines it. The size of
|
|
|
|
an external object may be set with the @code{.extern} directive. For
|
|
|
|
example, @samp{.extern sym,4} declares that the object at @code{sym}
|
|
|
|
is 4 bytes in length, while leaving @code{sym} otherwise undefined.
|
|
|
|
|
|
|
|
When no @option{-G} option is given, the default limit is 8 bytes.
|
|
|
|
The option @option{-G 0} prevents any data from being automatically
|
|
|
|
classified as small.
|
|
|
|
|
|
|
|
It is also possible to mark specific objects as small by putting them
|
|
|
|
in the special sections @code{.sdata} and @code{.sbss}, which are
|
|
|
|
``small'' counterparts of @code{.data} and @code{.bss} respectively.
|
|
|
|
The toolchain will treat such data as small regardless of the
|
|
|
|
@option{-G} setting.
|
|
|
|
|
|
|
|
On startup, systems that support a small data area are expected to
|
|
|
|
initialize register @code{$28}, also known as @code{$gp}, in such a
|
|
|
|
way that small data can be accessed using a 16-bit offset from that
|
|
|
|
register. For example, when @samp{addr} is small data,
|
|
|
|
the @samp{dla $4,addr} instruction above is equivalent to:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
daddiu $4,$28,%gp_rel(addr)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Small data is not supported for SVR4-style PIC.
|
2013-06-22 16:02:24 +00:00
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
@node MIPS ISA
|
|
|
|
@section Directives to override the ISA level
|
|
|
|
|
|
|
|
@cindex MIPS ISA override
|
|
|
|
@kindex @code{.set mips@var{n}}
|
|
|
|
@sc{gnu} @code{@value{AS}} supports an additional directive to change
|
2013-06-22 16:18:45 +00:00
|
|
|
the MIPS Instruction Set Architecture level on the fly: @code{.set
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 16:17:15 +00:00
|
|
|
mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
|
|
|
|
or 64r2.
|
2003-01-02 20:03:09 +00:00
|
|
|
The values other than 0 make the assembler accept instructions
|
2000-12-12 19:36:32 +00:00
|
|
|
for the corresponding @sc{isa} level, from that point on in the
|
|
|
|
assembly. @code{.set mips@var{n}} affects not only which instructions
|
|
|
|
are permitted, but also how certain macros are expanded. @code{.set
|
|
|
|
mips0} restores the @sc{isa} level to its original level: either the
|
|
|
|
level you selected with command line options, or the default for your
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
configuration. You can use this feature to permit specific @sc{mips3}
|
2000-12-12 19:36:32 +00:00
|
|
|
instructions while assembling in 32 bit mode. Use this directive with
|
2001-06-29 21:27:43 +00:00
|
|
|
care!
|
1999-05-03 07:29:11 +00:00
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
@cindex MIPS CPU override
|
|
|
|
@kindex @code{.set arch=@var{cpu}}
|
|
|
|
The @code{.set arch=@var{cpu}} directive provides even finer control.
|
|
|
|
It changes the effective CPU target and allows the assembler to use
|
|
|
|
instructions specific to a particular CPU. All CPUs supported by the
|
|
|
|
@samp{-march} command line option are also selectable by this directive.
|
|
|
|
The original value is restored by @code{.set arch=default}.
|
1999-05-03 07:29:11 +00:00
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
|
|
|
|
in which it will assemble instructions for the MIPS 16 processor. Use
|
|
|
|
@code{.set nomips16} to return to normal 32 bit mode.
|
2006-05-08 15:57:05 +00:00
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
Traditional MIPS assemblers do not support this directive.
|
1999-05-03 07:29:11 +00:00
|
|
|
|
bfd/
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
|
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The directive @code{.set micromips} puts the assembler into microMIPS mode,
|
|
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|
in which it will assemble instructions for the microMIPS processor. Use
|
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|
@code{.set nomicromips} to return to normal 32 bit mode.
|
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|
2013-06-22 16:18:45 +00:00
|
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Traditional MIPS assemblers do not support this directive.
|
bfd/
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
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|
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-25 18:02:34 +00:00
|
|
|
@node MIPS assembly options
|
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|
|
@section Directives to control code generation
|
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@cindex MIPS 32-bit microMIPS instruction generation override
|
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@kindex @code{.set insn32}
|
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@kindex @code{.set noinsn32}
|
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|
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The directive @code{.set insn32} makes the assembler only use 32-bit
|
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instruction encodings when generating code for the microMIPS processor.
|
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This directive inhibits the use of any 16-bit instructions from that
|
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point on in the assembly. The @code{.set noinsn32} directive allows
|
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16-bit instructions to be accepted.
|
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Traditional MIPS assemblers do not support this directive.
|
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1999-05-03 07:29:11 +00:00
|
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@node MIPS autoextend
|
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|
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@section Directives for extending MIPS 16 bit instructions
|
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@kindex @code{.set autoextend}
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@kindex @code{.set noautoextend}
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By default, MIPS 16 instructions are automatically extended to 32 bits
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
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when necessary. The directive @code{.set noautoextend} will turn this
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off. When @code{.set noautoextend} is in effect, any 32 bit instruction
|
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must be explicitly extended with the @code{.e} modifier (e.g.,
|
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@code{li.e $4,1000}). The directive @code{.set autoextend} may be used
|
1999-05-03 07:29:11 +00:00
|
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to once again automatically extend instructions when necessary.
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This directive is only meaningful when in MIPS 16 mode. Traditional
|
2013-06-22 16:18:45 +00:00
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MIPS assemblers do not support this directive.
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1999-05-03 07:29:11 +00:00
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@node MIPS insn
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@section Directive to mark data as an instruction
|
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@kindex @code{.insn}
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The @code{.insn} directive tells @code{@value{AS}} that the following
|
bfd/
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
|
|
|
data is actually instructions. This makes a difference in MIPS 16 and
|
|
|
|
microMIPS modes: when loading the address of a label which precedes
|
|
|
|
instructions, @code{@value{AS}} automatically adds 1 to the value, so
|
|
|
|
that jumping to the loaded address will do the right thing.
|
1999-05-03 07:29:11 +00:00
|
|
|
|
2009-07-23 10:19:20 +00:00
|
|
|
@kindex @code{.global}
|
|
|
|
The @code{.global} and @code{.globl} directives supported by
|
|
|
|
@code{@value{AS}} will by default mark the symbol as pointing to a
|
|
|
|
region of data not code. This means that, for example, any
|
|
|
|
instructions following such a symbol will not be disassembled by
|
2009-07-30 08:45:41 +00:00
|
|
|
@code{objdump} as it will regard them as data. To change this
|
2009-07-23 10:19:20 +00:00
|
|
|
behaviour an optional section name can be placed after the symbol name
|
|
|
|
in the @code{.global} directive. If this section exists and is known
|
|
|
|
to be a code section, then the symbol will be marked as poiting at
|
|
|
|
code not data. Ie the syntax for the directive is:
|
|
|
|
|
|
|
|
@code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
|
|
|
|
|
|
|
|
Here is a short example:
|
|
|
|
|
|
|
|
@example
|
|
|
|
.global foo .text, bar, baz .data
|
|
|
|
foo:
|
|
|
|
nop
|
|
|
|
bar:
|
|
|
|
.word 0x0
|
|
|
|
baz:
|
|
|
|
.word 0x1
|
2013-01-10 19:51:55 +00:00
|
|
|
|
2009-07-23 10:19:20 +00:00
|
|
|
@end example
|
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
@node MIPS Option Stack
|
1999-05-03 07:29:11 +00:00
|
|
|
@section Directives to save and restore options
|
|
|
|
|
|
|
|
@cindex MIPS option stack
|
|
|
|
@kindex @code{.set push}
|
|
|
|
@kindex @code{.set pop}
|
|
|
|
The directives @code{.set push} and @code{.set pop} may be used to save
|
|
|
|
and restore the current settings for all the options which are
|
|
|
|
controlled by @code{.set}. The @code{.set push} directive saves the
|
|
|
|
current settings on a stack. The @code{.set pop} directive pops the
|
|
|
|
stack and restores the settings.
|
|
|
|
|
|
|
|
These directives can be useful inside an macro which must change an
|
|
|
|
option such as the ISA level or instruction reordering but does not want
|
|
|
|
to change the state of the code which invoked the macro.
|
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
Traditional MIPS assemblers do not support these directives.
|
2002-03-16 03:09:19 +00:00
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
@node MIPS ASE Instruction Generation Overrides
|
2002-03-16 03:09:19 +00:00
|
|
|
@section Directives to control generation of MIPS ASE instructions
|
|
|
|
|
|
|
|
@cindex MIPS MIPS-3D instruction generation override
|
|
|
|
@kindex @code{.set mips3d}
|
|
|
|
@kindex @code{.set nomips3d}
|
|
|
|
The directive @code{.set mips3d} makes the assembler accept instructions
|
|
|
|
from the MIPS-3D Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
|
|
|
instructions from being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
@cindex SmartMIPS instruction generation override
|
|
|
|
@kindex @code{.set smartmips}
|
|
|
|
@kindex @code{.set nosmartmips}
|
|
|
|
The directive @code{.set smartmips} makes the assembler accept
|
|
|
|
instructions from the SmartMIPS Application Specific Extension to the
|
|
|
|
MIPS32 @sc{isa} from that point on in the assembly. The
|
|
|
|
@code{.set nosmartmips} directive prevents SmartMIPS instructions from
|
|
|
|
being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 01:17:18 +00:00
|
|
|
@cindex MIPS MDMX instruction generation override
|
|
|
|
@kindex @code{.set mdmx}
|
|
|
|
@kindex @code{.set nomdmx}
|
|
|
|
The directive @code{.set mdmx} makes the assembler accept instructions
|
|
|
|
from the MDMX Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomdmx} directive prevents MDMX
|
|
|
|
instructions from being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 13:28:56 +00:00
|
|
|
@cindex MIPS DSP Release 1 instruction generation override
|
2005-09-08 18:05:15 +00:00
|
|
|
@kindex @code{.set dsp}
|
|
|
|
@kindex @code{.set nodsp}
|
|
|
|
The directive @code{.set dsp} makes the assembler accept instructions
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 13:28:56 +00:00
|
|
|
from the DSP Release 1 Application Specific Extension from that point
|
|
|
|
on in the assembly. The @code{.set nodsp} directive prevents DSP
|
|
|
|
Release 1 instructions from being accepted.
|
|
|
|
|
|
|
|
@cindex MIPS DSP Release 2 instruction generation override
|
|
|
|
@kindex @code{.set dspr2}
|
|
|
|
@kindex @code{.set nodspr2}
|
|
|
|
The directive @code{.set dspr2} makes the assembler accept instructions
|
|
|
|
from the DSP Release 2 Application Specific Extension from that point
|
|
|
|
on in the assembly. This dirctive implies @code{.set dsp}. The
|
|
|
|
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
|
|
|
|
being accepted.
|
2005-09-08 18:05:15 +00:00
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
2005-09-06 18:53:03 +00:00
|
|
|
@cindex MIPS MT instruction generation override
|
|
|
|
@kindex @code{.set mt}
|
|
|
|
@kindex @code{.set nomt}
|
|
|
|
The directive @code{.set mt} makes the assembler accept instructions
|
|
|
|
from the MT Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomt} directive prevents MT
|
|
|
|
instructions from being accepted.
|
|
|
|
|
gas/
* config/tc-mips.c (mips_set_options): Add ase_mcu.
(mips_opts): Initialise ase_mcu to -1.
(ISA_SUPPORTS_MCU_ASE): New macro.
(MIPS_CPU_ASE_MCU): Likewise.
(is_opcode_valid): Handle MCU.
(macro_build, macro): Likewise.
(validate_mips_insn, validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_MCU and OPTION_NO_MCU.
(md_longopts): Add mmcu and mno-mcu.
(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
(mips_after_parse_args): Handle MCU.
(s_mipsset): Likewise.
(md_show_usage): Handle MCU options.
* doc/as.texinfo: Document -mmcu and -mno-mcu options.
* doc/c-mips.texi: Likewise, and document ".set mcu" and
".set nomcu" directives.
gas/testsuite/
* gas/mips/micromips@mcu.d: New test.
* gas/mips/mcu.d: Likewise.
* gas/mips/mcu.s: New test source.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
opcodes/
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
and "mips64r2".
(print_insn_args, print_insn_micromips): Handle MCU.
* micromips-opc.c (MC): New macro.
(micromips_opcodes): Add "aclr", "aset" and "iret".
* mips-opc.c (MC): New macro.
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-08-09 15:20:03 +00:00
|
|
|
@cindex MIPS MCU instruction generation override
|
|
|
|
@kindex @code{.set mcu}
|
|
|
|
@kindex @code{.set nomcu}
|
|
|
|
The directive @code{.set mcu} makes the assembler accept instructions
|
|
|
|
from the MCU Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomcu} directive prevents MCU
|
|
|
|
instructions from being accepted.
|
|
|
|
|
binutils/ChangeLog:
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 01:08:48 +00:00
|
|
|
@cindex Virtualization instruction generation override
|
|
|
|
@kindex @code{.set virt}
|
|
|
|
@kindex @code{.set novirt}
|
|
|
|
The directive @code{.set virt} makes the assembler accept instructions
|
|
|
|
from the Virtualization Application Specific Extension from that point
|
|
|
|
on in the assembly. The @code{.set novirt} directive prevents Virtualization
|
|
|
|
instructions from being accepted.
|
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
Traditional MIPS assemblers do not support these directives.
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
@node MIPS Floating-Point
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
|
|
|
@section Directives to override floating-point options
|
|
|
|
|
|
|
|
@cindex Disable floating-point instructions
|
|
|
|
@kindex @code{.set softfloat}
|
|
|
|
@kindex @code{.set hardfloat}
|
|
|
|
The directives @code{.set softfloat} and @code{.set hardfloat} provide
|
|
|
|
finer control of disabling and enabling float-point instructions.
|
|
|
|
These directives always override the default (that hard-float
|
|
|
|
instructions are accepted) or the command-line options
|
|
|
|
(@samp{-msoft-float} and @samp{-mhard-float}).
|
|
|
|
|
|
|
|
@cindex Disable single-precision floating-point operations
|
2009-09-25 18:58:58 +00:00
|
|
|
@kindex @code{.set singlefloat}
|
|
|
|
@kindex @code{.set doublefloat}
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 17:06:28 +00:00
|
|
|
The directives @code{.set singlefloat} and @code{.set doublefloat}
|
|
|
|
provide finer control of disabling and enabling double-precision
|
|
|
|
float-point operations. These directives always override the default
|
|
|
|
(that double-precision operations are accepted) or the command-line
|
|
|
|
options (@samp{-msingle-float} and @samp{-mdouble-float}).
|
|
|
|
|
2013-06-22 16:18:45 +00:00
|
|
|
Traditional MIPS assemblers do not support these directives.
|
2011-01-18 13:37:39 +00:00
|
|
|
|
|
|
|
@node MIPS Syntax
|
|
|
|
@section Syntactical considerations for the MIPS assembler
|
|
|
|
@menu
|
|
|
|
* MIPS-Chars:: Special Characters
|
|
|
|
@end menu
|
|
|
|
|
|
|
|
@node MIPS-Chars
|
|
|
|
@subsection Special Characters
|
|
|
|
|
|
|
|
@cindex line comment character, MIPS
|
|
|
|
@cindex MIPS line comment character
|
|
|
|
The presence of a @samp{#} on a line indicates the start of a comment
|
|
|
|
that extends to the end of the current line.
|
|
|
|
|
|
|
|
If a @samp{#} appears as the first character of a line, the whole line
|
|
|
|
is treated as a comment, but in this case the line can also be a
|
|
|
|
logical line number directive (@pxref{Comments}) or a
|
|
|
|
preprocessor control command (@pxref{Preprocessing}).
|
|
|
|
|
|
|
|
@cindex line separator, MIPS
|
|
|
|
@cindex statement separator, MIPS
|
|
|
|
@cindex MIPS line separator
|
|
|
|
The @samp{;} character can be used to separate statements on the same
|
|
|
|
line.
|