Unknown W. Brackets
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2f5c6a5660
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Fix VLDM/VSTM encoding for double/quad regs.
Duh, forgot to check Vd. Fixes #5723.
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2014-03-25 22:08:20 -07:00 |
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Unknown W. Brackets
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b589d3b170
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vertexjit: Fix a silly mistake in weights > 4.
Darn switch, took me way too long to notice this.
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2014-03-23 19:02:40 -07:00 |
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Unknown W. Brackets
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717e6db3a7
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Fix VDUP so that it actually works.
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2014-03-23 17:51:32 -07:00 |
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Unknown W. Brackets
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f74b765ff3
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Fix VLDM/VSTM encoding for D/Q regs.
Now it is actually using ASIMD/NEON.
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2014-03-23 16:26:13 -07:00 |
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Unknown W. Brackets
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ff2d5bb17e
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Add a float->GP reg, fix VDUP for I_16.
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2014-03-23 16:25:56 -07:00 |
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Unknown W. Brackets
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8056440ba1
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Implement NEON register VMOVs.
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2014-03-23 16:25:52 -07:00 |
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Unknown W. Brackets
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2b586b2a7a
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Support other constant VMOVs on NEON.
Float is especially useful.
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2014-03-23 16:12:51 -07:00 |
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Unknown W. Brackets
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3e1cd5c161
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Add a NEON VMOV imm encoding to the emitter.
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2014-03-23 16:12:46 -07:00 |
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Unknown W. Brackets
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06db03ac9e
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Add some asserts to VLDM/VSTM.
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2014-03-22 16:12:35 -07:00 |
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Unknown W. Brackets
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60bbf4af3b
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Fix VLD1/VST1 n=4.
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2014-03-22 16:12:08 -07:00 |
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Unknown W. Brackets
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f3d38ee269
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Fix VMOV for Dregs and VSHL reg order.
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2014-03-22 16:12:00 -07:00 |
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Unknown W. Brackets
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0da9c1851c
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vertexjit: Add VQMOV(U)N and fix VMOVN size.
It will be too confusing if it's specified as the destination, unlike
VMOVL. Plus the assembler syntax uses the source size.
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2014-03-22 16:11:36 -07:00 |
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Henrik Rydgård
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8dfadf7b8e
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ArmEmitter: Add VMOV_neon and a Size parameter to VFMA for consistency.
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2014-03-22 16:31:16 +01:00 |
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Unknown W. Brackets
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e783627947
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armjit: Use our I2R funcs on reg/reg math too.
When one is a known immediate. This should catch more cases, like:
ori v0, $0, 0xFFFF
and v1, v1, v0
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2014-03-14 19:15:43 -07:00 |
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Unknown W. Brackets
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836787d19a
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Optimize ANDI2R() to use UBFX if possible.
This way, & 0x7FF or & 0xFFFF etc. are all fast when on ARMv7.
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2014-03-14 19:15:42 -07:00 |
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Unknown W. Brackets
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3a07924ad9
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Add Try arm emitter I2R funcs.
This way we can use them without giving up the regcache's immediate
optimizations.
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2014-03-14 19:15:42 -07:00 |
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Unknown W. Brackets
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48fa22b7cf
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B/BL were swapped in the arm emitter.
Oops...
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2014-03-14 19:15:41 -07:00 |
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Unknown W. Brackets
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76305130ee
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Add a couple missing (unused) ARM instructions.
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2014-03-14 19:15:39 -07:00 |
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Henrik Rydgard
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ab9cd99d0f
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Major ARM disassembler improvements, will make debugging the JIT easier
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2014-03-12 18:09:28 +01:00 |
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Henrik Rydgard
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adadf11890
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An attempt to combine FPU regcache writebacks with VSTMIA. Disabled due to bugs.
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2014-03-11 11:03:51 +01:00 |
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Henrik Rydgard
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2eb6a4e2f2
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Fix a warning, rename some parameters, etc.
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2014-03-08 10:40:43 +01:00 |
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Sacha
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ad31cd1b7c
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Clean up ArmEmitter (cross-merge from Dolphin, minus the bad bits)
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2014-03-07 15:47:34 +10:00 |
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Sacha
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30a6a5d10f
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ARMJIT: Implement VLDM/VSTM load/store combinations and use in armjit. Also add them to disassembler.
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2014-03-07 02:56:34 +10:00 |
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Unknown W. Brackets
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2655a4cba6
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Include some now-missing things for Linux.
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2013-12-30 21:15:00 -08:00 |
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Henrik Rydgård
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e5e17fbc6e
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More include cleanup. Hoping for very slightly faster compile times..
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2013-12-30 10:49:05 +01:00 |
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Unknown W. Brackets
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e6b2d00a2f
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Avoid reseved identifiers like _SP, etc.
R_SP is not that bad.
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2013-12-29 14:25:34 -08:00 |
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Henrik Rydgard
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8956fb2932
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Minor optimization in ADDI2R
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2013-11-30 15:52:59 +01:00 |
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Unknown W. Brackets
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dffa35ef2f
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When ins is used with a zero argument, don't OR.
Seems it's used effectively to mask out bits with rs=zero. Makes sense...
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2013-11-29 09:17:12 -08:00 |
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Henrik Rydgard
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aaab7e32d2
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ARM emitter: Fix VDUP
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2013-11-24 19:30:25 +01:00 |
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Henrik Rydgard
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030e6460cc
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ARM: NEON-optimize software skinning
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2013-11-24 18:03:42 +01:00 |
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Henrik Rydgard
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dfea160491
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ARM: Use PLD (cache preload) in vertex decoder loop.
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2013-11-24 15:08:47 +01:00 |
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Henrik Rydgard
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f650b23c90
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ARM: Add NEON widening and narrowing moves, and float/int convert.
Experiment a little in the vertex decoder.
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2013-11-24 13:30:28 +01:00 |
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Henrik Rydgard
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16509ba3e9
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ARMEmitter: Make the helper functions private.
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2013-11-23 13:43:22 +01:00 |
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Henrik Rydgard
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cda4e9cbf3
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ARM emitter: Complete VLD1/VST1 for lanes and to-all-lanes.
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2013-11-23 13:36:26 +01:00 |
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Henrik Rydgard
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e0eb152fb9
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VLD1/VST1: Change argument ordering again.
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2013-11-23 11:05:19 +01:00 |
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Henrik Rydgard
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b64f44c3fc
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ARM emitter: Implement VMLA and VMUL by scalar, VLD1/VST1 multiple
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2013-11-23 01:51:35 +01:00 |
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Unknown W. Brackets
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c50ab6d6aa
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armjit: Fix divu when divisor is a constant 1.
Fixes #4539 and #4520.
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2013-11-19 13:24:15 -08:00 |
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Unknown W. Brackets
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f165a15eff
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Fix a -unsigned warning.
Looks ugly, but (u32)-(s32)val is what we really want here.
Also make a __FUNCTION__ redeclaration warning go away.
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2013-11-15 08:18:34 -08:00 |
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Sacha
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e3bdb3e09b
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Disable LitPool as it is causing crashes with Vertex Decoder JIT. Performance seems to be almost unaffected since the IMM changes.
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2013-11-15 14:12:00 +10:00 |
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Sacha
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20e8a81268
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Switch to compile-time ARMV7 define.
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2013-11-15 11:20:39 +10:00 |
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Henrik Rydgård
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ddf5b695ac
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Update ArmEmitter with Sonic1's new NEON emitters. Thanks!
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2013-11-13 11:34:47 +01:00 |
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Unknown W. Brackets
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1a98691c57
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armjit: Fix ANDI2R() clearing low bits incorrectly.
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2013-11-11 19:07:16 -08:00 |
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Unknown W. Brackets
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ee492099b5
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Avoid a literal in ORI2R where possible.
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2013-11-10 14:38:08 -08:00 |
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Unknown W. Brackets
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83fe874dcc
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armjit: Use multiple BICs in ANDI2R if possible.
Rather than a temporary.
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2013-11-09 08:42:31 -08:00 |
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Unknown W. Brackets
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6038d96b46
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armjit: Flush regs using STMIA where possible.
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2013-11-09 08:25:07 -08:00 |
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Henrik Rydgard
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1bf83efe9e
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ARM optimization in ADDI2R: Dual adds instead of MOVI2R, ADD when possible
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2013-11-08 12:43:47 +01:00 |
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Unknown W. Brackets
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f6662054bd
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Fix arm emitter bug in LDRH and friends.
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2013-11-05 00:32:08 -08:00 |
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Unknown W. Brackets
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7a8671f8a2
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Add a TSTI2R helper for readability mainly.
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2013-11-03 21:58:26 -08:00 |
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Unknown W. Brackets
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5de7181b36
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Add other forms of LDM/STM to the emitter.
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2013-11-03 21:31:05 -08:00 |
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Unknown W. Brackets
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95c8ee5089
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Missing stddef library (Linux buildfix.)
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2013-10-27 15:52:40 +00:00 |
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