Commit Graph

143890 Commits

Author SHA1 Message Date
Marek Olšák
8f935317e6 frontend/dri: add environment variable DRI_NO_MSAA for performance comparisons
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12491>
2021-08-21 00:30:59 +00:00
Marek Olšák
aad7a1d79a radeonsi: remove vertices_per_patch parameter from draw-related functions
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351>
2021-08-21 00:08:11 +00:00
Marek Olšák
10a46226b1 gallium: remove vertices_per_patch, add pipe_context::set_patch_vertices
We would like draw-only display lists to have immutable draw info and
this is the only GL non-draw state in pipe_draw_info (not counting
view_mask).

It also allows removing some code from draw_vbo for tessellation.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351>
2021-08-21 00:08:11 +00:00
Connor Abbott
6d76112624 tu: Remove some stale bypass xfails
These were fixed by 09e0b29bb6 which was
missed during the suite conversion. For the remaining still-valid fail,
there is a CTS patch in progress.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12488>
2021-08-20 22:28:56 +00:00
Rob Clark
d889f5f282 freedreno/crashdec: Quiet spammy print in query mode
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>
2021-08-20 22:01:49 +00:00
Rob Clark
dbea4bb970 freedreno/crashdec: Decode full RB in verbose mode
This is useful to get a better view of previous commands in the
ringbuffer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>
2021-08-20 22:01:49 +00:00
Rob Clark
ed8d3095ab freedreno/cffdec: Fix gpuaddr comparision
gpuaddrs are 64b, and they can be more than 2^^32 apart.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>
2021-08-20 22:01:49 +00:00
Rob Clark
32f13cb9bc freedreno/cffdec: Fix indentation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>
2021-08-20 22:01:49 +00:00
Icecream95
295807e666 pan/bi: Extend bi_add_nop_for_atest for tilebuffer loads
Fixes framebuffer_fetch and blend_equation_advanced dEQP tests on v6.

v2: Use clause dependencies rather than comparing the message type
v3: Shift the BIFROST_SLOT_* constants before using them as a mask

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12375>
2021-08-20 21:38:01 +00:00
Matt Turner
e0bc11d9d2 tu: Free device->bo_idx and device->bo_list on init failure
Two related changes:

- in tu_device.c:tu_CreateDevice we need to free both pointers in the
  teardown path after tu_bo_finish(global_bo), which uses the pointers.
  They are allocated in the first call to tu_bo_init(), which happens
  when global_bo is allocated.

- in tu_drm.c:tu_bo_init we need to free bo_list if the bo_idx
  allocation fails. Convert to the goto teardown pattern as well.

Fixes the following dEQP-VK tests:
  dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail
  dEQP-VK.api.object_management.alloc_callback_fail.device
  dEQP-VK.api.object_management.alloc_callback_fail.device_group

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12481>
2021-08-20 20:30:14 +00:00
Alyssa Rosenzweig
61c8e39649 pan/bi: Use CLPER_V6 on Mali G31
Apparently, CLPER_V7 is missing from Mali G31, but CLPER_V6 works. Fixes
INSTR_INVALID_ENC faults and failures in
dEQP-GLES3.functional.shaders.derivate.* on Dvalin.

Technically not an errata but an implementation difference. I suspect
Mali G51 will need this as well, should we ever allowlist it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
bfd3ae35c9 pan/bi: Use ST_TILE for multisampled blend output
ST_TILE lets us specify an explicit sample, whereas BLEND replicates to
all samples. This fully fixes the interaction between blend shaders and
multisampling on Bifrost, manifesting as
dEQP-GLES3.functional.fragment_ops.random.* failures with the
configuration rgba8888d24s8ms4.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
4a51366144 panfrost: Evaluate blend shaders per-sample
This varies the sample ID value, which will be used in the next commit.
This is less complicated than keying blend shaders to the content of
this flag and trying to make mega blend shaders covering all samples at
once ... complexity I'd rather not think about right now. The DDK does
it this way.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
16394dc71a pan/bi: Set the sample ID for blend shader LD_TILE
Use the explicit sample mode and set the sample ID in the pixel indices
structure to the current sample ID. This fixes tilebuffer loads in blend
shaders on multisampled framebuffers.

Make sure the new routine is broken out to a helper for use with ST_TILE
in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
9f19a883bc pan/bi: Extract load_sample_id to a helper
Will be reused in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
5c2a4eb1c2 pan/bi: Correct the sr_count on +ST_TILE
Otherwise we'll get validator fails when emitting +ST_TILE.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
710498e424 pan/bi: Don't set td in blend shaders
This breaks screen-space derivatives in a shader that uses multiple
render targets, if the derivative calculation is scheduled after a BLEND
instruction calling into a blend shader.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
0a26ec78b1 pan/bi: Set eldest_colour dependency for ST_TILE
I don't think we'll ever hit this in practice, since it's not needed for
blend shaders, but better to correct the code anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Alyssa Rosenzweig
a7f7d74137 panfrost: Disable shader-assisted indirect draws
Although it is passing all of dEQP-GLES31, it is failing a few
KHR-GLES31.* tests. It also has performance issues at the moment. Invert
the existing noindirect debug flag to become a indirect debug flag. Set
this flag for dEQP-GLES31 CI on G52, to make sure the code doesn't bit
rot on the hope someone will pick this up later on.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
2021-08-20 20:13:27 +00:00
Leandro Ribeiro
8107f67171 vulkan/wsi/wayland: memset members of image to zero
struct wsi_wl_image is only used as member of the swapchain, and during
the swapchain creation the image is already initialized to zero. So we
have no problems with members of the image being used uninitialized.

But for consistency, memset the members of this struct to zero in
wsi_wl_image_init(). This can help to avoid problems in the future.

Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12451>
2021-08-20 18:51:36 +00:00
Leandro Ribeiro
4cd187e71e vulkan/wsi/wayland: create swapchain using vk_zalloc()
In wsi_wl_surface_create_swapchain() we have a piece of code to init
some members of the chain to 0, in order to allow us to call
wsi_wl_swapchain_destroy() for cleanup.

Instead, we can use vk_zalloc() to allocate the chain, as it initializes
all members of the struct to zero. This help us to avoid problems when
people add new members to the struct and forget to initialize them.
Also, it makes the code look better.

Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12451>
2021-08-20 18:51:36 +00:00
Emma Anholt
03e457bb1a ci/lavapipe: Add a fractional run with ASan
This catches use-after-frees and buffer overflows, but not leaks (which we
disable the checking for since the library gets dlclose()d and we end up
with useless backtraces).

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8889>
2021-08-20 18:22:30 +00:00
Connor Abbott
47996b951e tu: Add a650-specific CCU flush workaround
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12475>
2021-08-20 18:03:26 +00:00
Connor Abbott
abf0ae014a tu: Properly handle waiting on an earlier pipeline stage
I never really implemented this properly, because I wasn't aware of the
clusters when doing the original pipeline barrier implementation. It
turns out that the Vulkan stages we get as part of the barriers are
actually good for something, because it turns out that the pipeline
state is split into stages, so earlier stages can run ahead of later
stages and sometimes we need to wait when an earlier stage depends on
the result of a later stage. This happens most often whenever a shader
reads the result of a color/depth attachment write, because attachment
writes happen in a logically later stage. However this could also happen
for a FS -> VS dependency.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12475>
2021-08-20 18:03:26 +00:00
Nanley Chery
4003f2d48d anv: Optimize genX(cmd_buffer_emit_gfx12_depth_wa)
Only emit the workaround as needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
ab4d411387 iris: Optimize genX(emit_depth_state_workarounds)
Only emit the workaround as needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
e86fb61106 iris: Use constants for emitting cso_z->packets
This should be a bit faster and easier to follow.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
2ae70329f5 intel: Move the D16 workarounds out of ISL
Implement the workarounds in anv and iris instead.

Before this commit, ISL unconditionally modified workaround registers
while filling out depth stencil state. To account for this, drivers
unconditionally stalled prior to emitting depth stencil packets. This
hurt performance.

By having the drivers perform the workarounds, they can choose when to
modify the relevant registers. The drivers now avoid emitting the
workaround for NULL depth buffers. This reduces stalls and leads to
better performance.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (the ISL/Anv bits)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (the Iris bits)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
9fd3baf34b iris: Update clear_params only when HiZ is enabled
This more closely matches ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
de7d8e53b7 iris: Emit clear_params as part of cso_z->packets
This should be a bit faster.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
78376a450b iris: Update the clear value in cso_z->packets
Enables emitting the packets all at once later on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
f131e8917a iris: Add genX(emit_depth_state_workarounds)
This will replace the workaround built into ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Nanley Chery
14b3732b84 anv: Add genX(cmd_buffer_emit_gfx12_depth_wa)
This will replace the workaround built into ISL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
2021-08-20 17:50:35 +00:00
Samuel Pitoiset
be6bdb0918 radv: fix copying depth+stencil images on compute
Using separate aspects is required.

Fixes few CTS failures (dEQP-VK.api.copy_and_blit.*) when the compute
path is forced in the driver. Note that CTS coverage of compute queue
is rather limited.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12287>
2021-08-20 16:43:22 +00:00
Timothy Arceri
02b394023b glsl: fix variable scope for instructions inside case statements
Fixes: 665d75cc5a ("glsl: Fix scoping bug in if statements.")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5247

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12435>
2021-08-20 16:13:56 +00:00
Samuel Pitoiset
067599f8bc radv: remove incorrect comment about compressed writes to HTILE on GFX10+
This seems to be unsupported.
COMPRESSION_EN=1 and WRITE_COMPRESS_ENABLE=1 don't update HTILE
with image stores.

Note that there is no issue because depth/stencil images will be
decompressed for image stores, and TC-compat HTILE is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>
2021-08-20 15:53:32 +00:00
Samuel Pitoiset
1c26751969 radv: remove unnecessary check in radv_layout_is_htile_compressed()
The driver doesn't enable TC-compat HTILE for storage images, so this
was actually always TRUE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>
2021-08-20 15:53:32 +00:00
Marek Olšák
86fd7f5484 st/mesa: move handling CubeMapSeamless into st_convert_sampler where it belongs
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>
2021-08-20 15:04:20 +00:00
Marek Olšák
feda6e9c5d st/mesa: set take_ownership = true in set_sampler_views
update_textures_local is removed because the only thing it did was
unreferencing sampler views, which is being removed.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>
2021-08-20 15:04:20 +00:00
Marek Olšák
bb89cf4bf3 gallium: add take_ownership into set_sampler_views to skip reference counting
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>
2021-08-20 15:04:20 +00:00
Marek Olšák
556c10c02c ac/surface: allow arbitrary swizzle modes for displayable DCC
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>
2021-08-20 14:28:36 +00:00
Marek Olšák
94d261029e radv: allow arbitrary swizzle modes for displayable DCC
by adding retile pipeline variants

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>
2021-08-20 14:28:36 +00:00
Marek Olšák
6fc38d3b07 radeonsi: allow arbitrary swizzle modes for displayable DCC
by adding retile shader variants

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>
2021-08-20 14:28:36 +00:00
Danylo Piliaiev
ee9f0e78c1 ir3: prohibit folding of half->full conversion into mul.s24/u24
mul.s24/u24 always return 32b result regardless of its sources size,
hence we cannot guarantee the high 16b of dst being zero or sign extended.

Fixes cts tests on a650:
 dEQP-VK.spirv_assembly.type.scalar.i16.mul_test_high_part_zero_*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12471>
2021-08-20 11:46:14 +00:00
Connor Abbott
10bf0c51d4 freedreno/ci: Add spillall tests
Only test shader tests, because the others are unlikely to have
interesting shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00
Connor Abbott
0b39f4ab42 ir3, turnip, freedreno: Report stp/ldp in shader stats
This is important after spilling, so that we get an indication when a
change causes spilling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00
Connor Abbott
58b54157ee ir3: Fix getting stp/ldp components in ir3_info
Noticed by inspection when adding stp_count/ldp_count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00
Connor Abbott
613eaac7b5 ir3: Initial support for spilling non-shared registers
Support for spilling shared registers to normal registers is still TODO.
There are also several improvements to be made, like rematerialization.

Note, there is one behavior change to register pressure accounting: we
now include half registers in the current full pressure directly in
mergedregs mode, rather than adding the max half pressure to the max
full pressure afterwards, which might result in lower calculated max
pressure in some cases with half registers. This is needed for spilling,
since we need to make sure the total pressure including half registers
is below the maximum at each instruction. Because the entire pass is
rewritten, including the register pressure calculating parts, it didn't
seem worth it to separate out this change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00
Connor Abbott
6a5312bf86 ir3: Fix compress_regs_left accounting for half-regs
This was just wrong - we need to check against the entire register file,
and we need to include removed full regs even if the register we're
trying to insert is a half-reg, or else we could run out of space when
reinserting full regs after it. There does need to be an additional
check so that we don't try to insert a half-reg beyond the half-reg
limit, but that has to happen in addition to the normal check.

This fixes KHR-GLES31.core.arrays_of_arrays.InteractionArgumentAliasing6
once spilling is added.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00
Connor Abbott
cca2e0fc14 ir3: Properly validate pcopy reg sizes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
2021-08-20 10:37:36 +00:00