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48 Commits
Author SHA1 Message Date
pancake 7ec6dbcf88 Release 4.0 2019-10-28 16:52:59 +01:00
pancake bc6d3f36da Import r2ida from https://github.com/radare/radare2ida 2019-10-28 11:03:42 +01:00
Sylvain Pelissier 96d68f14ed Microblaze ESIL update (#215)
* Corrected jumps and remove git messages
* Add ESIL for right shift and correct imm value
* Separate branch with immediate instructions
2019-10-16 12:52:27 +02:00
dependabot[bot] a67e7f0adb Bump lodash from 4.17.11 to 4.17.15 in /r2jadx (#213)
Bumps [lodash](https://github.com/lodash/lodash) from 4.17.11 to 4.17.15.
- [Release notes](https://github.com/lodash/lodash/releases)
- [Commits](https://github.com/lodash/lodash/compare/4.17.11...4.17.15)

Signed-off-by: dependabot[bot] <[email protected]>
2019-10-07 18:24:45 +08:00
dependabot[bot] 7125f795b4 Bump eslint-utils from 1.3.1 to 1.4.2 in /r2jadx (#212)
Bumps [eslint-utils](https://github.com/mysticatea/eslint-utils) from 1.3.1 to 1.4.2.
- [Release notes](https://github.com/mysticatea/eslint-utils/releases)
- [Commits](https://github.com/mysticatea/eslint-utils/compare/v1.3.1...v1.4.2)

Signed-off-by: dependabot[bot] <[email protected]>
2019-10-07 18:24:36 +08:00
Sylvain Pelissier 6ad247901d Update test to use NodeJS 10 (#211) 2019-10-07 17:24:36 +08:00
Maijin 7ecb70cd26 Change radare->radareorg links 2019-10-07 10:53:33 +02:00
Sylvain Pelissier f90380fc23 Improvements for Microblaze ESIL of jump an return operations 2019-10-07 15:53:45 +08:00
Anton Kochkov a0d0c360da Fix urls 2019-10-07 15:48:54 +08:00
Anton Kochkov 80e37a663d Fix urls 2019-10-07 15:48:15 +08:00
pancake fb3c96694e Add checkm8 io plugin 2019-09-30 20:01:56 +02:00
Sylvain Pelissier 2ee3d1153b Microblaze add calls and delay branch (#209) 2019-09-24 20:19:46 +02:00
Sylvain Pelissier 972e774df8 Add Travis CI test for Microblaze and update ESIL (#207) 2019-09-18 14:15:21 +02:00
pancake 4325c5c797 Release 3.9.0 2019-09-17 18:50:05 +02:00
Sylvain Pelissier 738ed6451c Improve Microblaze ESIL ##anal (#206) 2019-09-16 09:36:43 +02:00
Sylvain Pelissier d686d94c0e Correct pointer for r_str_newf function (#205) 2019-09-10 13:25:21 +02:00
Sylvain Pelissier 86a32aa11e Handle negative immediate values in instructions (#204) 2019-09-08 19:09:49 +02:00
pancake 0d830052ad Release 3.7.0 2019-08-01 05:10:31 +02:00
pancake cb31b4c934 Fixes and improvements in cmdline handling and such for r2snow 2019-07-24 12:06:33 +02:00
pancake 78336f4977 More fixes for r2snow 2019-07-24 06:45:43 +02:00
pancake 85f79f83b3 Import snowman output as comments into r2 in r2snow 2019-07-24 04:41:53 +02:00
pancake 940dfec369 More fixes and ipmrovements for r2jadx 2019-07-11 06:45:45 +02:00
pancake 807d1999c0 Update r2pipe dependency for r2jadx 2019-07-10 20:15:31 +02:00
pancake b74f1d306b Lots of improvements for r2jadx! 2019-07-10 12:54:43 +02:00
pancake 3134973ee0 Fix indent and add one more try/catch block 2019-07-09 15:42:37 +02:00
pancake 6993b40789 Use --illegal-access=warn 2019-07-09 15:39:04 +02:00
pancake f54381e411 Add missing md380 Makefile 2019-07-09 15:34:21 +02:00
pancake bd89b33d1a Add ^C message 2019-07-09 15:33:55 +02:00
pancake 96a6b07921 Check for jadx version and use r2pipe.isAvailable() after upgrading dependencies 2019-07-09 15:24:39 +02:00
pancake 05f76e5578 Release 3.6.0 2019-06-24 15:49:47 +02:00
pancake 2e8fac708c Initial working version of r2jadx 2019-06-21 10:27:44 +02:00
pancake c7ffc478e5 Initial implementation of r2jadx 2019-06-16 20:15:02 +02:00
meme c276d25c57 Update <mybfd.h> to reflect the static inlining of bfd_get_bits
https://github.com/radare/radare2/blob/master/libr/asm/arch/include/mybfd.h#L584-L585
2019-06-15 16:35:17 +02:00
dissonant-research c45284dab5 Switching from RIOSection to RIOMap in unicorn debug 2019-05-24 09:27:58 +02:00
pancake e9b20fb9eb Release 3.5.0 2019-05-13 11:18:56 +02:00
pancake cabcd22f39 refix 2019-04-26 00:28:49 +02:00
pancake 65b16c4ea2 Fix build for udis 2019-04-26 00:25:37 +02:00
pancake 32caa03626 Fix bin-md380 crash 2019-04-20 11:48:55 +02:00
pancake 710bd658e3 Implement loadbuffer ni md380 2019-04-20 02:17:43 +02:00
pancake a39b5dfac7 Fix build of md380 bin 2019-04-20 02:15:27 +02:00
pancake 207a4677a1 Initial import of the r2emuhash 2019-04-14 13:35:49 +02:00
pancake 9eb4ca72bb Release 3.4.0 2019-04-01 22:16:24 +02:00
Fedor Sakharov 0459dfa816 fixes trimmed last bytes in disassembly (#195)
Fixes #194
2019-03-10 23:20:46 +08:00
pancake d8517a28ec Fix truncated numbers issue 2019-03-08 19:44:30 +01:00
pancake 5a0cc39fac Release 3.3.0 2019-02-19 14:50:08 +01:00
Andrew Barbarello 5883f35f20 yara-r2: replace r_io_read_at with r_io_pread_at
r_io_read_at is deprecated, and the intention is clearly to read all
bytes of the current file to be scanned with yara rules.
2019-02-17 16:25:15 +01:00
Andrew Barbarello 93f603828e yara-r2: remove unused yara2 sigs/refs to yara2 2019-02-17 16:25:15 +01:00
Andrew Barbarello fdcd534137 yara-r2: install to R2PM_USERPLUGIN_DIR
Makefile was using `R2_PLUGDIR`, which is no longer exported in
environment by `r2pm`, see
https://github.com/radare/radare2/issues/12751 .

Instead, we use `R2PM_USRPLUGIN_DIR`. Also update
`r_cmd_yara_load_default_rules` to load yara3 rules from the correct
path
2019-02-17 16:25:15 +01:00
54 changed files with 4208 additions and 819 deletions

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+13 -13
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@@ -32,33 +32,33 @@ addons:
env:
- TESTS="r2pm -i armthumb"
- TESTS="r2pm -i baleful"
# - TESTS="r2pm -i bcl" [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i bcl" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/157522362
- TESTS="r2pm -i blackfin"
- TESTS="r2pm -i blessr2"
# - TESTS="r2pm -i bpf" [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i dlang" [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i bpf" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/157522362
# - TESTS="r2pm -i dlang" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/157522362
- TESTS="r2pm -i dirtycow"
- TESTS="r2pm -i lang-duktape"
- TESTS="git clone git://git.code.sf.net/p/libdwarf/code libdwarf-code && cd libdwarf-code && ./configure && make && cd .. && r2pm -i dwarf-parser && cd radare2-regressions && ./r2r dwarf && cd .. && r2pm -u libdwarf && rm -rf libdwarf-code" #need to remove libdwarf? or travis destroys the vm so no issue in that?
- TESTS="r2pm -i r2frida"
# - TESTS="r2pm -i io-ewf" # https://github.com/travis-ci/apt-package-whitelist/issues/3205
# - TESTS="r2pm -i keystone-lib && r2pm -i keystone && cd radare2-regressions && make keystone && cd .." [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i keystone-lib && r2pm -i keystone && cd radare2-regressions && make keystone && cd .." [BR] https://travis-ci.org/radareorg/radare2-extras/builds/157522362
- TESTS="r2pm -i mc6809"
- TESTS="r2pm -i microblaze"
- TESTS="r2pm -i microblaze && cd radare2-regressions && make microblaze"
- TESTS="r2pm -i msil"
- TESTS="r2pm -i pcap"
- TESTS="r2pm -i ppcdisasm"
- TESTS="r2pm -i psosvm"
- TESTS="r2pm -i pyc"
# - TESTS="r2pm -i vala && r2pm -i valabind && r2pm -i r2api-python" [BR] https://travis-ci.org/radare/radare2-extras/builds/387043680
# - TESTS="r2pm -i r2pipe-cs" [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i r2pipe-go" [BR] https://travis-ci.org/radare/radare2-extras/builds/387043680
# - TESTS="r2pm -i vala && r2pm -i valabind && r2pm -i r2api-python" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/387043680
# - TESTS="r2pm -i r2pipe-cs" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/157522362
# - TESTS="r2pm -i r2pipe-go" [BR] https://travis-ci.org/radareorg/radare2-extras/builds/387043680
- TESTS="r2pm -i r2pipe-js"
- TESTS="r2pm -i r2pipe-py"
- TESTS="r2pm -i r2pipe-rb"
# - TESTS="r2pm -i r2pipe-vala" https://travis-ci.org/radare/radare2-extras/builds/157522362
# - TESTS="r2pm -i r2pipe-vala" https://travis-ci.org/radareorg/radare2-extras/builds/157522362
- TESTS="r2pm -i radare2"
# - TESTS="r2pm -i r2snow" https://travis-ci.org/radare/radare2-extras/jobs/199500082
# - TESTS="r2pm -i r2snow" https://travis-ci.org/radareorg/radare2-extras/jobs/199500082
# - TESTS="r2pm -i radeco" [BR] https://travis-ci.org/radare/radare2-extras/builds/157522362
- TESTS="r2pm -i retdec"
- TESTS="r2pm -i swf && cd radare2-regressions && make swf && cd .."
@@ -94,9 +94,9 @@ cache:
before_script:
- export WORKING_DIR=${TRAVIS_BUILD_DIR}/..
- cd ${WORKING_DIR}
- rm -rf ~/.nvm && git clone https://github.com/creationix/nvm.git ~/.nvm && (cd ~/.nvm && git checkout `git describe --abbrev=0 --tags`) && source ~/.nvm/nvm.sh && nvm install 7
- git clone https://github.com/radare/radare2-regressions
- git clone https://github.com/radare/radare2 && cd radare2
- rm -rf ~/.nvm && git clone https://github.com/creationix/nvm.git ~/.nvm && (cd ~/.nvm && git checkout `git describe --abbrev=0 --tags`) && source ~/.nvm/nvm.sh && nvm install 10
- git clone https://github.com/radareorg/radare2-regressions
- git clone https://github.com/radareorg/radare2 && cd radare2
- export CC=gcc-7
- ./configure --prefix=${WORKING_DIR}/install > /dev/null
- make -s -j2 > /dev/null
+2 -2
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@@ -1,4 +1,4 @@
radare2-extras [![Build Status](https://travis-ci.org/radare/radare2-extras.svg?branch=master)](https://travis-ci.org/radare/radare2-extras)
radare2-extras [![Build Status](https://travis-ci.org/radareorg/radare2-extras.svg?branch=master)](https://travis-ci.org/radareorg/radare2-extras)
==============
This repository contains extra plugins for radare2.
@@ -33,4 +33,4 @@ Building
The recommended way to build and install those plugins for users
is to use r2pm. See the radare2-pm repository for details:
https://github.com/radare/radare2-pm
https://github.com/radareorg/radare2-pm
+2 -2
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@@ -5,7 +5,7 @@
"main": "index.js",
"repository": {
"type": "git",
"url": "https://github.com/radare/radare2-bindings.git"
"url": "https://github.com/radareorg/radare2-bindings.git"
},
"keywords": [
"radare",
@@ -24,7 +24,7 @@
},
"license": "LGPL-3.0",
"bugs": {
"url": "https://github.com/radare/radare2-extras/issues"
"url": "https://github.com/radareorg/radare2-extras/issues"
},
"homepage": "http://www.radare.org",
"devDependencies": {
+1 -1
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@@ -28,7 +28,7 @@ make install
There are two known warnings:
* be sure to have the latest [radare2 from git](https://github.com/radare/radare2)
* be sure to have the latest [radare2 from git](https://github.com/radareorg/radare2)
* on mac systems radare2 should be installed with sys/install.sh (and not sys/user.sh) because the Makefile relies on a properly working `pkg-config`
## Example
+11
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@@ -0,0 +1,11 @@
This is the r2 plugin to read/write memory using the checkm8 exploit.
1. Clone https://github.com/axi0mX/ipwndfu
2. Copy this file into the root directory of this repository
3. r2 -I r2io.py ipwndfu://
4. enjoy
NOTES
* This is very unstable, reading on unallocated regions results in device reboot
* Requires python3 .. so maybe better use @geohot's fork
+65
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@@ -0,0 +1,65 @@
# iOS pwndfu checkm8 io plugin for radare2
# ========================================
#
# -- pancake @ nopcode.org
#
# Usage:
# r2 -I test-py-io.py pwndfu://
#
# The r2lang.plugin function exposes a way to register new plugins
# into the RCore instance. This API is only available from RLang.
# You must call with with '#!python test.py' or 'r2 -i test.py ..'
import r2lang
from dfuexec import *
FAKESIZE = 512
device = None
def pyio(a):
def _open(path, rw, perm):
global device
device = dfu.acquire_device()
serial_number = device.serial_number
dfu.release_device(device)
device = PwnedDFUDevice()
print("MyPyIO Opening %s"%(path))
return 1234
def _check(path, many):
print("python-check %s"%(path))
return path[0:9] == "pwndfu://"
def _read(offset, length):
global device
res = device.read_memory(address, length)
print("python-read")
return res
def _seek(offset, whence):
print("python-seek")
if whence == 0: # SET
return offset
if whence == 1: # CUR
return offset
if whence == 2: # END
return ROM_SIZE
return ROM_SIZE
def _write(offset, data, length):
print("TODO: python-write")
return True
def _system(cmd):
print("pwndfu://%s"%(cmd))
return True
return {
"name": "pwndfu",
"license": "GPL",
"desc": "pwndfu IO plugin (pwndfu://3)",
"check": _check,
"open": _open,
"read": _read,
"seek": _seek,
"write": _write,
"system": _system,
}
print("Registering Python IO plugin...")
print(r2lang.plugin("io", pyio))
Vendored
+6 -5
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@@ -1,5 +1,5 @@
#!/bin/sh
# This script was automatically generated by ACR v1.7.0
# This script was automatically generated by ACR v1.7.2
# @author: pancake <nopcode.org>
# @url: http://www.nopcode.org
# @repo: git clone https://github.com/radare/acr
@@ -64,6 +64,7 @@ if [ -e "${VPATH}/config.guess" ]; then
fi
CPU="`uname -m|sed -e 's, ,,g'|cut -d - -f 1`"
OS="`uname -s|tr A-Z a-z`"
uname -r | grep -qE "(Microsoft|WSL)" 2>/dev/null && OS="wsl"
GNU="`uname --help 2>&1 | grep gnu`"
[ "${GNU}" ] && OS="${OS}-gnu"
[ "${CPU}" = ppc ] && CPU="powerpc"
@@ -104,12 +105,12 @@ done
: ${INSTALL_PROGRAM_STRIP:=${INSTALL} -m 755 -s}
: ${INSTALL_MAN:=${INSTALL} -m 444}
: ${INSTALL_LIB:=${INSTALL} -m 755 -c}
PKGNAME='radare2-extras' ; VERSION='3.1.0' ; CONTACT_MAIL="[email protected]" ; CONTACT_NAME="pancake" ; CONTACT="pancake <[email protected]>" ;
PKGNAME='radare2-extras' ; VERSION='4.0.0' ; CONTACT_MAIL="[email protected]" ; CONTACT_NAME="pancake" ; CONTACT="pancake <[email protected]>" ;
}
show_usage() {
cat <<EOF2
'configure' configures radare2-extras-3.1.0 to adapt to many kinds of systems.
'configure' configures radare2-extras-4.0.0 to adapt to many kinds of systems.
Usage: ./configure [OPTION]... [VAR=VALUE]...
@@ -179,7 +180,7 @@ take_environ() {
}
show_version() {
echo "radare2-extras-3.1.0 configuration script done with acr v1.7.0.
echo "radare2-extras-4.0.0 configuration script done with acr v1.7.2.
The 'Free Software Foundation' message is only for autodetection.
Originally written by pancake <nopcode.org>."
exit 0
@@ -203,7 +204,7 @@ case $flag in
show_version ; ;;
-r|--r|--report)
echo "PKGNAME: radare2-extras"
echo "VERSION: 3.1.0"
echo "VERSION: 4.0.0"
echo "LANGS: c"
echo "OPTIONAL: libewf libyara"
echo "PKG-CONFIG: r_core libewf unicorn yara"
+1 -1
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@@ -1,5 +1,5 @@
PKGNAME radare2-extras
VERSION 3.1.0
VERSION 4.0.0
CONTACT pancake ; [email protected]
REPORT PREFIX ;
+1 -1
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@@ -51,7 +51,7 @@ RUN cd /opt/code && \
tar -Jxf ${VALA_TAR}.tar.xz
RUN cd /opt/code/${VALA_TAR}; ./configure --prefix=/usr ; make && make install
# compile radare and bindings
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
#install Go
+1 -1
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@@ -28,7 +28,7 @@ RUN cd /opt/code && \
tar -Jxf ${VALA_TAR}.tar.xz
RUN cd /opt/code/${VALA_TAR}; ./configure --prefix=/usr ; make && make install
# compile radare and bindings
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
#install Go
+2 -2
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@@ -39,7 +39,7 @@ RUN apt-get install -y python-pip jython
RUN cd /opt/code; wget http://download.gnome.org/sources/vala/0.24/vala-0.24.0.tar.xz; tar -Jxf vala-0.24.0.tar.xz
RUN cd /opt/code/vala-0.24.0; ./configure --prefix=/usr ; make && make install
# compile radare
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
# Clean up APT when done.
RUN apt-get clean && rm -rf /var/lib/apt/lists/* /tmp/* /var/tmp/*
@@ -48,7 +48,7 @@ RUN apt-get clean && rm -rf /var/lib/apt/lists/* /tmp/* /var/tmp/*
RUN cd /opt/code; wget http://download.gnome.org/sources/vala/0.24/vala-0.24.0.tar.xz; tar -Jxf vala-0.24.0.tar.xz
RUN cd /opt/code/vala-0.24.0; ./configure --prefix=/usr ; make && make install
# compile radare
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
#install oracle jre stuffs
+2 -2
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@@ -23,7 +23,7 @@ RUN apt-get install -y python-pip jython
RUN cd /opt/code; wget http://download.gnome.org/sources/vala/0.24/vala-0.24.0.tar.xz; tar -Jxf vala-0.24.0.tar.xz
RUN cd /opt/code/vala-0.24.0; ./configure --prefix=/usr ; make && make install
# compile radare
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
# Clean up APT when done.
RUN apt-get clean && rm -rf /var/lib/apt/lists/* /tmp/* /var/tmp/*
@@ -32,7 +32,7 @@ RUN apt-get clean && rm -rf /var/lib/apt/lists/* /tmp/* /var/tmp/*
RUN cd /opt/code; wget http://download.gnome.org/sources/vala/0.24/vala-0.24.0.tar.xz; tar -Jxf vala-0.24.0.tar.xz
RUN cd /opt/code/vala-0.24.0; ./configure --prefix=/usr ; make && make install
# compile radare
RUN cd /opt/code; git clone https://github.com/radare/radare2.git; cd radare2; ./sys/all.sh
RUN cd /opt/code; git clone https://github.com/radareorg/radare2.git; cd radare2; ./sys/all.sh
#install oracle jre stuffs
+3 -2
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@@ -1,5 +1,5 @@
#!/bin/sh
# This script was automatically generated by ACR v1.7.0
# This script was automatically generated by ACR v1.7.2
# @author: pancake <nopcode.org>
# @url: http://www.nopcode.org
# @repo: git clone https://github.com/radare/acr
@@ -62,6 +62,7 @@ if [ -e "${VPATH}/config.guess" ]; then
fi
CPU="`uname -m|sed -e 's, ,,g'|cut -d - -f 1`"
OS="`uname -s|tr A-Z a-z`"
uname -r | grep -qE "(Microsoft|WSL)" 2>/dev/null && OS="wsl"
GNU="`uname --help 2>&1 | grep gnu`"
[ "${GNU}" ] && OS="${OS}-gnu"
[ "${CPU}" = ppc ] && CPU="powerpc"
@@ -176,7 +177,7 @@ take_environ() {
}
show_version() {
echo "radare2-keystone-0.1 configuration script done with acr v1.7.0.
echo "radare2-keystone-0.1 configuration script done with acr v1.7.2.
The 'Free Software Foundation' message is only for autodetection.
Originally written by pancake <nopcode.org>."
exit 0
+3 -1
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@@ -191,7 +191,9 @@ int x86_udis86_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len)
op->id = u.mnemonic;
oplen = op->size = ud_insn_len (&u);
r_strbuf_init (&op->esil);
if (anal->decode && (handler = udis86_esil_get_handler (u.mnemonic))) {
const bool decode = true;
if (decode && (handler = udis86_esil_get_handler (u.mnemonic))) {
info.oplen = oplen;
//if (anal->bits==32)
info.bitmask = UT32_MAX;
+4 -1
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@@ -150,7 +150,10 @@ int evm_dis(EvmOp *op, const unsigned char *buf, int buf_len) {
{
int pushSize = buf[0] - EVM_OP_PUSH1;
char hexbuf[64] = {0};
r_hex_bin2str(buf + 1, pushSize, hexbuf);
int res = r_hex_bin2str (buf + 1, pushSize + 1, hexbuf);
if (res < 1 || !*hexbuf) {
strcpy (hexbuf, "0");
}
settxtf (op, "push%d 0x%s", pushSize + 1, hexbuf);
op->len = 2 + pushSize;
}
+23 -1
View File
@@ -571,7 +571,29 @@ void bfd_putl16 (bfd_vma, void *);
/* Byte swapping routines which take size and endiannes as arguments. */
bfd_uint64_t bfd_get_bits (const void *, int, bfd_boolean);
//bfd_uint64_t bfd_get_bits (const void *, int, bfd_boolean);
static inline bfd_uint64_t
bfd_get_bits (const void *p, int bits, bfd_boolean big_p)
{
const bfd_byte *addr = (const bfd_byte *) p;
bfd_uint64_t data;
int i;
int bytes;
if (bits % 8 != 0)
return 0;
data = 0;
bytes = bits / 8;
for (i = 0; i < bytes; i++)
{
int addr_index = big_p ? i : bytes - i - 1;
data = (data << 8) | addr[addr_index];
}
return data;
}
void bfd_put_bits (bfd_uint64_t, void *, int, bfd_boolean);
extern bfd_boolean bfd_section_already_linked_table_init (void);
+1 -3
View File
@@ -13,11 +13,9 @@ static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
0
};
const char *buf_asm = "invalid";
evm_dis (&eop, buf, len);
buf_asm = sdb_fmt ("%s", eop.txt);
op->size = eop.len;
r_asm_op_set_asm (op, buf_asm);
r_asm_op_set_asm (op, eop.txt);
return eop.len;
}
+24 -24
View File
@@ -205,15 +205,15 @@ static RList *r_debug_unicorn_map_get(RDebug *dbg) {
RDebugMap *m;
RList *list;
SdbListIter *iter;
RIOSection *sect;
RIOMap *map;
int i = 0;
list = r_list_new ();
//list->free = r_debug_map_free;
ls_foreach (dbg->iob.io->sections, iter, sect) {
m = r_debug_map_new (sect->name,
sect->vaddr,
sect->vaddr + sect->vsize,
sect->perm, 0);
ls_foreach (dbg->iob.io->maps, iter, map) {
m = r_debug_map_new (map->name,
map->itv.addr,
map->itv.addr + map->itv.size,
map->perm, 0);
if (m) {
r_list_append (list, m);
}
@@ -510,7 +510,7 @@ static int r_debug_unicorn_wait(RDebug *dbg, int pid) {
static int r_debug_unicorn_init(RDebug *dbg) {
SdbListIter *iter;
int code_is_mapped;
RIOSection *sect;
RIOMap *map;
int bits = (dbg->bits & R_SYS_BITS_64) ? 64: 32;
uc_err err;
if (uh) {
@@ -532,7 +532,7 @@ static int r_debug_unicorn_init(RDebug *dbg) {
return false;
}
ut64 lastvaddr = 0LL;
int n_sect = ls_length (dbg->iob.io->sections);
int n_sect = ls_length (dbg->iob.io->maps);
if (n_sect == 0) {
message (logo);
message ("[UNICORN] dpa # reatach to initialize the unicorn\n");
@@ -540,35 +540,35 @@ static int r_debug_unicorn_init(RDebug *dbg) {
}
code_is_mapped = 0;
ls_foreach (dbg->iob.io->sections, iter, sect) {
ls_foreach (dbg->iob.io->maps, iter, map) {
int perms = 0;
if (sect->perm & R_PERM_R) perms |= UC_PROT_READ;
if (sect->perm & R_PERM_W) perms |= UC_PROT_WRITE;
if (sect->perm & R_PERM_X) perms |= UC_PROT_EXEC;
ut64 mapbase = sect->vaddr >> 12 << 12;
int bufdelta = sect->vaddr - mapbase;
if (map->perm & R_PERM_R) perms |= UC_PROT_READ;
if (map->perm & R_PERM_W) perms |= UC_PROT_WRITE;
if (map->perm & R_PERM_X) perms |= UC_PROT_EXEC;
ut64 mapbase = map->itv.addr >> 12 << 12;
int bufdelta = map->itv.addr - mapbase;
ut32 vsz = 64 * 1024;
ut8 *buf;
if (sect->vaddr < lastvaddr)
if (map->itv.addr < lastvaddr)
continue;
if (!(sect->perm & 1))
if (!(map->perm & 1))
continue;
if (!strstr (sect->name, "text"))
if (!strstr (map->name, "text"))
continue;
buf = calloc (vsz+bufdelta+1024, 1);
if (!buf) continue;
message ("[UNICORN] BASE 0x%08"PFMT64x"\n", mapbase);
//message ("DELTA = %d SIZE = %d\n", bufdelta,
//R_MIN (sect->vsize, (vsz - bufdelta)));
dbg->iob.read_at (dbg->iob.io, sect->vaddr, buf + bufdelta,
R_MIN (sect->vsize, (vsz - bufdelta)));
//R_MIN (map->itv.size, (vsz - bufdelta)));
dbg->iob.read_at (dbg->iob.io, map->itv.addr, buf + bufdelta,
R_MIN (map->itv.size, (vsz - bufdelta)));
message ("[UNICORN] Segment 0x%08"PFMT64x" 0x%08"PFMT64x" Size %d\n",
sect->vaddr, sect->vaddr + vsz, vsz);
map->itv.addr, map->itv.addr + vsz, vsz);
err = uc_mem_map_ptr (uh, mapbase, vsz, perms, buf);
if (err) {
message("[UNICORN] muc_mem_map_ptr failed to allocated %d\n", vsz);
}
//err = uc_mem_write (uh, sect->vaddr, buf, vsz);
//err = uc_mem_write (uh, map->itv.addr, buf, vsz);
/*
err = uc_mem_write (uh, mapbase, buf, vsz);
if (err) {
@@ -577,9 +577,9 @@ static int r_debug_unicorn_init(RDebug *dbg) {
//eprintf ("%02x %02x\n", buf[0], buf[1]);
//eprintf ("WRT = %d\n", err);
//err = uc_mem_read (uh, mapbase, buf, vsz); //sect->vsize+bufdelta);
//err = uc_mem_read (uh, mapbase, buf, vsz); //map->itv.size+bufdelta);
//eprintf ("RAD = %d\n", err);
lastvaddr = sect->vaddr + sect->vsize;
lastvaddr = map->itv.addr + map->itv.size;
code_is_mapped = 1;
if (JUST_FIRST_BLOCK) break;
//break;
+11
View File
@@ -0,0 +1,11 @@
all:
$(MAKE) -C bin-fw
$(MAKE) -C io-dfu
install:
$(MAKE) -C bin-fw install
$(MAKE) -C io-dfu install
uninstall:
$(MAKE) -C bin-fw uninstall
$(MAKE) -C io-dfu uninstall
+21 -14
View File
@@ -1,7 +1,8 @@
/* radare2 - LGPL - Copyright 2017 - pancake */
/* radare2 - LGPL - Copyright 2017-2019 - pancake */
#include <r_lib.h>
#include <r_bin.h>
#include <r_util.h>
static bool check_bytes(const ut8 *buf, ut64 length) {
if (buf && length >= 32) {
@@ -13,18 +14,23 @@ static bool check_bytes(const ut8 *buf, ut64 length) {
}
static ut32 readLE32(RBuffer *buf, int off) {
int left = 0;
const ut8 *data = r_buf_get_at (buf, off, &left);
return left > 3? r_read_le32 (data): 0;
return r_buf_read_le32_at (buf, off);
}
static void * load_bytes(RBinFile *arch, const ut8 *buf, ut64 sz, ut64 loadaddr, Sdb *sdb){
return (void*)(size_t)check_bytes (buf, sz);
static bool load_bytes(RBinFile *bf, void **bin_obj, const ut8 *buf, ut64 sz, ut64 loadaddr, Sdb *sdb){
return (bool)(void*)(size_t)check_bytes (buf, sz);
}
static void * load_buffer(RBinFile *arch, RBuffer *buf, ut64 loadaddr, Sdb *sdb){
ut8 data[64];
int data_len = r_buf_read_at (buf, 0, data, sizeof (data));
void *bo = NULL;
return (void*)(bool)(load_bytes (arch, &bo, data, data_len, loadaddr, sdb));
}
static bool load(RBinFile *arch) {
const ut8 *bytes = arch ? r_buf_buffer (arch->buf) : NULL;
ut64 sz = arch ? r_buf_size (arch->buf): 0;
ut64 sz;
const ut8 *bytes = arch ? r_buf_buffer (arch->buf, &sz) : NULL;
return check_bytes (bytes, sz);
}
@@ -61,16 +67,17 @@ static RList* sections(RBinFile *bf) {
if (!(ptr = R_NEW0 (RBinSection))) {
return ret;
}
ut64 vaddr = (ut64)readLE32(bf->buf, 0x80);
ut64 vaddr = (ut64)readLE32 (bf->buf, 0x80);
ut64 psize = (ut64)readLE32(bf->buf, 0x84);
strncpy (ptr->name, "system", R_BIN_SIZEOF_STRINGS);
ptr->name = strdup ("system");
ptr->size = psize;
ptr->arch = strdup ("arm");
ptr->bits = 16;
ptr->vsize = psize;
ptr->paddr = 0x100;
ptr->vaddr = vaddr;
ptr->srwx = R_BIN_SCN_READABLE | R_BIN_SCN_EXECUTABLE | R_BIN_SCN_MAP; // r-x
ptr->perm = R_PERM_RX;
ptr->add = true;
r_list_append (ret, ptr);
return ret;
@@ -98,9 +105,8 @@ static RBinInfo* info(RBinFile *bf) {
ret->os = strdup ("tytera");
ret->arch = strdup ("arm");
ret->machine = strdup (ret->arch);
int left;
const char *subSystem = (const char *)r_buf_get_at (bf->buf, 0x10, &left);
ret->subsystem = strdup (left>0?subSystem: "");
int left;
ret->subsystem = r_buf_get_string (bf->buf, 0x10);
ret->type = strdup ("Firmware");
ret->bits = 16;
ret->has_va = true;
@@ -120,6 +126,7 @@ RBinPlugin r_bin_plugin_bcl = {
.license = "BSD",
.load = &load,
.load_bytes = &load_bytes,
.load_buffer = &load_buffer,
.size = &size,
// .check = &check,
.check_bytes = &check_bytes,
File diff suppressed because it is too large. Load diff
@@ -476,7 +476,7 @@ microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
{
*targetvalid = FALSE;
}
else if (op->instr_type == branch_inst)
else if ((op->instr_type == branch_inst) || (op->instr_type == branch_inst_imm))
{
switch (op->inst_type)
{
+290 -291
View File
@@ -106,313 +106,312 @@
static struct op_code_struct
{
char *name;
short inst_type; /* Registers and immediate values involved. */
short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
short delay_slots; /* Info about delay slots needed after this instr. */
short immval_mask;
unsigned long bit_sequence; /* All the fixed bits for the op are set and
char *name;
short inst_type; /* Registers and immediate values involved. */
short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
short delay_slots; /* Info about delay slots needed after this instr. */
short immval_mask;
unsigned long bit_sequence; /* All the fixed bits for the op are set and
all the variable bits (reg names, imm vals)
are set to 0. */
unsigned long opcode_mask; /* Which bits define the opcode. */
enum microblaze_instr instr;
enum microblaze_instr_type instr_type;
/* More info about output format here. */
unsigned long opcode_mask; /* Which bits define the opcode. */
enum microblaze_instr instr;
enum microblaze_instr_type instr_type;
/* More info about output format here. */
} opcodes[MAX_OPCODES] =
{
{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
{"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
{"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
{"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
{"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
{"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
{"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
{"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
{"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
{"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
{"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
{"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
{"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
{"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
{"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
{"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
{"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
{"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
{"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
{"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
{"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
{"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
{"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
{"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
{"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
{"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
{"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
{"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
{"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
{"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
{"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
{"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
{"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
{"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
{"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
{"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
{"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
{"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
{"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
{"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
{"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
{"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
{"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
{"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
{"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
{"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
{"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
{"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
{"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
{"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
{"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
{"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
{"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
{"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
{"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
{"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
{"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
{"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
{"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
{"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
{"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
{"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
{"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
{"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
{"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
{"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
{"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
{"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
{"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
{"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
{"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
{"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
{"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
{"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
{"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
{"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
{"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0. */
{"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */
{"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */
{"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */
{"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */
{"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */
{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */
{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
{"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
{"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
{"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
{"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
{"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
{"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
{"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
{"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
{"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
{"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
{"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
{"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
{"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst_imm },
{"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst_imm },
{"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst_imm },
{"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst_imm },
{"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst_imm },
{"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst_imm },
{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst_imm },
{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst_imm },
{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
{"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
{"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
{"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
{"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
{"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
{"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
{"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
{"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
{"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
{"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
{"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
{"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
{"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
{"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
{"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
{"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
{"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
{"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
{"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
{"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
{"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
{"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
{"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
{"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
{"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
{"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
{"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
{"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
{"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
{"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
{"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
{"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
{"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
{"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
{"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
{"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
{"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst_imm },
{"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst_imm },
{"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst_imm },
{"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst_imm },
{"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst_imm },
{"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst_imm },
{"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst_imm },
{"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst_imm },
{"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst_imm },
{"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst_imm },
{"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst_imm },
{"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst_imm },
{"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst_imm },
{"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst_imm },
{"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst_imm },
{"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst_imm },
{"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst_imm },
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst_imm },
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst_imm },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
{"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
{"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
{"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
{"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
{"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
{"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
{"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
{"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
{"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
{"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0. */
{"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */
{"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */
{"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */
{"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */
{"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */
{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */
{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
{"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
{"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
{"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
{"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
{"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
{"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
{"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
{"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
{"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{NULL, 0, 0, 0, 0, 0, 0, 0, 0},
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
{"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
{"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
{"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
{"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{NULL, 0, 0, 0, 0, 0, 0, 0, 0},
};
/* Prefix for register names. */
char register_prefix[] = "r";
char special_register_prefix[] = "spr";
char fsl_register_prefix[] = "rfsl";
char pvr_register_prefix[] = "rpvr";
@@ -25,45 +25,45 @@
enum microblaze_instr
{
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
shr, sw, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
eget, ecget, neget, necget, eput, ecput, neput, necput,
teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
aget, caget, naget, ncaget, aput, caput, naput, ncaput,
taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
invalid_inst
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
shr, sw, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
eget, ecget, neget, necget, eput, ecput, neput, necput,
teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
aget, caget, naget, ncaget, aput, caput, naput, ncaput,
taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
invalid_inst
};
enum microblaze_instr_type
{
arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
return_inst, immediate_inst, special_inst, memory_load_inst,
memory_store_inst, barrel_shift_inst, anyware_inst
arithmetic_inst, arithmetic_inst_imm, logical_inst, mult_inst, div_inst, branch_inst,
branch_inst_imm, return_inst, immediate_inst, special_inst, memory_load_inst,
memory_store_inst, barrel_shift_inst, anyware_inst
};
#define INST_WORD_SIZE 4
@@ -27,6 +27,7 @@
#include "dis-asm.h"
#include <stdlib.h>
#include <string.h>
#include <r_asm.h>
#include "microblaze-opc.h"
#include "microblaze-dis.h"
@@ -96,8 +97,8 @@ get_field_imm15 (long instr)
static char *
get_field_special (long instr, struct op_code_struct * op)
{
char tmpstr[25];
char spr[6];
char *tmpstr;
char spr[6];
switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
{
@@ -150,18 +151,18 @@ get_field_special (long instr, struct op_code_struct * op)
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
== REG_PVR_MASK)
{
sprintf (tmpstr, "%spvr%d", register_prefix,
tmpstr = r_str_newf ("%spvr%d", register_prefix,
(unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
^ op->immval_mask) ^ REG_PVR_MASK);
return (strdup (tmpstr));
return (tmpstr);
}
else
strcpy (spr, "pc");
break;
}
sprintf (tmpstr, "%s%s", register_prefix, spr);
return (strdup (tmpstr));
tmpstr = r_str_newf ("%s", spr);
return (tmpstr);
}
static unsigned long
+100
View File
@@ -0,0 +1,100 @@
#!/bin/sh
# This script is suposed to be executed from r2
SDB=~/prg/radare2/shlr/sdb/src/sdb
#r="r2 -1"
#r="rax2"
r="r2cmd"
walkbbs() {
at=$1
bbs=`$r afbq @ $at`
for bb in $bbs ; do
bbsz=`$r '?v $Fs @'$bb`
echo "$bb $bbsz"
done
}
match() {
export SDB=$SDB
A="$1"
if [ -z "$A" ]; then
A=ls.sdb
fi
for B in db/*.sdb ; do
if [ "$A" = "$B" ]; then
continue
fi
AKEYS=`$SDB $A |cut -d = -f1`
BKEYS=`$SDB $B |cut -d = -f1`
for a in ${AKEYS} ; do
for b in ${BKEYS} ; do
if [ "$a" = "$b" ]; then
N=`$SDB $A $a`
M=`$SDB $B $a`
echo "CC $A $N is similar to $B $M"
break
fi
done
done
done
}
if [ -z "$R2PIPE_IN" ]; then
if [ -z "$1" ]; then
echo "Usage: r2emuha.sh [make|find] [file]"
echo " $ r2emuha.sh make /bin/ls"
echo " $ r2emuha.sh make /bin/sleep"
echo " $ r2emuha.sh find ls.sdb"
else
case "$1" in
"make")
r2 -qAA -i $0 "$2"
;;
"find")
match "$2"
;;
*)
echo "Unknown command. Use: make or find."
exit 1
;;
esac
fi
exit 0
fi
emuhash() {
at=$1
name=`$r fd@$at`
$r 'drw 0' > /dev/null # reset register values to 0
$r aeim > /dev/null # initialize vm and set SP, BP, PC
$r 'dr??' > .r0
$r "aef $at 2>/dev/null" > /dev/null
$r 'dr??' > .r1
diff -ru .r0 .r1 | grep -v PC | grep -e '^- ' -e '^+ ' > .d
#cat .d
crc32=`rahash2 -qqa crc32 .d`
if [ "$crc32" = 00000000 ]; then
printf "$at $crc32 $name (ignored)\r"
else
echo "$at $crc32 $name"
echo "$crc32=$name" >> ${SDBTXT}
fi
rm -f .r0 .r1 .d
}
FILE=$(`$r i~^file` | grep bin | cut -d : -f 1)
NAME=db/`basename "$FILE"`
echo "FILE=$FILE"
echo "NAME=$NAME"
SDBBDS=${NAME}.sdb
SDBTXT=${SDBBDS}.txt
:> ${SDBTXT}
fcns=`$r aflq`
for a in $fcns ; do
emuhash $a
done
$SDB ${SDBBDS} = < ${SDBTXT}
+5
View File
@@ -0,0 +1,5 @@
language: python
python:
- "2.7"
- "3.4"
+25
View File
@@ -0,0 +1,25 @@
# radare2ida
This repository contains a collection of documents, scripts
and utilities that will allow you to use IDA and R2, converting
projects metadata from one tool to the other and providing
tools to integrate them in a more useful way.
In progress:
* Documentation about how to use the tool
* Export IDB from IDA into a radare2 script
* Import radare2 project metadata into IDA database
* Launch r2 from IDA
* Use IDA as an IO backend for R2
* Expose R2 functionalities into IDA
* Assembler/Disassembler
* Base converter
* ROP gadget search
* ...
## ida2r2
**Note:** This requires the [python-idb](https://github.com/williballenthin/python-idb) installed
and available for python imports. It is recommended to use the latest version of
`python-idb` by cloning the repository and installing it using `python setup.py install`.
+4
View File
@@ -0,0 +1,4 @@
Migration from IDA to Radare2
=============================
https://radare.gitbooks.io/radare2book/content/debugger/migration.html
+494
View File
@@ -0,0 +1,494 @@
#!/usr/bin/env python
""" Convert IDB and IDC from IDA into a radare2 script
$ ida2r2.py -h
usage: ida2r2.py [-h] (-idb IDB_FILE | -idc IDC_FILE) -o OUT_FILE [-nc | -nf | -nn]
Export IDB or IDC from IDA into a radare2 initialization script
optional arguments:
-h, --help show this help message and exit
-idb IDB_FILE, --IDBFile IDB_FILE
Path to the IDB file
-idc IDC_FILE, --IDCFile IDC_FILE
Path to the IDC file
-o OUT_FILE, --OutputFile OUT_FILE
Export to a specified file path
-nc, --no-comments Don't convert comments
-nf, --no-functions Don't convert functions
-nn, --no-names Don't convert names
"""
__author__ = "Itay Cohen (@megabeets_), Maxime Morin (@maijin), Sergi Alvarez (@pancake)"
import argparse
import idb
import sys
import re
import base64
# CONSTANTS
FLAG_PREFIX="ida."
def get_args():
''' Handle arguments using argparse
'''
arg_parser = argparse.ArgumentParser(
description="Export IDB or IDC from IDA into a radare2 initialization script")
arg_group_files = arg_parser.add_mutually_exclusive_group(required=True)
arg_group_files.add_argument("-idb", "--IDBFile",
action="store",
dest="idb_file",
help="Path to the IDB file")
arg_group_files.add_argument("-idc", "--IDCFile",
action="store",
dest="idc_file",
help="Path to the IDC file")
arg_parser.add_argument("-o", "--OutputFile",
action="store",
dest="out_file",
required=True,
help="Export to a specified file path")
arg_parser.add_argument("-nc", "--no-comments",
dest="is_comments",
action="store_false",
help="Don't convert comments")
arg_parser.add_argument("-nf", "--no-functions",
dest="is_functions",
action="store_false",
help="Don't convert functions")
arg_parser.add_argument("-nn", "--no-names",
dest="is_names",
action="store_false",
help="Don't convert names")
arg_parser.set_defaults(is_comments=True, is_functions=True, is_names=True)
args = arg_parser.parse_args()
return args
def write_header():
outfile.write("""########################################################
#
# This file was generated by the ida2r2.py script.
# Source: https://github.com/radare/radare2ida
#
########################################################
""")
###
# IDB Parsing
#
def idb2r2_comments(api, textseg):
''' Convert comments from a specific text segments in the IDB
'''
for ea in range(textseg, api.idc.SegEnd(textseg)):
try:
flags = api.ida_bytes.get_cmt(ea, True)
if flags != "":
outfile.write("CCu base64:{b64} @ {addr}\n".format(
b64=base64.b64encode(flags.encode(encoding='UTF-8')).decode("utf-8"),
addr=str(ea)
))
except Exception as e:
try:
flags = api.ida_bytes.get_cmt(ea, False)
outfile.write("CCu base64:{b64} @ {addr}\n".format(
b64=base64.b64encode(flags.encode(encoding='UTF-8')).decode("utf-8"),
addr=str(ea)
))
except:
pass
def idb2r2_functions(api):
''' Convert all functions from the IDB
'''
outfile.write("\n# IDB Functions\n")
for ea in api.idautils.Functions():
outfile.write("f {prefix}{name} @ {addr}\n".format(
prefix=FLAG_PREFIX,
name=api.idc.GetFunctionName(ea).replace("@", "_"),
addr=str(ea)
))
# Write the command responsible to analyze these functions
outfile.write("aF @@ {prefix}*\n".format(prefix=FLAG_PREFIX))
def idb2r2_names(api):
''' Convert all names from the IDB
'''
outfile.write("\n# IDB Names\n")
for ea, name in api.idautils.Names():
outfile.write("f {prefix}{name} @ {addr}\n".format(
prefix=FLAG_PREFIX,
name=name.replace("@", "_"),
addr=str(ea)
))
def idb_parse(args):
global outfile
with idb.from_file(args.idb_file) as db:
api = idb.IDAPython(db)
# Compatability check for those who install python-idb from pip
try:
baddr = hex(api.ida_nalt.get_imagebase())
except:
baddr = "[base address]"
outfile = open(args.out_file, 'w')
write_header()
print("[+] Starting conversion from '%s' to '%s'" %
(args.idb_file, args.out_file))
if args.is_functions:
idb2r2_functions(api)
if args.is_names:
idb2r2_names(api)
if args.is_comments:
segs = idb.analysis.Segments(db).segments
outfile.write("\n# IDB Comments\n")
for segment in segs.values():
idb2r2_comments(api, segment.startEA)
print("[+] Conversion done.\n")
print("[!] Execute: r2 -i %s -B %s [program]\n" %
(args.out_file, baddr))
#
# End of IDB Parsing
###
# -------------------------------------------------------------------
###
# IDC Parsing
#
class Func(object):
# FIXME: parse ftype into params and values
def __init__(self, name="unknown", params=[], values=[], address=0, size=0, ftype=""):
self.name = name
self.params = params
self.values = values
self.address = address
self.size = size
self.ftype = ftype
class Llabel(object):
def __init__(self, name="unknown", address=0):
self.name = name
self.address = address
class Comm(object):
def __init__(self, text="", address=0):
self.text = text
self.address = address
class Enum(object):
def __init__(self, name="unknown", members=[]):
self.name = name
self.members = members
class Struct(object):
def __init__(self, name="unknown", members=[]):
self.name = name
self.members = members
class Union(object):
def __init__(self, name="unknown", members=[]):
self.name = name
self.members = members
class Type(object):
def __init__(self, name="unknown"):
self.name = name
self.members = members
# ----------------------------------------------------------------------
functions = []
llabels = []
comments = []
structs = []
enums = []
types = []
def idc_functions_parse(idc):
# MakeFunction (0XF3C99,0XF3CA8);
mkfun_re = re.compile("""
(?m) # Multiline
^[ \t]*MakeFunction[ \t]*\(
(?P<fstart>0[xX][\dA-Fa-f]{1,8}) # Function start
[ \t]*\,[ \t]*
(?P<fend>0[xX][\dA-Fa-f]{1,8}) # Function end
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkfun_group_name = dict([(v,k) for k,v in mkfun_re.groupindex.items()])
mkfun = mkfun_re.finditer(idc)
for match in mkfun :
fun = Func()
for group_index,group in enumerate(match.groups()) :
if group :
if mkfun_group_name[group_index+1] == "fstart" :
fun.address = int(group, 16)
if mkfun_group_name[group_index+1] == "fend" :
fun.size = int(group, 16) - fun.address
functions.append(fun)
# SetFunctionFlags (0XF3C99, 0x400);
mkfunflags_re = re.compile("""
(?m) # Multiline
^[ \t]*SetFunctionFlags[ \t*]\(
(?P<fstart>0[xX][\dA-Fa-f]{1,8}) # Function start
[ \t]*\,[ \t]*
(?P<flags>0[xX][\dA-Fa-f]{1,8}) # Flags
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkfunflags_group_name = dict([(v,k) for k,v in mkfunflags_re.groupindex.items()])
mkfunflags = mkfunflags_re.finditer(idc)
for match in mkfunflags :
for group_index,group in enumerate(match.groups()) :
if group :
if mkfunflags_group_name[group_index+1] == "fstart" :
addr = int(group, 16)
if mkfunflags_group_name[group_index+1] == "flags" :
for fun in functions :
if fun.address == addr :
pass # TODO: parse flags
# MakeFrame (0XF3C99, 0, 0, 0);
# MakeName (0XF3C99, "SIO_port_setup_S");
mkname_re = re.compile("""
(?m) # Multiline
^[ \t]*MakeName[ \t]*\(
(?P<fstart>0[xX][\dA-Fa-f]{1,8}) # Function start
[ \t]*\,[ \t]*
"(?P<fname>.*)" # Function name
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkname_group_name = dict([(v,k) for k,v in mkname_re.groupindex.items()])
mkname = mkname_re.finditer(idc)
for match in mkname :
for group_index,group in enumerate(match.groups()) :
if group :
if mkname_group_name[group_index+1] == "fstart" :
addr = int(group, 16)
if mkname_group_name[group_index+1] == "fname" :
for fun in functions :
if fun.address == addr :
fun.name = group
# SetType (0XFFF72, "__int32 __cdecl PCI_ByteWrite_SL(__int32 address, __int32 value)");
mkftype_re = re.compile("""
(?m) # Multiline
^[ \t]*SetType[ \t]*\(
(?P<fstart>0[xX][\dA-Fa-f]{1,8}) # Function start
[ \t]*\,[ \t]*
"(?P<ftype>.*)" # Function type
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkftype_group_name = dict([(v,k) for k,v in mkftype_re.groupindex.items()])
mkftype = mkftype_re.finditer(idc)
for match in mkftype :
for group_index,group in enumerate(match.groups()) :
if group :
if mkftype_group_name[group_index+1] == "fstart" :
addr = int(group, 16)
if mkftype_group_name[group_index+1] == "ftype" :
for fun in functions :
if fun.address == addr :
fun.ftype = group
# MakeNameEx (0xF3CA0, "return", SN_LOCAL);
mklocal_re = re.compile("""
(?m) # Multiline
^[ \t]*MakeNameEx[ \t]*\(
(?P<laddr>0[xX][\dA-Fa-f]{1,8}) # Local label address
[ \t]*\,[ \t]*
"(?P<lname>.*)" # Local label name
[ \t]*\,[ \t]*SN_LOCAL
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mklocal_group_name = dict([(v,k) for k,v in mklocal_re.groupindex.items()])
mklocal = mklocal_re.finditer(idc)
for match in mklocal :
lab = Llabel()
for group_index,group in enumerate(match.groups()) :
if group :
if mklocal_group_name[group_index+1] == "laddr" :
lab.address = int(group, 16)
if mklocal_group_name[group_index+1] == "lname" :
lab.name = group
llabels.append(lab)
# ----------------------------------------------------------------------
def idc_enums_parse(idc):
pass
# ----------------------------------------------------------------------
def idc_structs_parse(idc):
# id = AddStrucEx (-1, "struct_MTRR", 0);
mkstruct_re = re.compile("""
(?m) # Multiline
^[ \t]*id[ \t]*=[ \t]*AddStrucEx[ \t]*\(
[ \t]*-1[ \t]*,[ \t]*
"(?P<sname>.*)" # Structure name
[ \t]*\,[ \t]*0
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkstruct_group_name = dict([(v,k) for k,v in mkstruct_re.groupindex.items()])
mkstruct = mkstruct_re.finditer(idc)
for match in mkstruct :
s = Struct()
for group_index,group in enumerate(match.groups()) :
if group :
if mkstruct_group_name[group_index+1] == "sname" :
s.name = group
structs.append(s)
# Case 1: not nested structures
# =============================
# id = GetStrucIdByName ("struct_header");
# mid = AddStructMember(id,"BCPNV", 0, 0x5000c500, 0, 7);
# mid = AddStructMember(id,"_", 0X7, 0x00500, -1, 1);
# mid = AddStructMember(id, "BCPNV_size",0X8, 0x004500, -1, 1);
mkstruct_re = re.compile("""
(?m) # Multiline
^[ \t]*id[ \t]*=[ \t]*GetStrucIdByName[ \t]*\(
[ \t]*-1[ \t]*,[ \t]*
"(?P<sname>.*)" # Structure name
[ \t]*\,[ \t]*0
[ \t]*\);[ \t]*$
""", re.VERBOSE)
# ----------------------------------------------------------------------
def idc_comments_parse(idc):
# MakeComm (0XFED3D, "PCI class 0x600 - Host/PCI bridge");
mkcomm_re = re.compile("""
(?m) # Multiline
^[ \t]*MakeComm[ \t]*\(
(?P<caddr>0[xX][\dA-Fa-f]{1,8}) # Comment address
[ \t]*\,[ \t]*
"(?P<ctext>.*)" # Comment
[ \t]*\);[ \t]*$
""", re.VERBOSE)
mkcomm_group_name = dict([(v,k) for k,v in mkcomm_re.groupindex.items()])
mkcomm = mkcomm_re.finditer(idc)
for match in mkcomm :
for group_index,group in enumerate(match.groups()) :
if group :
if mkcomm_group_name[group_index+1] == "caddr" :
address = int(group, 16)
if mkcomm_group_name[group_index+1] == "ctext" :
com_multi = group.split('\\n')
for a in com_multi :
com = Comm()
com.address = address
com.text = a
comments.append(com)
# ----------------------------------------------------------------------
# print("af+ 0x%08lx %d %s" % (func.address, func.size, func.name))
def idc_generate_r2(out_file):
global outfile
outfile = open(out_file, 'w')
write_header()
for f in functions :
if f.name != "unknown" :
outfile.write("af+ {addr} {size} {name}\n".format(
addr=hex(f.address),
size=f.size,
name=f.name))
outfile.write("\"CCa {addr} {type}\"\n".format(
addr=hex(f.address),
type=f.ftype))
for l in llabels :
if l.name != "unknown" :
for f in functions :
if (l.address > f.address) and (l.address < (f.address + f.size)) :
outfile.write("f. {name} @ {addr}\n".format(
name=l.name,
addr=hex(l.address)))
for c in comments :
if c.text != "" :
outfile.write("\"CCa {addr} {text}\"\n".format(
addr=c.address,
text=c.text))
outfile.seek(0,2)
if outfile.tell() == 0:
print("[-] Found nothing to convert :-(")
exit()
# ----------------------------------------------------------------------
def idc_parse(args):
print("[+] Starting convertion from '%s' to '%s'" %
(args.idc_file, args.out_file))
idc_file = open(args.idc_file, "r")
idc = idc_file.read()
idc_enums_parse(idc)
idc_structs_parse(idc)
if args.is_functions:
idc_functions_parse(idc)
if args.is_comments:
idc_comments_parse(idc)
idc_generate_r2(args.out_file)
print("[+] Convertion done.\n")
print("[!] Execute: r2 -i %s [program]\n" %
(args.out_file))
#
# End of IDC Parsing
###
# ----------------------------------------------------------------------
def main():
''' Gets arguments from the user. Perform convertion of the chosen data from the IDB into a radare2 initialization script
'''
args = get_args()
if args.idb_file:
idb_parse(args)
elif args.idc_file:
idc_parse(args)
if __name__ == "__main__":
main()
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/*
* ida2rdb.idc
* ===========
*
* Exports an ida database in a format to be handled by radare
*
* author: pancake <@youterm.com>
*
* TODO:
* * Add stack frame related information (stack size, and so) as comments
*
*/
#include <idc.idc>
static dumpMeNot(fd, ea) {
auto func, comment, sz, i, ref;
// Loop from start to end in the current segment
//SegStart(ea);
for (func=ea; func != BADADDR && func < SegEnd(ea); func=NextFunction(func)) {
// If the current address is function process it
// if (GetFunctionFlags(func) != -1) {
sz = FindFuncEnd(func) - func;
fprintf(fd, "afr %s 0x%08lx\n", GetFunctionName(func), func);
comment = GetFunctionCmt(func, 0);
if (comment != "")
fprintf(fd, "CC %s@0x%08x\n", comment, func);
fprintf(fd, "CC framesize=%d@0x%08x\n", func, GetFrameSize(func));
// Find all code references to func
for (ref=RfirstB(func); ref != BADADDR; ref=RnextB(func, ref)) {
//fprintf(fd, "; xref from %08lX (%s)\n", ref, GetFunctionName(ref));
fprintf(fd, "Cx 0x%08lx 0x%08lx\n", func, ref);
}
// }
}
func=ea;
while (func != BADADDR && func < SegEnd(ea)) {
comment = CommentEx(func, 0);
if (comment != "")
fprintf(fd, "CC %s@0x%08x\n", comment, func);
comment = GetConstCmt(func, 0);
if (comment != "")
fprintf(fd, "CC %s@0x%08x\n", comment, func);
comment = GetEnumCmt(func, 0);
if (comment != "")
fprintf(fd, "CC %s@0x%08x\n", comment, func);
comment = RptCmt(func);
if (comment != "")
fprintf(fd, "CC %s@0x%08x\n", comment, func);
func = func + ItemSize(func);
}
}
static main() {
auto fd;
auto file;
auto i, func, ref,sz;
auto ord,ea;
auto comment;
auto entry;
file = GetInputFile()+".txt";
fd = fopen(file, "w");
if (!fd) {
Message("Cannot open '"+file+"'\n");
Exit(1);
}
entry="";
// Walk entrypoints
for ( i=0; ; i++ ) {
ord = GetEntryOrdinal(i);
if ( ord == 0 ) break;
ea = GetEntryPoint(ord);
fprintf(fd, "entry=0x%08lx %s\n", ea, Name(ea));
entry = ea;
}
// XXX last entrypoint taken as ok??
dumpMeNot(fd, entry);
// eof
fclose(fd);
Message(file+"file generated.\n");
}
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#!/usr/bin/perl
# author: pancake <youterm.com>
# MakeName (0X804C1AF, "the_forker");
# MakeRptCmt (0X804C1B6, "comentari chachi\n");
open FD, "<".$ARGV[0] or die "Cannot open file\n";
print "fs symbols\n";
while(<FD>) {
$str=$_;
if ($str=~/MakeName[^X]*.([^,]*)[^"]*.([^"]*)/) {
print "f sym.$2 @ 0x$1\n";
}
elsif ($str=~/MakeRptCmt[^X]*.([^,]*)[^"]*.([^"]*)/) {
$cmt = $2;
$off = $1;
$cmt=~s/\\n//g;
print "CC $cmt @ 0x$off\n";
}
}
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R2PM_BINDIR=$(shell r2pm -H R2PM_BINDIR)
all: node_modules
node_modules:
mkdir -p node_modules
npm i
install:
ln -fs "$(shell pwd)"/r2jadx.js "$(R2PM_BINDIR)"/r2jadx
uninstall:
rm -f "$(R2PM_BINDIR)"/r2jadx
test:
r2 -A -i ./r2jadx.js /tmp/classes.dex
indent:
node_modules/.bin/semistandard --fix *.js
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r2jadx
======
Jadx is decompiles Class and Dex files into Java source code.
The r2jadx project aims to integrate this decompiler into r2.
This project is still WIP, I focus on DEX support for now, so
feel free to report issues or submit improvements/fixes to
get more information from the jadx json files into r2!
Features:
* Show plaintext jadx decompilation results from r2
* Cache decompilation results in disk for fast interactions
* Associate address-to-line (and fileline-to-address)
* Experimental integration into `pdc`
* Supports low level and high level decompilations
Low level have some benefits compared to High Level decompilation
* Output comparable to `r2dec`
* Works even on obfuscated code
* Better match with assembly code (looks nice with decompiler graphs)
Author
------
--pancake @ 2019
Requirements
------------
In order to use r2jadx you need some recent versions of both:
* r2 >= 3.6
* jadx >= 1.0.0
* nodejs >= 10
Installation
------------
The easiest way to install r2, jadx and r2jadx is via r2pm:
* r2pm -i jadx r2jadx
Once the tool and script are installed you may want to make
it available via `pdc` inside r2 to get it working in Cutter
or Panels:
```> e cmd.pdc=!*r2jadx```
Some explanations on this line:
* `cmd.pdc` eval var makes the `pdc` command execute a different program
* `!*` prefix is an alias for the `#!pipe`
* `r2jadx` is the r2jadx.js script installed in `PATH`
* `r2` tweaks the `PATH` envvar to make `r2pm` scripts available into r2
* Running `pdc?` will do `!*r2jadx -h`, `pdc*` -> `!*r2jadx -r2` ...
Usage
-----
The first time you run r2jadx it will create a `.d` directory in the same
place where the loaded `classes.dex` live.
This directory contains two subdirectories with the `json` and `java` outputs
of the JADX decompilation results.
Those are the command line arguments accepted by r2jadx:
* -r -> import ALL the low level decompilation results into r2 as comments
* -r2 -> import ALL the high level decompilation results into r2 as comments
To get the function decompilation results:
* -ll -> low level decompilation of the current function
* -hl -> high level decompilation of the current function (default if no arg)
In addition we can have a full dump of the decompilation
* -ahl -> all functions high-level decompiled results
* -all -> all functions low-level decompiled results
* -cat -> `cat` the decompiled java file associated with the current function
--pancake
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#!/usr/bin/env node
const execSync = require('child_process').execSync;
const shellEscape = require('shell-escape');
const path = require('path');
const fs = require('fs');
function toPaddedHexString (num, len) {
const str = parseInt(num).toString(16);
return '0x' + ('0'.repeat(len - str.length) + str);
}
function walkSync (dir, arr) {
if (arguments.length === 1) {
arr = [];
}
if (!fs.lstatSync(dir).isDirectory()) {
return dir;
}
const files = fs.readdirSync(dir).map(f => walkSync(path.join(dir, f), arr));
arr.push(...files);
return arr;
}
const walk = async (dir, filelist = []) => {
const files = fs.readdirSync(dir);
for (var file of files) {
const filepath = path.join(dir, file);
const stat = await fs.stat(filepath);
if (stat.isDirectory()) {
filelist = await walk(filepath, filelist);
} else {
filelist.push(file);
}
}
return filelist;
};
function processMethod (data, mode, offset, method) {
function comment (addr, line) {
if (mode === 'c' || mode === 'cat') {
// console.error(data.name);
// console.log(data.source);
if (!data.source) {
return '';
}
let lastOffset = parseInt(method.offset);
if (mode === 'cat' || (mode === 'c' && addr === lastOffset)) {
const source = data.source.replace('.json', '.java');
const fileData = fs.readFileSync(source);
return fileData.toString('utf8');
}
return '';
}
if (mode === 'f') {
let lastOffset = parseInt(method.offset);
if (addr === lastOffset) {
return toPaddedHexString(addr, 8) + ' ' + line + '\n';
}
return '';
}
const b64line = Buffer.from(line).toString('base64');
if (b64line.length > 2048) {
return 'CCu toolong @ ' + addr + '\n';
}
return 'CCu base64:' + b64line + ' @ ' + addr + '\n';
}
let lastOffset = parseInt(method.offset);
if (mode === 'all' || mode === 'ahl') {
// decompile selected method with offset + text format
let res = '\n' + toPaddedHexString(method.offset, 8) + ' ' + method.name + ':\n';
for (let line of method.lines) {
res += toPaddedHexString(line.offset || lastOffset, 8) + ' ' + line.code + '\n';
if (line.offset) {
lastOffset = line.offset;
}
}
return res;
}
if (mode === 'r') {
offset = 0;
mode = 'r2';
}
if (mode === 'll' || mode === 'hl') {
// decompile given method for r2
let res = '';
if (offset === lastOffset) {
return processMethod(data, 'r2', offset, method);
}
for (let line of method.lines) {
if (parseInt(line.offset) === offset - 16) {
res += processMethod(data, 'r2', offset, method);
}
}
return res;
}
// mode === 'r2'
let res = comment(parseInt(method.offset) + 16, method.name);
for (let line of method.lines) {
// TODO: use CL console.error('CL ' + line.offset + ' base64:' + line.code);
const addr = parseInt(line.offset || lastOffset);
res += comment(addr, line.code.trim());
// 'CCu base64:' + Buffer.from(line.code).toString('base64') + ' @ ' + parseInt(line.offset || lastOffset) + '\n';
if (line.offset) {
lastOffset = line.offset;
}
}
return res;
}
function processClass (data, mode, offset) {
offset = parseInt(offset);
let res = '';
if (data.methods) {
for (let method of data.methods) {
switch (mode) {
case 'a':
case 'c':
case 'f':
case 'cat':
case 'r':
case 'r2':
case 'all':
case 'ahl':
case 'll':
case 'hl':
res += processMethod(data, mode, offset, method);
break;
default:
res += 'Invalid mode ' + mode + '\n';
break;
}
}
}
return res;
}
function dex2path (target) {
return target + '.d';
}
async function crawl (target, mode, arg) {
// console.log('crawling', arguments);
switch (mode) {
case 'f':
return crawlFiles(path.join(target, 'hl'), mode, arg);
case 'c':
return crawlFiles(path.join(target, 'hl'), 'c', arg);
case 'a':
return crawlFiles(path.join(target, 'hl'), 'cat', arg);
case 'r':
return crawlFiles(path.join(target, 'll'), mode, arg);
case 'r2':
return crawlFiles(path.join(target, 'hl'), mode, arg);
case 'll':
return crawlFiles(path.join(target, 'll'), mode, arg);
case 'hl':
return crawlFiles(path.join(target, 'hl'), mode, arg);
case 'ahl':
return crawlFiles(path.join(target, 'hl'), mode, arg);
case 'all':
return crawlFiles(path.join(target, 'll'), mode, arg);
case 'cat':
return crawlFiles(path.join(target, 'cat'), mode, arg);
case '?':
case 'h':
case 'help':
default:
return 'Usage: !*r2jadx ([filename])[ll,hl,all,ahl,cat,help]';
}
}
async function crawlFiles (target, mode, arg) {
const ext = 'json'; // (mode === 'cat' || mode === 'c') ? 'java' : 'json';
// console.error('FINDUS', target);
const files = walkSync(target).filter(_ => (_.endsWith && _.endsWith(ext)));
let res = '';
for (let fileName of files) {
try {
if (mode === 'cat') {
const fileData = fs.readFileSync(fileName.replace('.json', '.java'));
res += fileData;
} else {
const fileData = fs.readFileSync(fileName);
const data = JSON.parse(fileData);
res += processClass(data, mode, arg);
if (data['inner-classes']) {
for (let klass of data['inner-classes']) {
klass.source = fileName;
res += processClass(klass, mode, arg);
}
}
}
} catch (e) {
console.error('' + fileName + ': ' + e);
}
}
return res;
}
async function decompile (target, mode, arg) {
const outdir = dex2path(target);
if (!fs.existsSync(outdir)) {
if (!check()) {
console.error('Invalid version of jadx. We need >= 1.x');
process.exit(1);
}
const options = { }; // stderr: 'inherit' };
try {
console.error('jadx: Performing the low level decompilation...');
const cmd = [ 'r2pm', '-r', 'jadx', '--output-format', 'json', '-f', '-d', path.join(outdir, 'll'), target ];
execSync(shellEscape(cmd, options));
} catch (e) {
}
try {
console.error('jadx: Performing the high level decompilation...');
const cmd = [ 'r2pm', '-r', 'jadx', '--show-bad-code', '--output-format', 'java', '-d', path.join(outdir, 'hl'), target ];
execSync(shellEscape(cmd, options));
} catch (e) {
}
try {
console.error('jadx: Constructing the high level jsons...');
const cmd = [ 'r2pm', '-r', 'jadx', '--show-bad-code', '--output-format', 'json', '-d', path.join(outdir, 'hl'), target ];
execSync(shellEscape(cmd, options));
} catch (e) {
}
}
return crawl(outdir, mode, arg);
}
function check () {
const cmd = [ 'r2pm', '-r', 'jadx', '--version' ];
const res = execSync(shellEscape(cmd, {})).toString('utf8');
return res.startsWith('1');
}
module.exports = {
crawl: crawl,
dex2path: dex2path,
decompile: decompile,
check: check
};
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{
"name": "r2jadx",
"version": "1.0.0",
"description": "",
"main": "r2jadx.js",
"dependencies": {
"glob": "^7.1.4",
"r2pipe": "^2.7.2",
"r2pipe-promise": "^1.5.1",
"shell-escape": "*"
},
"devDependencies": {
"semistandard": "*"
},
"author": "pancake <[email protected]>",
"license": "MIT"
}
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#!/usr/bin/env node
const jadx = require('./jadx');
const r2pipe = require('r2pipe');
async function main (argv) {
const r2arg = (argv.length > 2 && argv[2][0] !== '-') ? argv[2] : undefined;
let r2 = r2pipe.openSync(r2arg);
try {
r2.cmd('af');
const info = r2.cmdj('ij');
const fileName = info.core.file;
const fcn = r2.cmdj('afij');
if (!fileName.endsWith('.dex')) {
throw new Error('Sorry, this is not a DEX file');
}
const fcnOffset = (fcn && fcn.length > 0) ? fcn[0].offset : 0;
let mode = 'all';
if (argv.length > 2) {
argv = argv.slice(1);
}
if (argv[1] && argv[1][0] === '-') {
mode = argv[1].substring(1);
}
if (fileName) {
try {
const res = await jadx.decompile(fileName, mode, fcnOffset);
if (mode.startsWith('r')) {
for (let line of res.split('\n')) {
if (line.trim().length > 0) {
r2.cmd(line);
}
}
} else {
console.log(res);
}
return res;
} catch (e) {
throw e;
}
} else {
throw new Error('Cannot find function');
}
} catch (e) {
console.error('Oops', e, e.output ? e.output.toString() : '');
throw e;
} finally {
r2.quit();
}
}
if (process.argv.length < 3) {
if (!r2pipe.isAvailable()) {
console.error('Usage: r2jadx [file] # or run it from inside r2');
process.exit(1);
}
}
switch (process.argv[2]) {
case '-h':
console.error('Usage: !*r2jadx [-mode]');
console.error('Setup: e cmd.pdc=!*r2jadx');
console.error('Modes: -r2 = r2 output');
console.error(' -a = show decompilation of all the classes');
console.error(' -c = decompile current class');
console.error(' -f = decompile current function');
console.error(' -r = load all decompilation output as comments (ll)');
console.error(' -r2 = load all decompilation output as comments (hl)');
console.error(' -ahl = all high level decompilation');
console.error(' -all = all low level decompilation');
console.error(' -hl = high level decompilation');
console.error(' -ll = low level decompilation');
process.exit(0);
}
main(process.argv)
.then((res) => {
console.log(res);
process.exit(0);
})
.catch((err) => {
console.error(err);
process.exit(0);
});
+2 -2
View File
@@ -1,9 +1,9 @@
# r2k
kernel module for radare2
This module is going to be part of radare2 (https://github.com/radare/radare2).
This module is going to be part of radare2 (https://github.com/radareorg/radare2).
It will work together with an userland program (https://github.com/radare/radare2/blob/master/libr/io/p/io_r2k.c)
It will work together with an userland program (https://github.com/radareorg/radare2/blob/master/libr/io/p/io_r2k.c)
This module allows to:
+22 -4
View File
@@ -1,18 +1,36 @@
#!/bin/sh
TARGET="$1"
if [ -z "$1" ]; then
case "$TARGET" in
-h)
echo "Usage. r2snow -a,-f,-r"
;;
-a)
ARG=$TARGET
TARGET=""
;;
-f)
ARG=$TARGET
TARGET=""
;;
-r)
ARG=$TARGET
TARGET=""
;;
esac
if [ -z "$TARGET" ]; then
TARGET="${R2_FILE}"
fi
if [ -z "$TARGET" ]; then
echo "Usage: r2 -i '.!r2snow'" > /dev/stderr
exit 1
fi
if [ -f "$1" ]; then
echo "Cannot find $1" > /dev/stderr
if [ ! -f "$TARGET" ]; then
echo "Cannot find $TARGET" > /dev/stderr
exit 1
fi
nocode --print-cxx=r2snow-source.c --print-ranges=r2snow-addrof.txt "$TARGET"
r2snow.pl
r2snow.pl $ARG
exit 0
+77 -8
View File
@@ -2,6 +2,9 @@
# generate r2 script out of a snowman decompilation
# author : pancake // nopcode.org // 2016
use MIME::Base64;
sub rf {
my ($file) = shift;
open FH, $file or die "cannot open $file";
@@ -18,17 +21,21 @@ sub wf {
}
use constant {
R2SNOW_SOURCE => "r2snow-source.c"
R2SNOW_SOURCE => "r2snow-source.c",
R2SNOW_ADDROF => "r2snow-addrof.txt"
};
my $source = join("", rf(R2SNOW_SOURCE));
my @addrof = rf("r2snow-addrof.txt");
my @addrof = rf(R2SNOW_ADDROF);
my $ts = $source;
$ts =~s/reinterpret_cast//g;
$ts =~s/static_cast//g;
wf(R2SNOW_SOURCE . ".txt", $ts);
local @nts = split /\n/g,$ts;
local @nls = ();
sub initNewlines() {
my $offset = 0;
@@ -40,6 +47,42 @@ sub initNewlines() {
}
}
sub functionAt($) {
my ($ln) = @_;
my $line = 1;
my $findeof = 0;
my $text = "";
foreach my $nt (@nts) {
if ($nt=~/^ /) {
$text .= $nt . "\n";
} else {
if ($findeof) {
return $text . $nt . "\n";
} else {
$text = $nt . "\n";
}
}
if ($line >= $ln) {
$findeof = 1;
}
$line++;
}
return "";
}
sub addrFor($) {
my ($offset) = @_;
my $line = 0;
foreach my $a (@addrof) {
my ($addr, $off) = split(" ", $a);
if ($addr >= $offset) {
return $line;
}
$line++;
}
return 0;
}
sub lineFor($) {
my ($offset) = @_;
my $line = 0;
@@ -53,10 +96,36 @@ sub lineFor($) {
}
initNewlines();
foreach my $a (@addrof) {
my ($addr, $offset) = split(" ", $a);
my $file = R2SNOW_SOURCE . ".txt";
my $line = lineFor($offset);
print "CL $file:$line $addr\n";
my $arg = $ARGV[0];
if ($arg eq '-h') {
print('Usage: !r2snow [-a,-f,-r]');
print(' -a : show all the program decompiled');
print(' -f : decompile current function');
print(' -r : import decompiler output as comments');
} elsif ($arg eq '-a') {
print($ts);
} elsif ($arg eq '-f') {
my $off = $ENV{"R2_OFFSET"};
print(functionAt(addrFor(scalar $off)));
} else {
local $oaddr = '';
local $oline = 0;
foreach my $a (@addrof) {
my ($addr, $offset) = split(" ", $a);
my $file = R2SNOW_SOURCE . ".txt";
my $line = lineFor($offset);
my $text = @nts[$line - 1];
my $txt64 = encode_base64($text);
$txt64 =~ s/\n//g;
unless ($oaddr eq $addr or $oline == $line) {
print "CCu base64:$txt64 @ $addr\n";
##print "CC $line @ $addr\n"; #u base64:$txt64 @ $addr\n";
}
$oaddr = $addr;
$oline = $line;
#print "CL $file:$line $addr\n";
}
}
unlink(R2SNOW_SOURCE);
unlink(R2SNOW_SOURCE.".txt");
+2 -2
View File
@@ -63,7 +63,7 @@ Q&A
Where can I find some sample programs to take as a template?
---
https://github.com/radare/radare2-extras/tree/master/r2wars/t
https://github.com/radareorg/radare2-extras/tree/master/r2wars/t
How to make awesome warrior that wins r2wars if I'm a n00b?
---
@@ -79,7 +79,7 @@ ARM and MIPS have memory alignment restrictions, so you dont want to run code or
This is pending to be implemented, but will be done before r2con. See those bugs for more details
https://github.com/radare/radare2/labels/r2wars
https://github.com/radareorg/radare2/labels/r2wars
How is this code executed?
---
+1 -1
View File
@@ -9,7 +9,7 @@
},
"license": "LGPL-3.0",
"bugs": {
"url": "https://github.com/radare/radare2-extras/issues"
"url": "https://github.com/radareorg/radare2-extras/issues"
},
"homepage": "http://www.radare.org",
"dependencies": {
+3 -2
View File
@@ -1,5 +1,5 @@
#!/bin/sh
# This script was automatically generated by ACR v1.7.0
# This script was automatically generated by ACR v1.7.2
# @author: pancake <nopcode.org>
# @url: http://www.nopcode.org
# @repo: git clone https://github.com/radare/acr
@@ -62,6 +62,7 @@ if [ -e "${VPATH}/config.guess" ]; then
fi
CPU="`uname -m|sed -e 's, ,,g'|cut -d - -f 1`"
OS="`uname -s|tr A-Z a-z`"
uname -r | grep -qE "(Microsoft|WSL)" 2>/dev/null && OS="wsl"
GNU="`uname --help 2>&1 | grep gnu`"
[ "${GNU}" ] && OS="${OS}-gnu"
[ "${CPU}" = ppc ] && CPU="powerpc"
@@ -170,7 +171,7 @@ take_environ() {
}
show_version() {
echo "radare2-extras-ssdeep-1.0 configuration script done with acr v1.7.0.
echo "radare2-extras-ssdeep-1.0 configuration script done with acr v1.7.2.
The 'Free Software Foundation' message is only for autodetection.
Originally written by pancake <nopcode.org>."
exit 0
Binary file not shown.
-2
View File
@@ -1,2 +0,0 @@
http://blog.didierstevens.com/programs/yara-rules/
https://code.google.com/p/malwarecookbook/source/browse/trunk/3/6/magic.yara?r=5
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
+8 -10
View File
@@ -38,17 +38,15 @@ mrproper: clean
rm -f Makefile
install:
${INSTALL_LIB} ${MOD}.${LIBEXT} $(R2PM_PLUGDIR)/${MOD}.${LIBEXT}
rm -rf $(R2PM_PLUGDIR)/yara
mkdir -p $(R2PM_PLUGDIR)/yara
cp -rf ../rules-yara3/ $(R2PM_PLUGDIR)/
${INSTALL_LIB} ${MOD}.${LIBEXT} $(R2PM_USRPLUGIN_DIR)/${MOD}.${LIBEXT}
cp -rf ../rules-yara3/ $(R2PM_USRPLUGIN_DIR)/
symstall:
ln -fs ${PWD}/${MOD}.${LIBEXT} $(R2PM_PLUGDIR)/$(MOD).$(LIBEXT)
rm -rf $(R2PM_PLUGDIR)/yara
ln -fs $(PWD)/../rules-yara3 $(R2PM_PLUGDIR)/rules-yara3
ln -fs ${PWD}/${MOD}.${LIBEXT} $(R2PM_USRPLUGIN_DIR)/$(MOD).$(LIBEXT)
rm -rf $(R2PM_USRPLUGIN_DIR)/yara
ln -fs $(PWD)/../rules-yara3 $(R2PM_USRPLUGIN_DIR)/rules-yara3
uninstall:
rm -f ${R2PM_PLUGDIR}/$(MOD).$(LIBEXT)
rm -rf ${R2PM_PLUGDIR}/rules-yara3
rm -rf ${R2PM_PLUGDIR}/yara
rm -f ${R2PM_USRPLUGIN_DIR}/$(MOD).$(LIBEXT)
rm -rf ${R2PM_USRPLUGIN_DIR}/rules-yara3
rm -rf ${R2PM_USRPLUGIN_DIR}/yara
+3 -2
View File
@@ -1,5 +1,5 @@
#!/bin/sh
# This script was automatically generated by ACR v1.7.0
# This script was automatically generated by ACR v1.7.2
# @author: pancake <nopcode.org>
# @url: http://www.nopcode.org
# @repo: git clone https://github.com/radare/acr
@@ -62,6 +62,7 @@ if [ -e "${VPATH}/config.guess" ]; then
fi
CPU="`uname -m|sed -e 's, ,,g'|cut -d - -f 1`"
OS="`uname -s|tr A-Z a-z`"
uname -r | grep -qE "(Microsoft|WSL)" 2>/dev/null && OS="wsl"
GNU="`uname --help 2>&1 | grep gnu`"
[ "${GNU}" ] && OS="${OS}-gnu"
[ "${CPU}" = ppc ] && CPU="powerpc"
@@ -172,7 +173,7 @@ take_environ() {
}
show_version() {
echo "radare2-extras-yara-1.0 configuration script done with acr v1.7.0.
echo "radare2-extras-yara-1.0 configuration script done with acr v1.7.2.
The 'Free Software Foundation' message is only for autodetection.
Originally written by pancake <nopcode.org>."
exit 0
+5 -19
View File
@@ -10,8 +10,6 @@
#undef R_IPI
#define R_IPI static
static int loaded_version = 3;
// true if the plugin has been initialized.
static int initialized = false;
@@ -65,7 +63,7 @@ static int r_cmd_yara_scan(const RCore* core) {
return false;
}
result = r_io_read_at (core->io, 0L, to_scan, to_scan_size);
result = r_io_pread_at (core->io, 0L, to_scan, to_scan_size);
if (!result) {
eprintf ("Something went wrong during r_io_read_at\n");
free (to_scan);
@@ -260,19 +258,6 @@ static int r_cmd_yara_add_file(const char* rules_path) {
goto err_exit;
}
#if 0
if (loaded_version == 2) {
if (yr_compiler_push_file_name (compiler, rules_path) != ERROR_SUCCESS) {
char buf[64];
eprintf ("Error: %s : %s\n",
yr_compiler_get_error_message (compiler, buf, sizeof (buf)),
rules_path);
goto err_exit;
}
}
#endif
result = yr_compiler_add_file (compiler, rules_file, NULL, rules_path);
fclose (rules_file);
rules_file = NULL;
@@ -363,13 +348,13 @@ static int r_cmd_yara_call(void *user, const char *input) {
}
static int r_cmd_yara_load_default_rules (const RCore* core) {
#define YARA_PATH R2_PREFIX "/lib/radare2-extras/" R2_VERSION "/rules-yara3/"
RListIter* iter = NULL;
YR_COMPILER* compiler = NULL;
YR_RULES* yr_rules;
char* filename, *complete_path;
char* rules = NULL;
RList* list = r_sys_dir (YARA_PATH);
char* y3_rule_dir = r_str_newf ("%s%s%s", r_str_home(R2_HOME_PLUGINS), R_SYS_DIR, "rules-yara3");
RList* list = r_sys_dir (y3_rule_dir);
if (yr_compiler_create (&compiler) != ERROR_SUCCESS) {
char buf[64];
@@ -383,7 +368,7 @@ static int r_cmd_yara_load_default_rules (const RCore* core) {
r_list_foreach (list, iter, filename) {
if (filename[0] != '.') { // skip '.', '..' and hidden files
complete_path = r_str_append (strdup (YARA_PATH), filename);
complete_path = r_str_newf ("%s%s%s", y3_rule_dir, R_SYS_DIR, filename);
rules = (char*)r_file_gzslurp (complete_path, NULL, true);
free (complete_path);
@@ -415,6 +400,7 @@ static int r_cmd_yara_load_default_rules (const RCore* core) {
return true;
err_exit:
if (y3_rule_dir) free (y3_rule_dir);
if (compiler) yr_compiler_destroy (compiler);
if (list) r_list_free (list);
if (rules) free (rules);