lioncash
25428cb28c
OpcodeDispatcher: Handle VSQRTPD
2022-12-07 22:42:16 +00:00
lioncash
2125949d6d
OpcodeDispatcher: Handle VSQRTPS
2022-12-07 22:42:16 +00:00
Ryan Houdek
7ac21e794d
Merge pull request #2212 from lioncash/comiss
...
OpcodeDispatcher: Handle VCOMISD/VCOMISS/VUCOMISD/VUCOMISS
2022-12-07 14:38:49 -08:00
lioncash
4aa0f3d0a4
OpcodeDispatcher: Handle VCOMISD
2022-12-07 22:06:25 +00:00
lioncash
740c983f65
OpcodeDispatcher: Handle VCOMISS
2022-12-07 22:06:25 +00:00
lioncash
83bccc0032
OpcodeDispatcher: Handle VUCOMISD
2022-12-07 22:06:22 +00:00
lioncash
d1ab636df1
OpcodeDispatcher: Handle VUCOMISS
2022-12-07 21:22:19 +00:00
lioncash
26b629833e
OpcodeDispatcher: Handle VPAVGW
2022-12-07 21:07:43 +00:00
lioncash
95964f8dd8
OpcodeDispatcher: Handle VPAVGB
2022-12-07 21:07:40 +00:00
Ryan Houdek
94ae2e3a9c
Merge pull request #2209 from lioncash/ins
...
IR: Handle 128-bit VInsElement with SVE
2022-12-07 11:08:47 -08:00
lioncash
eae33b0c50
IR: Handle 128-bit VInsElement with SVE
...
Currently VDupElement allows duplicating 128-bit elements in 256-bit
vectors with SVE, so we can extend VInsElement to have similar behavior.
2022-12-07 18:41:45 +00:00
Ryan Houdek
e9aa368a62
Merge pull request #2208 from lioncash/zero
...
OpcodeDispatcher: Explicitly zero upper lanes
2022-12-07 10:13:53 -08:00
lioncash
5a37786da7
OpcodeDispatcher: Explicitly zero upper lanes
...
Makes our intent to zero-extend the upper lanes explicit and lets us
remove a special case in the LoadSource implementation.
This also makes things a little nicer since we're not hardcoding 32 byte
stores.
2022-12-07 17:22:20 +00:00
lioncash
4cf3805950
OpcodeDispatcher: Handle VADDSD
2022-12-07 16:43:47 +00:00
lioncash
1f5a1826a6
OpcodeDispatcher: Handle VADDSS
2022-12-07 16:43:44 +00:00
lioncash
6a63ae2d9c
OpcodeDispatcher: Merge PHADD into VectorALUOp
2022-12-07 15:18:19 +00:00
lioncash
a7a1e2abd3
OpcodeDispatcher: Merge HADDP into VectorALUOp
2022-12-07 15:14:10 +00:00
lioncash
047ae13c98
OpcodeDispatcher: Merge PAVGOp with VectorALUOp
...
This can be merged into it, considering it only has one IR op.
2022-12-07 14:51:08 +00:00
lioncash
3d5e0c5832
OpcodeDispatcher: Merge PSUBSOp with VectorALUOp
2022-12-06 01:31:26 +00:00
lioncash
71a36763df
OpcodeDispatcher: Merge PADDSOp with VectorALUOp
2022-12-06 01:27:31 +00:00
lioncash
07bd3137ef
OpcodeDispatcher: Merge PSUBQOp with VectorALUOp
2022-12-06 01:21:33 +00:00
lioncash
c2b40b4dd3
OpcodeDispather: Merge PADDQOp with VectorALUOp
2022-12-06 01:13:12 +00:00
lioncash
db74e46fc3
OpcodeDispatcher: Merge ANDNOp with VectorALUROp
...
Now that ANDNOp is reduced to one IR op, we can merge it with
VectorALUROp
2022-12-05 22:28:39 +00:00
lioncash
13bba59ba6
OpcodeDispatcher: Simplify ANDNOp and VANDNOp
...
We can just use VBic here to simplify everything.
2022-12-05 22:15:15 +00:00
lioncash
6b259e2731
OpcodeDispatcher: Handle VPADDQ
2022-12-05 17:53:33 +00:00
lioncash
200660aba5
OpcodeDispatcher: Handle VPADDD
2022-12-05 17:44:12 +00:00
lioncash
065c12cfbb
OpcodeDispatcher: Handle VPADDW
2022-12-05 17:33:52 +00:00
lioncash
318972620f
OpcodeDispatcher: Handle VPADDB
2022-12-05 17:23:39 +00:00
lioncash
e7f54d1592
OpcodeDispatcher: Handle VADDPD
2022-12-05 16:59:04 +00:00
lioncash
a8571282b2
OpcodeDispatcher: Handle VADDPS
2022-12-05 16:43:26 +00:00
Ryan Houdek
69f39a0bc3
Arm64: Const on unmodified argument
...
Just noticed this when tinkering around the JIT.
These arguments can safely be const.
2022-12-05 03:54:17 -08:00
Ryan Houdek
5e46d63c42
Arm64: Minor optimization in AESKEYGENASSIST
...
The less number of FPR<->GPR movement instructions the better.
This removes one instance of `ins` and replaces the other with a 64-bit
`dup` instead.
The LoadConstant still turns in to a single `movz` instruction with the
shift.
2022-12-03 03:59:27 -08:00
xianwei zheng
863a59a8e2
Thunk: Crash on XSetErrorHandler(NULL) ( #2190 )
...
* BUGFIX:Adding the nullptr check to FinalizeHostTrampolineForGuestFunction. It will lead crash on interpreter code set function nullptr callback. eg. XSetErrorHandler(NULL)
* fix #2189
2022-11-30 21:57:09 -08:00
lioncash
02a2292115
OpcodeDispatcher: Handle VPANDN
2022-11-30 15:51:10 +00:00
lioncash
a483bc9837
OpcodeDispatcher: Handle VANDNPD
2022-11-30 15:51:10 +00:00
lioncash
120a6b85f4
OpcodeDispatcher: Handle VANDNPS
2022-11-30 15:51:05 +00:00
lioncash
0f8fcfc43e
OpcodeDispatcher: Handle VPAND
2022-11-29 19:08:58 +00:00
lioncash
698b7fda06
OpcodeDispatcher: Handle VANDPD
2022-11-29 19:06:25 +00:00
lioncash
23caa6e20f
OpcodeDispatcher: Handle VANDPS
2022-11-29 19:04:29 +00:00
lioncash
16ed20cfae
OpcodeDispatcher: Handle VPOR
2022-11-29 18:43:38 +00:00
lioncash
ef368ceafa
OpcodeDispatcher: Handle VORPD
2022-11-29 18:40:04 +00:00
lioncash
45480ef32c
OpcodeDispatcher: Handle VORPS
2022-11-29 18:38:13 +00:00
lioncash
c065770f48
OpcodeDispatcher: Handle VPXOR
2022-11-29 18:12:04 +00:00
lioncash
27957ea051
OpcodeDispatcher: Handle VXORPD
2022-11-29 18:05:28 +00:00
lioncash
94e9d1ab3b
OpcodeDispatcher: Handle VXORPS
2022-11-29 18:04:29 +00:00
lioncash
3e80416eb6
OpcodeDispatcher: Handle VZEROUPPER/VZEROALL
2022-11-29 16:15:32 +00:00
lioncash
69d26cfee6
OpcodeDispatcher: Handle combined VMOVQ/VMOVD
2022-11-29 01:49:58 +00:00
lioncash
e3be1540f1
OpcodeDispatcher: Handle VMOVQ
...
Fairly trivial, we can reuse the existing implementation for MOVQ.
2022-11-29 01:49:15 +00:00
Ryan Houdek
57c5761920
Merge pull request #2179 from Sonicadvance1/tsl_maps
...
Core: Replace a couple maps with tsl robin_map
2022-11-28 17:48:27 -08:00
lioncash
45115384b5
OpcodeDispatcher: Handle VMOVNTPD
2022-11-28 16:58:37 +00:00
