2016-10-19 14:28:05 +00:00
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/* Tang Yuhang <tyh000011112222@gmail.com> 2016 */
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2017-07-04 07:55:46 +00:00
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/* pancake <pancake@nopcode.org> 2017 */
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2016-10-10 07:16:56 +00:00
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#include <string.h>
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#include <ctype.h>
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#include <errno.h>
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2017-07-04 07:55:46 +00:00
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#include "getopt.h"
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2016-10-10 07:16:56 +00:00
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2016-10-10 16:04:46 +00:00
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#include <capstone/capstone.h>
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2023-05-09 12:46:10 +00:00
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#include "cstool.h"
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2016-10-10 07:16:56 +00:00
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2019-02-03 06:46:54 +00:00
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void print_string_hex(const char *comment, unsigned char *str, size_t len);
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2017-07-04 07:55:46 +00:00
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static struct {
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const char *name;
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cs_arch arch;
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cs_mode mode;
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2017-07-04 08:04:53 +00:00
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} all_archs[] = {
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2017-07-04 07:55:46 +00:00
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{ "arm", CS_ARCH_ARM, CS_MODE_ARM },
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{ "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
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{ "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
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{ "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
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{ "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
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2019-02-27 07:51:34 +00:00
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{ "armv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 },
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{ "thumbv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 },
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2019-03-15 12:16:45 +00:00
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{ "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
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{ "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
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2018-03-20 00:52:33 +00:00
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{ "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
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2023-07-19 09:56:27 +00:00
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{ "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
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2017-07-04 07:55:46 +00:00
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{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
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{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
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{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
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2023-11-15 04:12:14 +00:00
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{ "aarch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN },
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{ "aarch64be", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN },
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2017-07-04 07:55:46 +00:00
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{ "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN },
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2019-02-27 07:51:34 +00:00
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{ "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO },
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{ "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN },
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{ "mipsbe32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN},
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{ "mipsbe32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MICRO },
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{ "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 },
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{ "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO },
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2017-07-04 07:55:46 +00:00
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{ "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN },
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{ "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN },
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{ "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN },
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{ "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16
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{ "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT
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{ "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32
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{ "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT
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{ "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64
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{ "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT
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2019-05-08 10:17:00 +00:00
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{ "ppc32", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN },
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{ "ppc32be", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN },
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{ "ppc32qpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
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{ "ppc32beqpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
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2022-07-23 14:33:08 +00:00
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{ "ppc32ps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN },
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{ "ppc32beps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN },
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2017-07-04 07:55:46 +00:00
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{ "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
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{ "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
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2019-04-30 05:50:42 +00:00
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{ "ppc64qpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
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{ "ppc64beqpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
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2017-07-04 07:55:46 +00:00
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{ "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
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2019-02-27 07:51:34 +00:00
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{ "sparcv9", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 },
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2017-07-04 07:55:46 +00:00
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{ "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN },
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{ "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN },
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{ "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 },
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{ "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN },
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
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{ "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 },
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{ "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 },
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{ "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 },
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{ "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 },
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{ "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 },
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{ "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 },
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{ "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 },
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{ "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 },
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{ "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 },
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{ "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 },
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2018-03-31 09:29:22 +00:00
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{ "evm", CS_ARCH_EVM, 0 },
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2019-02-01 15:03:47 +00:00
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{ "wasm", CS_ARCH_WASM, 0 },
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2019-02-18 09:39:51 +00:00
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{ "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC },
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{ "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC },
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{ "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED },
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{ "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED },
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2022-12-03 01:57:40 +00:00
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{ "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC },
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{ "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC },
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2019-06-03 15:20:51 +00:00
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{ "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 },
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{ "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 },
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{ "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 },
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{ "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX },
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2022-09-12 12:26:04 +00:00
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{ "sh", CS_ARCH_SH, CS_MODE_BIG_ENDIAN },
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{ "sh2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN},
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{ "sh2e", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
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{ "sh-dsp", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN},
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{ "sh2a", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN},
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{ "sh2a-fpu", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
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{ "sh3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 },
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{ "sh3be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 },
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{ "sh3e", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
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{ "sh3ebe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
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{ "sh3-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
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{ "sh3-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
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{ "sh4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
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{ "sh4be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
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{ "sh4a", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
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{ "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
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{ "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
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2023-03-27 19:37:40 +00:00
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{ "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
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2023-04-10 17:18:41 +00:00
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{ "tc110", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 },
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{ "tc120", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 },
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{ "tc130", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 },
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{ "tc131", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 },
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{ "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
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{ "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
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{ "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
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2024-01-02 04:02:38 +00:00
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{ "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN },
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{ "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN },
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2017-07-04 07:55:46 +00:00
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{ NULL }
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};
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static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins);
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2016-10-14 09:29:56 +00:00
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2018-07-23 17:41:59 +00:00
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void print_string_hex(const char *comment, unsigned char *str, size_t len)
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2016-10-21 08:42:47 +00:00
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{
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unsigned char *c;
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printf("%s", comment);
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for (c = str; c < str + len; c++) {
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printf("0x%02x ", *c & 0xff);
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}
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printf("\n");
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}
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2016-10-10 07:16:56 +00:00
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// convert hexchar to hexnum
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static uint8_t char_to_hexnum(char c)
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{
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2016-10-10 15:20:29 +00:00
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if (c >= '0' && c <= '9') {
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2016-10-21 08:03:35 +00:00
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return (uint8_t)(c - '0');
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2016-10-10 15:20:29 +00:00
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}
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if (c >= 'a' && c <= 'f') {
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return (uint8_t)(10 + c - 'a');
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}
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// c >= 'A' && c <= 'F'
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return (uint8_t)(10 + c - 'A');
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2016-10-10 07:16:56 +00:00
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}
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2016-10-10 15:20:29 +00:00
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// convert user input (char[]) to uint8_t[], each element of which is
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// valid hexadecimal, and return actual length of uint8_t[] in @size.
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2016-10-10 07:16:56 +00:00
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static uint8_t *preprocess(char *code, size_t *size)
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{
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2016-10-21 08:03:35 +00:00
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size_t i = 0, j = 0;
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2016-10-10 15:20:29 +00:00
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uint8_t high, low;
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uint8_t *result;
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2017-07-26 15:22:46 +00:00
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if (strlen(code) == 0)
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return NULL;
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2016-10-10 15:20:29 +00:00
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result = (uint8_t *)malloc(strlen(code));
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if (result != NULL) {
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while (code[i] != '\0') {
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if (isxdigit(code[i]) && isxdigit(code[i+1])) {
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high = 16 * char_to_hexnum(code[i]);
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low = char_to_hexnum(code[i+1]);
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result[j] = high + low;
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i++;
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j++;
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}
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|
|
i++;
|
|
|
|
}
|
|
|
|
*size = j;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
2016-10-10 07:16:56 +00:00
|
|
|
}
|
|
|
|
|
2016-10-10 15:20:29 +00:00
|
|
|
static void usage(char *prog)
|
2016-10-10 07:16:56 +00:00
|
|
|
{
|
2019-02-01 15:03:47 +00:00
|
|
|
printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
|
2023-09-05 04:24:59 +00:00
|
|
|
printf("Syntax: %s [-d|-a|-r|-s|-u|-v] <arch+mode> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
|
2016-10-10 15:20:29 +00:00
|
|
|
printf("\nThe following <arch+mode> options are supported:\n");
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_X86)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" x16 16-bit mode (X86)\n");
|
|
|
|
printf(" x32 32-bit mode (X86)\n");
|
|
|
|
printf(" x64 64-bit mode (X86)\n");
|
|
|
|
printf(" x16att 16-bit mode (X86), syntax AT&T\n");
|
|
|
|
printf(" x32att 32-bit mode (X86), syntax AT&T\n");
|
|
|
|
printf(" x64att 64-bit mode (X86), syntax AT&T\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_ARM)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" arm arm\n");
|
|
|
|
printf(" armbe arm + big endian\n");
|
|
|
|
printf(" thumb thumb mode\n");
|
|
|
|
printf(" thumbbe thumb + big endian\n");
|
|
|
|
printf(" cortexm thumb + cortex-m extensions\n");
|
2023-07-19 09:56:27 +00:00
|
|
|
printf(" cortexv8m thumb + cortex-m extensions + v8\n");
|
2019-03-15 05:01:04 +00:00
|
|
|
printf(" armv8 arm v8\n");
|
|
|
|
printf(" thumbv8 thumb v8\n");
|
2019-03-15 12:16:45 +00:00
|
|
|
printf(" armv8be arm v8 + big endian\n");
|
|
|
|
printf(" thumbv8be thumb v8 + big endian\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
2023-11-15 04:12:14 +00:00
|
|
|
if (cs_support(CS_ARCH_AARCH64)) {
|
|
|
|
printf(" aarch64 aarch64 mode\n");
|
|
|
|
printf(" aarch64be aarch64 + big endian\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
2023-12-28 02:10:38 +00:00
|
|
|
if (cs_support(CS_ARCH_ALPHA)) {
|
2024-01-02 04:02:38 +00:00
|
|
|
printf(" alpha alpha + little endian\n");
|
|
|
|
printf(" alphabe alpha + big endian\n");
|
2023-12-28 02:10:38 +00:00
|
|
|
}
|
|
|
|
|
2016-10-10 15:20:29 +00:00
|
|
|
if (cs_support(CS_ARCH_MIPS)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" mips mips32 + little endian\n");
|
|
|
|
printf(" mipsbe mips32 + big endian\n");
|
|
|
|
printf(" mips64 mips64 + little endian\n");
|
|
|
|
printf(" mips64be mips64 + big endian\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_PPC)) {
|
2019-05-08 10:17:00 +00:00
|
|
|
printf(" ppc32 ppc32 + little endian\n");
|
|
|
|
printf(" ppc32be ppc32 + big endian\n");
|
|
|
|
printf(" ppc32qpx ppc32 + qpx + little endian\n");
|
|
|
|
printf(" ppc32beqpx ppc32 + qpx + big endian\n");
|
2022-07-23 14:33:08 +00:00
|
|
|
printf(" ppc32ps ppc32 + ps + little endian\n");
|
|
|
|
printf(" ppc32beps ppc32 + ps + big endian\n");
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" ppc64 ppc64 + little endian\n");
|
|
|
|
printf(" ppc64be ppc64 + big endian\n");
|
2019-04-30 05:50:42 +00:00
|
|
|
printf(" ppc64qpx ppc64 + qpx + little endian\n");
|
|
|
|
printf(" ppc64beqpx ppc64 + qpx + big endian\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_SPARC)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" sparc sparc\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_SYSZ)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" systemz systemz (s390x)\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_XCORE)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" xcore xcore\n");
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
2018-03-31 09:29:22 +00:00
|
|
|
|
2016-10-27 04:12:59 +00:00
|
|
|
if (cs_support(CS_ARCH_M68K)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" m68k m68k + big endian\n");
|
|
|
|
printf(" m68k40 m68k_040\n");
|
2016-10-27 04:12:59 +00:00
|
|
|
}
|
2016-10-10 15:20:29 +00:00
|
|
|
|
2017-04-17 08:58:29 +00:00
|
|
|
if (cs_support(CS_ARCH_TMS320C64X)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" tms320c64x TMS320C64x\n");
|
2017-04-17 08:58:29 +00:00
|
|
|
}
|
|
|
|
|
2018-03-31 09:29:22 +00:00
|
|
|
if (cs_support(CS_ARCH_M680X)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" m6800 M6800/2\n");
|
|
|
|
printf(" m6801 M6801/3\n");
|
|
|
|
printf(" m6805 M6805\n");
|
|
|
|
printf(" m6808 M68HC08\n");
|
|
|
|
printf(" m6809 M6809\n");
|
|
|
|
printf(" m6811 M68HC11\n");
|
|
|
|
printf(" cpu12 M68HC12/HCS12\n");
|
|
|
|
printf(" hd6301 HD6301/3\n");
|
|
|
|
printf(" hd6309 HD6309\n");
|
|
|
|
printf(" hcs08 HCS08\n");
|
2018-03-31 09:29:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_EVM)) {
|
2019-01-23 06:39:01 +00:00
|
|
|
printf(" evm Ethereum Virtual Machine\n");
|
2018-03-31 09:29:22 +00:00
|
|
|
}
|
2019-01-09 10:30:11 +00:00
|
|
|
|
2018-12-02 20:39:41 +00:00
|
|
|
if (cs_support(CS_ARCH_MOS65XX)) {
|
2019-06-03 15:20:51 +00:00
|
|
|
printf(" 6502 MOS 6502\n");
|
|
|
|
printf(" 65c02 WDC 65c02\n");
|
|
|
|
printf(" w65c02 WDC w65c02\n");
|
|
|
|
printf(" 65816 WDC 65816 (long m/x)\n");
|
2018-12-02 20:39:41 +00:00
|
|
|
}
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
|
2019-02-01 15:03:47 +00:00
|
|
|
if (cs_support(CS_ARCH_WASM)) {
|
2019-02-18 02:44:12 +00:00
|
|
|
printf(" wasm: Web Assembly\n");
|
2019-02-01 15:03:47 +00:00
|
|
|
}
|
|
|
|
|
2019-02-18 09:39:51 +00:00
|
|
|
if (cs_support(CS_ARCH_BPF)) {
|
|
|
|
printf(" bpf Classic BPF\n");
|
|
|
|
printf(" bpfbe Classic BPF + big endian\n");
|
|
|
|
printf(" ebpf Extended BPF\n");
|
|
|
|
printf(" ebpfbe Extended BPF + big endian\n");
|
|
|
|
}
|
|
|
|
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
if (cs_support(CS_ARCH_RISCV)) {
|
|
|
|
printf(" riscv32 riscv32\n");
|
|
|
|
printf(" riscv64 riscv64\n");
|
|
|
|
}
|
|
|
|
|
2022-09-12 12:26:04 +00:00
|
|
|
if (cs_support(CS_ARCH_SH)) {
|
|
|
|
printf(" sh superh SH1\n");
|
|
|
|
printf(" sh2 superh SH2\n");
|
|
|
|
printf(" sh2e superh SH2E\n");
|
|
|
|
printf(" sh2dsp superh SH2-DSP\n");
|
|
|
|
printf(" sh2a superh SH2A\n");
|
|
|
|
printf(" sh2afpu superh SH2A-FPU\n");
|
|
|
|
printf(" sh3 superh SH3\n");
|
|
|
|
printf(" sh3be superh SH3 big endian\n");
|
|
|
|
printf(" sh3e superh SH3E\n");
|
|
|
|
printf(" sh3ebe superh SH3E big endian\n");
|
|
|
|
printf(" sh3-dsp superh SH3-DSP\n");
|
|
|
|
printf(" sh3-dspbe superh SH3-DSP big endian\n");
|
|
|
|
printf(" sh4 superh SH4\n");
|
|
|
|
printf(" sh4be superh SH4 big endian\n");
|
|
|
|
printf(" sh4a superh SH4A\n");
|
|
|
|
printf(" sh4abe superh SH4A big endian\n");
|
|
|
|
printf(" sh4al-dsp superh SH4AL-DSP\n");
|
|
|
|
printf(" sh4al-dspbe superh SH4AL-DSP big endian\n");
|
|
|
|
}
|
|
|
|
|
2023-03-24 12:17:08 +00:00
|
|
|
if (cs_support(CS_ARCH_TRICORE)) {
|
2023-04-10 17:18:41 +00:00
|
|
|
printf(" tc110 tricore V1.1\n");
|
|
|
|
printf(" tc120 tricore V1.2\n");
|
|
|
|
printf(" tc130 tricore V1.3\n");
|
|
|
|
printf(" tc131 tricore V1.3.1\n");
|
|
|
|
printf(" tc160 tricore V1.6\n");
|
|
|
|
printf(" tc161 tricore V1.6.1\n");
|
|
|
|
printf(" tc162 tricore V1.6.2\n");
|
2023-03-24 12:17:08 +00:00
|
|
|
}
|
|
|
|
|
2017-07-04 08:04:53 +00:00
|
|
|
printf("\nExtra options:\n");
|
|
|
|
printf(" -d show detailed information of the instructions\n");
|
2023-09-05 04:24:59 +00:00
|
|
|
printf(" -r show detailed information of the real instructions (even for alias)\n");
|
|
|
|
printf(" -a Print Capstone register alias (if any). Otherwise LLVM register names are emitted.\n");
|
2019-01-09 10:27:00 +00:00
|
|
|
printf(" -s decode in SKIPDATA mode\n");
|
2019-02-18 02:45:52 +00:00
|
|
|
printf(" -u show immediates as unsigned\n");
|
2019-01-09 10:27:00 +00:00
|
|
|
printf(" -v show version & Capstone core build info\n\n");
|
2016-10-10 07:16:56 +00:00
|
|
|
}
|
|
|
|
|
2017-07-04 07:55:46 +00:00
|
|
|
static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
|
|
|
|
{
|
2019-04-11 01:07:26 +00:00
|
|
|
printf("\tID: %u (%s)\n", ins->id, cs_insn_name(handle, ins->id));
|
2023-09-05 04:24:59 +00:00
|
|
|
if (ins->is_alias) {
|
|
|
|
printf("\tIs alias: %" PRIu64 " (%s) ", ins->alias_id, cs_insn_name(handle, ins->alias_id));
|
|
|
|
printf("with %s operand set\n", ins->usesAliasDetails ? "ALIAS" : "REAL");
|
|
|
|
}
|
2019-04-11 01:07:26 +00:00
|
|
|
|
2017-07-04 07:55:46 +00:00
|
|
|
switch(arch) {
|
|
|
|
case CS_ARCH_X86:
|
|
|
|
print_insn_detail_x86(handle, md, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_ARM:
|
|
|
|
print_insn_detail_arm(handle, ins);
|
|
|
|
break;
|
2023-11-15 04:12:14 +00:00
|
|
|
case CS_ARCH_AARCH64:
|
|
|
|
print_insn_detail_aarch64(handle, ins);
|
2017-07-04 07:55:46 +00:00
|
|
|
break;
|
|
|
|
case CS_ARCH_MIPS:
|
|
|
|
print_insn_detail_mips(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_PPC:
|
|
|
|
print_insn_detail_ppc(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_SPARC:
|
|
|
|
print_insn_detail_sparc(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_SYSZ:
|
|
|
|
print_insn_detail_sysz(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_XCORE:
|
|
|
|
print_insn_detail_xcore(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_M68K:
|
|
|
|
print_insn_detail_m68k(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_TMS320C64X:
|
|
|
|
print_insn_detail_tms320c64x(handle, ins);
|
|
|
|
break;
|
2018-03-31 09:29:22 +00:00
|
|
|
case CS_ARCH_M680X:
|
|
|
|
print_insn_detail_m680x(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_EVM:
|
|
|
|
print_insn_detail_evm(handle, ins);
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
break;
|
2019-02-01 15:03:47 +00:00
|
|
|
case CS_ARCH_WASM:
|
|
|
|
print_insn_detail_wasm(handle, ins);
|
|
|
|
break;
|
2018-12-02 20:39:41 +00:00
|
|
|
case CS_ARCH_MOS65XX:
|
|
|
|
print_insn_detail_mos65xx(handle, ins);
|
|
|
|
break;
|
2019-02-18 09:39:51 +00:00
|
|
|
case CS_ARCH_BPF:
|
|
|
|
print_insn_detail_bpf(handle, ins);
|
|
|
|
break;
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
case CS_ARCH_RISCV:
|
|
|
|
print_insn_detail_riscv(handle, ins);
|
|
|
|
break;
|
2022-09-12 12:26:04 +00:00
|
|
|
case CS_ARCH_SH:
|
|
|
|
print_insn_detail_sh(handle, ins);
|
|
|
|
break;
|
2023-04-23 07:14:03 +00:00
|
|
|
case CS_ARCH_TRICORE:
|
|
|
|
print_insn_detail_tricore(handle, ins);
|
|
|
|
break;
|
2023-12-28 02:10:38 +00:00
|
|
|
case CS_ARCH_ALPHA:
|
|
|
|
print_insn_detail_alpha(handle, ins);
|
|
|
|
break;
|
2017-07-04 07:55:46 +00:00
|
|
|
default: break;
|
|
|
|
}
|
|
|
|
|
2023-07-19 09:56:27 +00:00
|
|
|
if (ins->detail && ins->detail->groups_count) {
|
2017-07-04 07:55:46 +00:00
|
|
|
int j;
|
|
|
|
|
|
|
|
printf("\tGroups: ");
|
|
|
|
for(j = 0; j < ins->detail->groups_count; j++) {
|
|
|
|
printf("%s ", cs_group_name(handle, ins->detail->groups[j]));
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
2016-10-10 07:16:56 +00:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
2017-07-04 07:55:46 +00:00
|
|
|
int i, c;
|
2016-10-10 15:20:29 +00:00
|
|
|
csh handle;
|
|
|
|
char *mode;
|
|
|
|
uint8_t *assembly;
|
|
|
|
size_t count, size;
|
2017-07-04 07:55:46 +00:00
|
|
|
uint64_t address = 0LL;
|
2016-10-10 15:20:29 +00:00
|
|
|
cs_insn *insn;
|
|
|
|
cs_err err;
|
2016-10-21 08:03:35 +00:00
|
|
|
cs_mode md;
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
cs_arch arch = CS_ARCH_ALL;
|
2016-10-21 08:42:47 +00:00
|
|
|
bool detail_flag = false;
|
2017-06-15 18:13:28 +00:00
|
|
|
bool unsigned_flag = false;
|
2019-01-04 09:23:15 +00:00
|
|
|
bool skipdata = false;
|
2023-07-19 09:56:27 +00:00
|
|
|
bool custom_reg_alias = false;
|
2023-09-05 04:24:59 +00:00
|
|
|
bool set_real_detail = false;
|
2017-07-04 08:04:53 +00:00
|
|
|
int args_left;
|
2016-10-10 15:20:29 +00:00
|
|
|
|
2023-09-05 04:24:59 +00:00
|
|
|
while ((c = getopt (argc, argv, "rasudhv")) != -1) {
|
2017-07-04 07:55:46 +00:00
|
|
|
switch (c) {
|
2023-07-19 09:56:27 +00:00
|
|
|
case 'a':
|
|
|
|
custom_reg_alias = true;
|
|
|
|
break;
|
2023-09-05 04:24:59 +00:00
|
|
|
case 'r':
|
|
|
|
set_real_detail = true;
|
|
|
|
break;
|
2019-01-04 09:23:15 +00:00
|
|
|
case 's':
|
|
|
|
skipdata = true;
|
|
|
|
break;
|
2018-03-31 09:29:22 +00:00
|
|
|
case 'u':
|
|
|
|
unsigned_flag = true;
|
|
|
|
break;
|
|
|
|
case 'd':
|
|
|
|
detail_flag = true;
|
|
|
|
break;
|
|
|
|
case 'v':
|
2019-01-23 06:39:01 +00:00
|
|
|
printf("cstool for Capstone Disassembler, v%u.%u.%u\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
|
2019-01-09 10:27:00 +00:00
|
|
|
|
|
|
|
printf("Capstone build: ");
|
|
|
|
if (cs_support(CS_ARCH_X86)) {
|
|
|
|
printf("x86=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_ARM)) {
|
|
|
|
printf("arm=1 ");
|
|
|
|
}
|
|
|
|
|
2023-11-15 04:12:14 +00:00
|
|
|
if (cs_support(CS_ARCH_AARCH64)) {
|
|
|
|
printf("aarch64=1 ");
|
2019-01-09 10:27:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_MIPS)) {
|
|
|
|
printf("mips=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_PPC)) {
|
|
|
|
printf("ppc=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_SPARC)) {
|
|
|
|
printf("sparc=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_SYSZ)) {
|
|
|
|
printf("sysz=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_XCORE)) {
|
|
|
|
printf("xcore=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_M68K)) {
|
|
|
|
printf("m68k=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_TMS320C64X)) {
|
|
|
|
printf("tms320c64x=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_M680X)) {
|
|
|
|
printf("m680x=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_EVM)) {
|
|
|
|
printf("evm=1 ");
|
|
|
|
}
|
2023-04-10 17:18:41 +00:00
|
|
|
|
2019-02-01 15:03:47 +00:00
|
|
|
if (cs_support(CS_ARCH_WASM)) {
|
|
|
|
printf("wasm=1 ");
|
|
|
|
}
|
|
|
|
|
2019-01-09 10:30:11 +00:00
|
|
|
if (cs_support(CS_ARCH_MOS65XX)) {
|
2019-02-18 11:52:51 +00:00
|
|
|
printf("mos65xx=1 ");
|
2019-01-09 10:30:11 +00:00
|
|
|
}
|
|
|
|
|
2019-02-18 12:06:11 +00:00
|
|
|
if (cs_support(CS_ARCH_BPF)) {
|
|
|
|
printf("bpf=1 ");
|
|
|
|
}
|
|
|
|
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
if (cs_support(CS_ARCH_RISCV)) {
|
|
|
|
printf("riscv=1 ");
|
|
|
|
}
|
|
|
|
|
2022-09-12 12:26:04 +00:00
|
|
|
if (cs_support(CS_ARCH_SH)) {
|
|
|
|
printf("sh=1 ");
|
|
|
|
}
|
|
|
|
|
2019-01-09 10:27:00 +00:00
|
|
|
if (cs_support(CS_SUPPORT_DIET)) {
|
|
|
|
printf("diet=1 ");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_SUPPORT_X86_REDUCE)) {
|
|
|
|
printf("x86_reduce=1 ");
|
|
|
|
}
|
|
|
|
|
2023-03-24 12:17:08 +00:00
|
|
|
if (cs_support(CS_ARCH_TRICORE)) {
|
|
|
|
printf("tricore=1 ");
|
|
|
|
}
|
|
|
|
|
2023-12-28 02:10:38 +00:00
|
|
|
if (cs_support(CS_ARCH_ALPHA)) {
|
|
|
|
printf("alpha=1 ");
|
|
|
|
}
|
|
|
|
|
2019-01-09 10:27:00 +00:00
|
|
|
printf("\n");
|
2018-03-31 09:29:22 +00:00
|
|
|
return 0;
|
|
|
|
case 'h':
|
|
|
|
usage(argv[0]);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
2016-10-21 08:03:35 +00:00
|
|
|
}
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
2017-07-04 08:04:53 +00:00
|
|
|
|
|
|
|
args_left = argc - optind;
|
2017-07-04 07:55:46 +00:00
|
|
|
if (args_left < 2 || args_left > 3) {
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
|
2017-07-04 07:55:46 +00:00
|
|
|
mode = argv[optind];
|
|
|
|
assembly = preprocess(argv[optind + 1], &size);
|
2017-07-26 15:22:46 +00:00
|
|
|
if (!assembly) {
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
2017-07-04 08:04:53 +00:00
|
|
|
|
2017-07-04 07:55:46 +00:00
|
|
|
if (args_left == 3) {
|
|
|
|
char *temp, *src = argv[optind + 2];
|
|
|
|
address = strtoull(src, &temp, 16);
|
|
|
|
if (temp == src || *temp != '\0' || errno == ERANGE) {
|
|
|
|
printf("ERROR: invalid address argument, quit!\n");
|
|
|
|
return -2;
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-04 08:04:53 +00:00
|
|
|
for (i = 0; all_archs[i].name; i++) {
|
|
|
|
if (!strcmp(all_archs[i].name, mode)) {
|
|
|
|
arch = all_archs[i].arch;
|
|
|
|
err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle);
|
2017-07-04 07:55:46 +00:00
|
|
|
if (!err) {
|
2017-07-04 08:04:53 +00:00
|
|
|
md = all_archs[i].mode;
|
2017-07-04 07:55:46 +00:00
|
|
|
if (strstr (mode, "att")) {
|
|
|
|
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
|
|
|
|
}
|
2019-01-04 09:23:15 +00:00
|
|
|
|
|
|
|
// turn on SKIPDATA mode
|
|
|
|
if (skipdata)
|
|
|
|
cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON);
|
2017-07-04 07:55:46 +00:00
|
|
|
}
|
|
|
|
break;
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
if (arch == CS_ARCH_ALL) {
|
|
|
|
printf("ERROR: Invalid <arch+mode>: \"%s\", quit!\n", mode);
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-10 15:20:29 +00:00
|
|
|
if (err) {
|
|
|
|
printf("ERROR: Failed on cs_open(), quit!\n");
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-21 08:42:47 +00:00
|
|
|
if (detail_flag) {
|
2016-10-21 08:03:35 +00:00
|
|
|
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
|
|
|
|
}
|
2017-07-04 08:04:53 +00:00
|
|
|
|
2017-06-15 18:13:28 +00:00
|
|
|
if (unsigned_flag) {
|
|
|
|
cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON);
|
|
|
|
}
|
2016-10-14 09:29:56 +00:00
|
|
|
|
2023-07-19 09:56:27 +00:00
|
|
|
if (custom_reg_alias) {
|
|
|
|
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS);
|
|
|
|
}
|
|
|
|
|
2023-09-05 04:24:59 +00:00
|
|
|
if (set_real_detail) {
|
|
|
|
cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL);
|
|
|
|
}
|
|
|
|
|
2016-10-21 08:03:35 +00:00
|
|
|
count = cs_disasm(handle, assembly, size, address, 0, &insn);
|
2016-10-10 15:20:29 +00:00
|
|
|
if (count > 0) {
|
2016-10-11 08:19:27 +00:00
|
|
|
size_t i;
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
int j;
|
2017-07-04 08:04:53 +00:00
|
|
|
|
2017-10-24 17:03:24 +00:00
|
|
|
printf("%2"PRIx64" ", insn[i].address);
|
2016-10-11 08:19:27 +00:00
|
|
|
for (j = 0; j < insn[i].size; j++) {
|
2017-09-06 13:35:19 +00:00
|
|
|
if (j > 0)
|
|
|
|
putchar(' ');
|
2016-10-11 08:19:27 +00:00
|
|
|
printf("%02x", insn[i].bytes[j]);
|
|
|
|
}
|
2022-12-18 09:26:24 +00:00
|
|
|
// Align instruction when it varies in size.
|
|
|
|
// ex: x86, s390x or compressed riscv
|
|
|
|
if (arch == CS_ARCH_RISCV) {
|
|
|
|
for (; j < 4; j++) {
|
|
|
|
printf(" ");
|
|
|
|
}
|
|
|
|
} else if (arch == CS_ARCH_X86) {
|
2016-10-11 08:19:27 +00:00
|
|
|
for (; j < 16; j++) {
|
2017-10-24 17:03:24 +00:00
|
|
|
printf(" ");
|
2016-10-11 08:19:27 +00:00
|
|
|
}
|
2020-09-03 08:49:29 +00:00
|
|
|
} else if (arch == CS_ARCH_SYSZ) {
|
|
|
|
for (; j < 6; j++) {
|
|
|
|
printf(" ");
|
|
|
|
}
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
2016-10-21 08:42:47 +00:00
|
|
|
|
2016-10-11 08:19:27 +00:00
|
|
|
printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str);
|
2016-10-21 08:42:47 +00:00
|
|
|
|
|
|
|
if (detail_flag) {
|
2017-07-04 07:55:46 +00:00
|
|
|
print_details(handle, arch, md, &insn[i]);
|
2016-10-21 08:03:35 +00:00
|
|
|
}
|
2016-10-10 15:20:29 +00:00
|
|
|
}
|
2016-11-04 16:43:22 +00:00
|
|
|
|
2016-10-10 15:20:29 +00:00
|
|
|
cs_free(insn, count);
|
|
|
|
} else {
|
|
|
|
printf("ERROR: invalid assembly code\n");
|
|
|
|
return(-4);
|
|
|
|
}
|
|
|
|
|
|
|
|
cs_close(&handle);
|
2018-07-24 02:19:07 +00:00
|
|
|
free(assembly);
|
2016-10-10 15:20:29 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-10 07:16:56 +00:00
|
|
|
}
|