* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
- Add support for new Tricore architectures
- Clean up redundant instructions definitions
- Modify architecture options for the TRICORE mode
- Update disallowed modes for Tricore architecture
- Add new instruction `MOVZ_A`, remove instruction `NOT`, and add several new multiply and multiply-subtract instructions
- Move `multiclass mISR_1` and `multiclass mISYS_0` to separate file and fix typo in `rfe` instruction in `mISYS_0`
- Add support for new CPU feature `TriCore_FEATURE_HasV162` and update relevant inc files.
- Add 3 new TriCore instructions
- Remove TriCore instruction "TriCore_INS_INIT"
- Alphabetized and rearranged various TriCore instructions
- Commented out code remains in the diff but is not part of the program.
14.0.5, and introduced new arm64 operand types.
New operand type for svcr MSR/MRS/SMSTART/SMSTOP instructions to
facilitate easier cstool printing.
New operand type for SME instructions with a matrix register that is
indexed.
