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1531 Commits

Author SHA1 Message Date
pancake
9039228b58 Honor Q as an alias for q! in visual and prompt 2016-12-19 04:46:50 +01:00
pancake
2c5400e03e Fix more CIDs, memleaks mainly 2016-12-19 04:21:56 +01:00
Álvaro Felipe Melchor
a874de805e clean up code applying coding style 2016-12-15 21:04:27 +01:00
Gerardo García Peña
f40cbcee33 Set ATmega8 MCU by default. (#6291) 2016-12-08 01:22:54 +01:00
Álvaro Felipe Melchor
028e8f0ca3 Fix few covs 2016-12-04 22:26:17 +01:00
Sven Steinbauer
e4b5f0f32b Cleanup opjc for x86_nz 2016-12-01 10:07:53 +00:00
pancake
cb06c9c26b Fix #6270 - Honor current offset when assembling conditional jumps in x86 2016-11-30 16:22:34 +01:00
pancake
7e07579cdc Fix last covs 2016-11-20 12:20:05 +01:00
Sven Steinbauer
5010de936f Add br and blr (#6217) 2016-11-17 16:54:24 +00:00
Sven Steinbauer
8cf9af578c Add arm64 branch instructions (#6216) 2016-11-17 17:05:13 +01:00
Sven Steinbauer
dec588687a Fix add and sub for arm thumb FIX #6181 (#6198) 
* Enhance sub op support for thumb arch

Generate correct instructions up to 0x100

* Improve support for add instruction for thumb arch
 2016-11-16 11:25:11 +00:00
pancake
23cb88355d Remove global code_align into RAsmCode 2016-11-16 01:24:09 +01:00
pancake
72b2249110 aae now flag all syscalls found in the binary 2016-11-15 12:55:09 +01:00
pancake
11f2c4fe4f Add more movk/movz/movn for the arm64 assembler 2016-11-15 11:57:48 +01:00
radare
7852d92713 thumb assembly issues fix #3122 (#6189) 
* Fix thumb ldr r0, [rN] assembly

* Handle numeric values for ldr rN, [rN, N]

does not handle special cases with values ending in 0, 4, 8

* Fix ldr assembly for 4 bit values

values that can be expressed with 4 bits care outputted with shorter instructions.

* Add support for blx op with register values

* Fix mov instruction with register as first parm
 2016-11-14 14:23:38 +01:00
Sven Steinbauer
cd37be0406 Fix mov instruction with register as first parm 2016-11-14 12:14:51 +00:00
Sven Steinbauer
64bea8794c Add support for blx op with register values 2016-11-14 11:48:49 +00:00
Sven Steinbauer
ef448c64fe Fix ldr assembly for 4 bit values 
values that can be expressed with 4 bits care outputted with shorter instructions.
 2016-11-14 09:18:37 +00:00
Duncan Ogilvie
e16b490db5 fixed incorrect jna/jbe (#6185) 2016-11-12 17:58:00 +01:00
Sebastian Reichel
e9383b1441 Arch independent data in share (#6183) 
* magic data is architecture independent

* fcnsign data is architecture independent

* opcode data is architecture independent

* syscall data is architecture independent

* hud data is architecture independent
 2016-11-12 11:08:34 +01:00
Sven Steinbauer
9eb8802a0e Handle numeric values for ldr rN, [rN, N] 
does not handle special cases with values ending in 0, 4, 8
 2016-11-11 19:09:42 +00:00
Sven Steinbauer
26cdbfdbdc Fix thumb ldr r0, [rN] assembly 2016-11-11 08:37:06 +00:00
Sebastian Reichel
ff868af3be asm_m68k_cs: Add missing CORELIB check (#6169) 
radare_plugin should not be defined for builtin plugins.
 2016-11-10 10:14:45 +01:00
Stefan Marsiske
ec4e60d2bd fix radare_plugin redundantly defined (#6165) 
without these guards the linker complains:

p/asm_z80.o:(.data.rel+0x0): multiple definition of `radare_plugin'
p/asm_m68k_cs.o:(.data.rel+0x0): first defined here
collect2: error: ld returned 1 exit status
 2016-11-09 17:35:47 +01:00
Álvaro Felipe Melchor
f5166f936d Fix some meamleaks (#6156) 2016-11-09 02:28:14 +01:00
Álvaro Felipe Melchor
3222447eab Fix warnings when compiling in linux 2016-11-08 01:58:07 +01:00
Álvaro Felipe Melchor
9f6c3a2c8a fix warning in tms320 s/st8/char/g 2016-11-07 22:31:09 +01:00
Álvaro Felipe Melchor
f941d219fe revert change on ins.c 2016-11-07 21:23:05 +01:00
Álvaro Felipe Melchor
302d3f52e9 Take into account section alignment 2016-11-06 22:00:08 +01:00
Sven Steinbauer
e797258741 Test for valid numbers in arm getnum function (#6118) 
* Test for valid numbers in arm getnum function

Using strtod it's possible to test if the string passed in is a valid
number

Also handles hexvalues

* KISS the fix
 2016-11-05 10:38:42 +01:00
szt
f29a91b63a arm chars are unsigned by default 
http://blog.cdleary.com/2012/11/arm-chars-are-unsigned-by-default/
 2016-11-04 04:49:34 +01:00
Sven Steinbauer
80da50f31f Error on invalid b instruction (#6109) 
If label resolves to an offset of 0, assume instruction invalid
 2016-11-04 00:34:56 +01:00
Álvaro Felipe Melchor
601bd60e4d refix r_asm_set_big_endian 2016-11-03 13:47:51 +01:00
Álvaro Felipe Melchor
53655fd3c2 fix regression 2016-11-03 13:42:37 +01:00
pancake
2e23217ccd Add support for .endian rasm2 directive 2016-11-03 12:49:16 +01:00
pancake
cb1f0c79ce Support /**/ in a single line 2016-11-03 12:32:50 +01:00
pancake
0fb0a170d2 Fix /**/ comments in rasm2 2016-11-03 12:29:08 +01:00
pancake
90fcf76623 Initial support for .align in rasm2 2016-11-03 12:01:54 +01:00
pancake
9d1f080b59 Fix heap overflow in rasm2 2016-11-03 11:11:50 +01:00
pancake
39f25ae2db Support /**/ in rasm2 -f 2016-11-03 10:39:20 +01:00
pancake
37454c1dc1 Fix #6052 - ?O supports name -> id 2016-11-02 03:49:55 +01:00
Sven Steinbauer
ab2551691c Add arm shift ops FIX #5482 (#6081) 2016-11-01 00:56:27 +01:00
pancake
4421b2ef72 Fix m68k plugin name 2016-10-31 00:00:01 +01:00
Maijin
e5b30f91d8 Add Oj Fix #6074 
Add Oj Fix #6074
 2016-10-30 12:39:49 +01:00
pancake
e31164a5fa Fix latest covs 2016-10-29 13:06:11 +02:00
Sven Steinbauer
54afd47d9e Remove m68k asm and anal from core (#6063) 
* Remove m68k disassembler - Moving to extras
* Remove m68k anal plugin - Gets moved to r2e to be installed with m68k
 2016-10-28 12:54:48 +02:00
Sven Steinbauer
7d5f4cbde7 Assemble 64bit byte mov correctly [FIX 6042] (#6053) 
$ rasm2 -a x86 -b 64 'mov byte [rbp - 0x100], 2'
c68500ffffff02

Oddly this also compiles correctly before this patch with keystone
installed. Not sure as to why yet.
 2016-10-27 15:14:10 +02:00
pancake
94d47c79bb Completely remove all references to list.h 2016-10-27 13:33:27 +02:00
pancake
e925e04ea2 Fix crash in disassembler 2016-10-27 01:42:00 +02:00
pancake
d41b577106 Fix #5924 - r_flags -> r_flag 2016-10-27 01:07:58 +02:00
pancake
3ab7122df2 Implement ?O and r_asm_mnemonics() new API 2016-10-27 00:54:48 +02:00
pancake
589ac97bda Fix some overflow-related covs 2016-10-26 23:40:17 +02:00
pancake
8d37adc546 Fix all pending null-deref covs 2016-10-26 23:22:04 +02:00
Álvaro Felipe Melchor
a2befc8adc Enhance performance in r_anal_fcn_get_in() using tinyrange and sorted adds 
* added sorted parameter in r_list
* use r_list_sort in r_range_sort
* some clean up
* added is_data into RBinSection
* use tinyrange by default to improve speed
 2016-10-25 01:12:06 +02:00
Sven Steinbauer
52cc4dfe95 Move Z80 non-commercial to r2e (#6015) 
* Move z80 non-commercial to r2e

Rename z80-cr to z80 as a consequence as it will be the default z80 disassembler

* Add GPL z80 assembler back in

* Fix Clang build
 2016-10-24 13:21:36 +01:00
Álvaro Felipe Melchor
0cd32b4090 fix build 2016-10-24 11:58:35 +02:00
Sven Steinbauer
aa5fd3253c Update and fix LGPL Z80 disassembler (#6009) 
* Fix dd IX instructions

* Fix segfault for dd and de ops

Although only seemed to happen on OSX, not on linux.

* Fix ed op

* Remove invalid instruction "in f, [c]" which is not referenced in
http://clrhome.org/table/

* fix bad offsets to ops following removed one

* Fix fd ops with bad type flags

* Fix ed and fdcb ops

Remove debug prints
 2016-10-24 10:28:59 +01:00
pancake
35d9eef757 Fix 20 more covs (divBy0, dbl3, negidx, bufovr, ..) 2016-10-20 15:39:36 +02:00
pancake
be9df39f6f Fixed 40 null derefs reported by coverity 2016-10-20 15:02:25 +02:00
pancake
7a1b6871d9 Fix a bunch of outstanding coverities 2016-10-20 14:11:02 +02:00
Sven Steinbauer
4a2fba6168 Add segment reg support and numerous fixes FIX #5967 (#5995) 
* Add support for seg registers

Support added for mov and pop instructions

[fs] is treated as [fs:0] which is not equivalent

Accepts sreg:[x] and [sreg:x] syntax

* Error if mov op reg sizes differ

also add support for 16bit register mov ops

* Improve segment register handling for mov op

* Fix opcode for 64bit instr with 32bits regs

* Refactor parsing of segment reg offset
 2016-10-19 21:10:17 +01:00
Sven Steinbauer
f6b0ba574b Fix for issue #5976 (#5979) 
Check that register is not memory i.e. [eax] to generate correct opcode
 2016-10-17 15:45:38 +02:00
szt
45bbca4e29 Fix "orr" in ARM assembler (#5958) 
https://github.com/radare/radare2/issues/5954 fix
 2016-10-12 23:33:53 +02:00
Álvaro Felipe Melchor
84b4b1b8f6 fix regression 2016-10-10 21:09:30 +02:00
pancake
3ae8b9813b Get rid of some %\d$ constructions in anal_8051.c for #3944 2016-10-10 10:20:51 +02:00
Duncan Ogilvie
d0cccc5ec7 updated various opcode descriptions (#5948) 2016-10-09 19:11:40 +02:00
Álvaro Felipe Melchor
66a55302ee Fix build 2016-10-08 13:25:16 +02:00
pancake
cd26e34a7b Blind fix #5938 - remove some __FILE__ references 2016-10-08 03:01:22 +02:00
pancake
a8af78c7a6 Rollback the z80 change 2016-10-08 02:40:40 +02:00
pancake
0cf6623f52 Kill the z80.cr plugin, and use the disasm into z80 2016-10-08 01:35:27 +02:00
Duncan Ogilvie
8386438ea0 fixed and added opcode descriptions (#5942) 2016-10-07 18:35:40 +02:00
pancake
d7e0be5dad Implement rasm2 -s? and refactor this a bit 2016-10-04 15:01:02 +02:00
pancake
1e89dddd87 Fixes in oa, asm.bits, avr and io debug issues 2016-09-26 00:46:20 +02:00
Álvaro Felipe Melchor
7c8292b9fb Fix warnings and coding style 2016-09-25 01:27:05 +02:00
h4ng3r
e1889b31a1 Fix some BR test from asm.dalvik 2016-09-25 01:26:52 +02:00
Sven Steinbauer
8ab5f5fb5b Add short jumps to nz (#5832) 2016-09-23 17:26:07 +02:00
Marc
0c8556bb22 Fix some DEX disasm issues (#5829) 2016-09-23 00:33:25 +02:00
Vlad Ivanov
438f151d6c asm_xtensa: fix possible buffer overrun (#5820) 2016-09-22 12:21:37 +02:00
Gerardo García Peña
91cb15a3e7 New opcodes and operations in AVR anal plugin. (#5783) 2016-09-20 13:48:17 +02:00
Álvaro Felipe Melchor
05ae77eda4 fix warning & remove check in version info elf 2016-09-19 15:47:19 +02:00
Sven Steinbauer
2996538700 Fix #5633 - Change x == NULL to correct syntax 2016-09-19 14:44:47 +02:00
pancake
e10c664c55 Add msr/mrs for the armass64 assembler 2016-09-16 18:27:42 +02:00
pancake
1449d61850 Fix regression in rasm2 -d 2016-09-15 17:30:38 +02:00
pancake
4f6b64a984 Some code cleanup/review for rasm2 + arc 2016-09-15 16:21:44 +02:00
Sylvain Pelissier
bfeff9f10b ARM conditional instruction information (#5747) 2016-09-13 15:12:07 +02:00
pancake
496da56a9e Fix sys/ios-static.sh 2016-09-12 20:52:12 +02:00
pancake
90fb18dcfc Fix endian issue in mips.gnu assembler 2016-09-02 17:12:28 +02:00
Maijin
48cbf32b88 Fix #5666 2016-09-02 14:15:05 +02:00
Vlad Ivanov
19d4154e39 anal_xtensa: initial ESIL support 2016-09-01 22:50:28 +02:00
pancake
0a1e99ce04 Fix assemble() endianness for mips 2016-09-01 22:46:07 +02:00
pancake
4429de16f9 Fix pa/pad for big/lil endian 2016-09-01 22:34:28 +02:00
pancake
dc545c8102 Fix regression in rasm2 -e 2016-09-01 21:50:04 +02:00
Rakholiya Jenish
f3085dd3e4 remove %hh usage 2016-08-19 19:58:38 -04:00
Mitchell Johnson
7661c3930a Add a missing MSP430 constant register instruction encoding (#5548) 
* Fix a missing #1 constant-generator encoding for msp430
* Fix up some tab/space mixing
 2016-08-18 15:58:38 +02:00
dx
4b263b3475 Fix a handful of boring leaks (#5518) 
Valgrinding to get exp. Testing with "r2 -Aqcq /bin/ls"

Before:

       definitely lost: 22,735 bytes in 250 blocks
       indirectly lost: 23,542 bytes in 605 blocks
         possibly lost: 2,464 bytes in 7 blocks
       still reachable: 3,876,216 bytes in 80,761 blocks

After:

       definitely lost: 25,216 bytes in 58 blocks
       indirectly lost: 24,830 bytes in 739 blocks
         possibly lost: 0 bytes in 0 blocks
       still reachable: 20,105 bytes in 34 blocks

The "goto beach" (named like that for consistency) change resulted in
freeing most of the "still reachable" stuff on quit, which also moved
stuff out of "possibly lost", so.. it looks like it's leaking more now.
Yay.
 2016-08-16 00:45:33 +02:00
pancake
fe0530aa9c Fix OOB read in vax disassembler 2016-08-14 19:35:24 +02:00
Álvaro Felipe Melchor
dc5673ec3a Fix regression with the arm/thumb changes (#5464) 
Now we build a list of ranges (RAnalRange) based on anal hints to handle the
bits in a better way in the case of arm/thumb

Now instead of asm.bits that rules the whole binary we can define ranges with
anal hints
 2016-08-10 18:49:44 +02:00
pancake
6d1d02024e Remove problematic asprintf defines from libiberty.h 2016-08-08 13:40:50 +02:00
Álvaro Felipe Melchor
0bc983027f improve arm/thumb in elf file format and disasm 2016-08-07 17:38:34 +02:00
pancake
a211c48bd5 Update some indentation in asm.dalvik 2016-08-06 11:58:54 +02:00
pancake
744fad6418 Port to Termux (Android-Debian environment) 2016-08-06 05:12:58 +01:00
pancake
cc01682132 Some playground with DEX 2016-08-05 13:11:30 +02:00
Sven Steinbauer
ca96796268 Prevent possible max shift value (#5391) 
Protect against shifts that might be bigger than 31
 2016-07-27 13:21:36 +02:00
Álvaro Felipe Melchor
9e412a9048 fix again the crash in nz 2016-07-26 23:08:29 +02:00
Álvaro Felipe Melchor
5d493c1950 refix crash in nz assembler 2016-07-26 22:37:20 +02:00
Álvaro Felipe Melchor
3c8066ce57 fix crash in nz assembler 2016-07-26 22:08:25 +02:00
pancake
2dda628da1 Null terminate array of instructions in x86.nz to fix a crash 2016-07-26 18:46:48 +02:00
pancake
b342358513 Fix x86.nz warnings from clang 2016-07-25 21:26:35 +02:00
Sven Steinbauer
e436e66428 Kill dead code (#5378) 
Fix dead code warnings from coverity scan
 2016-07-25 21:24:29 +02:00
Sven Steinbauer
c5635eec3c Fix error on invalid reg (#5374) 
some instructions wouldn't error on invalid source or dest values.
Set valid reg to false by default and only set true if actually valid
 2016-07-25 18:52:58 +02:00
Sven Steinbauer
887f5bfa8c Support extended 64bit registers [Fix #5364] 2016-07-25 18:02:46 +02:00
pancake
6c549b424a Remove x86.tab from r2 master (moved to extras) 2016-07-25 03:47:47 +02:00
pancake
845bfebc9e Fix null deref in x86.nz 2016-07-25 03:42:28 +02:00
pancake
91fe80f4ca Fix avr's rjmp disasm, analysis and esil 2016-07-25 03:19:16 +02:00
Maijin
22de895ef5 Rename CSR disasm/anal into XAP4 Fix #5355 2016-07-23 00:41:42 +02:00
Sven Steinbauer
996e767e0d Refactor nz assembler 
Refactor nz assembler
 2016-07-22 18:33:54 +02:00
Maijin
e3a05bdb76 Kill libr/asm/t 2016-07-12 22:51:47 +02:00
Maijin
c274afe748 Fix #3286 - Use stdbool.h 2016-07-12 22:15:19 +02:00
bsmiles32
622e828e1d Add basic support for N64 RSP processor. (#5269) 
* Add basic support for N64 RSP processor.
This includes:
* a table driven instruction decoder (rsp_idec)
* a disassembler
* a very primitive anal plugin
 2016-07-03 22:03:26 +02:00
pancake
2cc433cefa Fixes for avr to make travis green 2016-07-02 02:37:00 +02:00
pancake
9864ef8841 Lowercase all registers to match RReg rules in AVR 2016-07-01 15:22:23 +02:00
Álvaro Felipe Melchor
4396598081 Fix oob read reported by revskill on mk68 code 2016-06-30 23:15:25 +02:00
Álvaro Felipe Melchor
d69a502eb5 fix indentation m68k_disasm 2016-06-30 23:01:24 +02:00
pancake
98e90dd3cf Implement RSyscall.IO in disasm loop for X86 and AVR 2016-06-29 17:02:43 +02:00
pancake
fe644e60ff Fix crash in r2 -a arm -b32 -c'wa str r0' 2016-06-27 15:58:43 +02:00
Sven Steinbauer
2c086751b9 Add fsincos instruction [fix #5204] (#5205) 2016-06-24 15:08:52 +02:00
Sven Steinbauer
995c952c5d Fix #5097 : mov instruction with rex regs 
sil, dil, spl, and bpl, registers now supported
 2016-06-22 13:04:23 +02:00
Sven Steinbauer
db76ef6497 Add bt instruction [fix #1277] (#5194) 2016-06-22 12:31:08 +02:00
Sylvain Pelissier
50aed82b66 Add lfence, mfence and sfence to x86.nz (#5193) 2016-06-22 10:29:26 +02:00
danielps
1b21628964 V810: Fix floating-point instructions (#5186) 2016-06-20 23:39:01 +02:00
pancake
f96f00d62d Fix #5158 - Merge r_db into r_util 2016-06-17 12:19:16 +02:00
Sven Steinbauer
d45101eebe Add offset support to add instruction (#5137) 
support syntax for

add eax, [ecx]
add ecx, [eba +/- 3]
 2016-06-15 15:33:14 +02:00
pancake
e032a48cbe Fix latest 26 COVs 2016-06-14 23:47:58 +02:00
pancake
8a82e5cae6 Implement 'cbz' in armass-thumb 2016-06-13 11:12:20 +02:00
Sven Steinbauer
deebcc5f46 Add check for 64bit overflow (#5116) 2016-06-10 17:02:51 +02:00
Jeffrey Crowell
3e8a0cc693 replace usage of killed r_str_trim 2016-06-10 01:12:07 +00:00
Sven Steinbauer
00e964e9b6 Add support to mov for negative immediates (#5090) 
mov eax, -3
 2016-06-07 12:23:44 +02:00
Sven Steinbauer
6e4a1b55b1 Error if moving 64bit val to 32bit reg (#5088) 
mov eax, 0x1122334455667788 now errors if trying to assemble with -b64.
 2016-06-07 11:01:35 +02:00
pancake
eb9feef231 Fixes for powerpc endian in mach0 and other issues 2016-06-06 22:57:22 +02:00
pancake
608b79d2b4 Finally fix the build on osx-ppc 2016-06-06 17:30:07 +02:00
pancake
5903bc0d10 Fix #5083 - null deref in armass 2016-06-06 16:53:56 +02:00
pancake
d3394d5a7a Fix latest 28 COVs 2016-06-02 03:19:31 +02:00
pancake
03294af32b Fix null deref in libr_asm and add lang-python r2pm pkg 2016-06-02 02:45:38 +02:00
pancake
95b2e511f5 Fix some warnings 2016-06-01 12:23:10 +02:00
Sven Steinbauer
63dd8590d7 Refactor mov assembly for nz (#5057) 
* reg offset code consolidated to single location and simplified
* Refactor `getreg` for `arg` and `arg2` to use `r0` and `r1` throughout
        `mov` case

Should clean it up a little.
 2016-06-01 12:15:33 +02:00
Karol Harasim
d190e0d3c3 Add description for Xtensa instructions 2016-05-31 21:48:18 +02:00
pancake
c64eeaa266 Initial implementation of asm.assembler to select different assembler plugin than the disasm 2016-05-30 18:53:32 +02:00
Duncan Ogilvie
216de66e68 fixed jcc (#5034) 2016-05-30 04:21:02 +02:00
Duncan Ogilvie
021a3ea8b2 Update x86 (#5035) 2016-05-30 04:20:29 +02:00
Duncan Ogilvie
18ffea18cc added/fixed various cmovXX opcodes (#5033) 
As per the Intel manual:

```
CMOVcc - Conditional Move:
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 47 /r        | CMOVA r16, r/m16  | RM   | Valid      | Valid          | Move if above (CF=0 and ZF=0).         
| REX.W + 0F 43 /r| CMOVAE r64, r/m64 | RM   | Valid      | N.E.           | Move if above or equal (CF=0).         
| 0F 42 /r        | CMOVB r16, r/m16  | RM   | Valid      | Valid          | Move if below (CF=1).                  
| REX.W + 0F 46 /r| CMOVBE r64, r/m64 | RM   | Valid      | N.E.           | Move if below or equal (CF=1 or ZF=1). 
| 0F 42 /r        | CMOVC r16, r/m16  | RM   | Valid      | Valid          | Move if carry (CF=1).                  
| REX.W + 0F 44 /r| CMOVE r64, r/m64  | RM   | Valid      | N.E.           | Move if equal (ZF=1).                  
| 0F 4F /r        | CMOVG r16, r/m16  | RM   | Valid      | Valid          | Move if greater (ZF=0 and SF=OF).      
| REX.W + 0F 4D /r| CMOVGE r64, r/m64 | RM   | Valid      | N.E.           | Move if greater or equal (SF=OF).      
| 0F 4C /r        | CMOVL r16, r/m16  | RM   | Valid      | Valid          | Move if less (SF!= OF).                 
| REX.W + 0F 4E /r| CMOVLE r64, r/m64 | RM   | Valid      | N.E.           | Move if less or equal (ZF=1 or SF!= OF).
| 0F 46 /r        | CMOVNA r16, r/m16 | RM   | Valid      | Valid          | Move if not above (CF=1 or ZF=1).      
| REX.W + 0F 42 /r| CMOVNAE r64, r/m64| RM   | Valid      | N.E.           | Move if not above or equal (CF=1).     
| 0F 43 /r        | CMOVNB r16, r/m16 | RM   | Valid      | Valid          | Move if not below (CF=0).              
| REX.W + 0F 47 /r| CMOVNBE r64, r/m64| RM   | Valid      | N.E.           | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| 0F 43 /r        | CMOVNC r16, r/m16 | RM   | Valid      | Valid          | Move if not carry (CF=0).              
| REX.W + 0F 45 /r| CMOVNE r64, r/m64 | RM   | Valid      | N.E.           | Move if not equal (ZF=0).              
| 0F 4E /r        | CMOVNG r16, r/m16 | RM   | Valid      | Valid          | Move if not greater (ZF=1 or SF!= OF).  
| REX.W + 0F 4C /r| CMOVNGE r64, r/m64| RM   | Valid      | N.E.           | Move if not greater or equal (SF!= OF). 
| 0F 4D /r        | CMOVNL r16, r/m16 | RM   | Valid      | Valid          | Move if not less (SF=OF).              
| REX.W + 0F 4F /r| CMOVNLE r64, r/m64| RM   | Valid      | N.E.           | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| 0F 41 /r        | CMOVNO r16, r/m16 | RM   | Valid      | Valid          | Move if not overflow (OF=0).           
| REX.W + 0F 4B /r| CMOVNP r64, r/m64 | RM   | Valid      | N.E.           | Move if not parity (PF=0).             
| 0F 49 /r        | CMOVNS r16, r/m16 | RM   | Valid      | Valid          | Move if not sign (SF=0).               
| REX.W + 0F 45 /r| CMOVNZ r64, r/m64 | RM   | Valid      | N.E.           | Move if not zero (ZF=0).               
| 0F 40 /r        | CMOVO r16, r/m16  | RM   | Valid      | Valid          | Move if overflow (OF=1).               
| REX.W + 0F 4A /r| CMOVP r64, r/m64  | RM   | Valid      | N.E.           | Move if parity (PF=1).                 
| 0F 4A /r        | CMOVPE r16, r/m16 | RM   | Valid      | Valid          | Move if parity even (PF=1).            
| REX.W + 0F 4B /r| CMOVPO r64, r/m64 | RM   | Valid      | N.E.           | Move if parity odd (PF=0).             
| 0F 48 /r        | CMOVS r16, r/m16  | RM   | Valid      | Valid          | Move if sign (SF=1).                   
| REX.W + 0F 44 /r| CMOVZ r64, r/m64  | RM   | Valid      | N.E.           | Move if zero (ZF=1).
```

* fixed typo

* or -> nor
 2016-05-30 04:20:19 +02:00
Sven Steinbauer
c58689bae1 Fixes for mov op for nz assembler (#5020) 
A number of fixes and updates to the `mov` command for the nz assembler
including:

* handling of `esp` register in more cases
* able to handle negative offsets for target register both byte and word
* able to handle negative offsets for target with immediate value as
        source, both byte and word
* refactor mov block of code to be more consistent (further work needed)
 2016-05-27 18:11:01 +02:00
Sven Steinbauer
76a4e0ca7a Add support for immediate word for sub (#5006) 
`nz` now generates the correct opcode when using a word as an immediate
in the `sub` instruction with a register + offset as the target

Also adds support for word register offsets and refactors that portion
of the code a little

For 32bit only so far
 2016-05-25 17:22:00 +02:00
jvoisin
4b8af71ef4 Removed a duplicate loopne and loopnz entry 
removed a duplicate `loopne` and `loopnz` entry
 2016-05-25 15:24:13 +02:00
Jeffrey Crowell
2a77791616 add 64bit xchg instruction 
still broken for the special case of xchg (E|R)ax, r(32|64)

but will add that next
 2016-05-24 15:13:37 +00:00
Roman Valls Guimerà
6f66ba9b84 Typo "intro"->"into memory" (#4991) 2016-05-24 16:07:38 +02:00
Anton Kochkov
f6b18bcb56 Fix CID 1356018 2016-05-24 08:54:39 +03:00
Sven Steinbauer
8da8ad740f Cleanup fixes 
* For commit comments and compiler errors
* Fixes for PR comments
* fix some "infer fixes" commits

Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
 2016-05-23 11:25:44 +02:00
Sven Steinbauer
599b6553e4 Infer fixes for asm 
Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
 2016-05-23 11:25:44 +02:00
pancake
7f6029f17c Fix OR x86.nz test 2016-05-18 11:17:26 +02:00
pancake
2fd754a76c Fix #4938 - Implement 'or REG, NUM' in the x86.nz assembler 2016-05-18 10:48:48 +02:00
Riccardo Schirone
5b92204c27 asm/arch/avr: do not print space if there are no operands 2016-05-17 13:18:23 +02:00
pancake
22989f1ce9 Workaround for x86.nz inc [eax] 2016-05-14 10:59:54 +02:00
Sven Steinbauer
074b327c1c Fix #3644 : Add SIB addressing support to nz compiler 2016-05-13 11:45:54 +02:00
pancake
b4bb247791 Add nop for arm64 assembler 2016-05-10 11:22:13 +02:00
Sven Steinbauer
766b9ec4f0 Add support for dword offsets (#4825) 
* Add support for dword offsets to internal assembler

Internal assembler produces incorrect opcodes for offsets that were
greater than a short.

    rasm2 "mov eax, [eax + 1337]"
    8b8039

This adds support for values >127.

    rasm2 "mov eax, [eax + 1337]"
    8b8039050000

producing the same output as the `nasm` assembler.

* Fix support for negative short and dword offsets

Handle negative offsets for `mov` instructions both short and dword
sizes.

* Whitespace fixes

* Remove rogue character

Remove the reogue `:` that got into the code
 2016-05-09 15:25:20 +02:00
Damien Zammit
5e1ad580db build: fix warnings 2016-05-08 12:21:11 +02:00
Sven Steinbauer
7c0b3eb64a Fix #4745 incorrect assembly for x86 mov (#4791) 2016-05-06 16:08:41 +02:00
Damien Zammit
632dccc217 Remove LIL_ENDIAN macro and configure option 
TODO: Remove other endian cruft from:
- hashing algs
- judy
- squashfs
- grub
- tms320

Signed-off-by: Damien Zammit <damien@zamaudio.com>
 2016-05-06 10:21:55 +02:00
Damien Zammit
af0a865d9f WIP - Totally remove host endianness dependence 
- Adds endian aware functions
- Removes references to host endian
- Uses binary detected endianness else tries LE and restricts by RAsmPlugin
- Fixes gdb debugger endianness when debugging BE qemu gdbserver

Signed-off-by: Damien Zammit <damien@zamaudio.com>
 2016-05-04 23:42:17 +10:00
Álvaro Felipe Melchor
149c7567ed improve arm/thumb detection for .so 2016-05-02 23:00:53 +02:00
pancake
1f7db90e41 Priorize keystone plugins and other random changes 2016-05-02 02:46:01 +02:00
pancake
b417da6d4d Add setarch/(from|to).string simplified RAsm APIs 2016-04-29 11:30:38 +02:00
Riccardo Schirone
26fc8f92ef libr: remove some unused variables and functions 2016-04-27 12:59:45 +02:00
pancake
bfc8e5318e More fixes from osx-ppc 2016-04-27 11:27:22 +02:00
pancake
e9dc4ae89e Fix #4695 - no prompt after r2 -qp 2016-04-26 19:11:11 +02:00
kolen
a65ea77725 Fix 'ed' opcode range resulted in overflow 
Should be:
40 41 .. 4a 4b
   maps to
00 01 .. 0a 0b

Was:
3a 3b 3c 3d 3e 3f 40 41 .. 4a 4b
            maps to
fa fb fc fd fe ff 00 01 .. 0a 0b
 2016-04-21 15:33:26 +02:00
Christoph Sarnowski
145688a60a Fix tricore disasm buffer copy function 
- Did not take `memaddr' argument into account, resulting in wrong disassembly.
- Check boundaries
 2016-04-15 15:51:28 +02:00
NaveenBoggarapu
4c04b98b47 few memory leaks fixed 2016-04-13 21:55:48 +02:00
Travis Goodspeed
3ca3b4f534 This patch fixes a bug in which many MSP430 instructions would be mistaken for emulated instructions. 2016-04-12 23:11:14 +02:00
pancake
5ef2b3cc0f Fix many warnings 2016-04-11 12:22:15 +02:00
Alexander Couzens
7c6ec5f146 fix mips forward assembler when using negative offset 
Fix 'Invalid reg name (-0x5c60)' when try to assemble
'lw t9, -0x5c60(gp)'
 2016-04-11 00:58:04 +02:00
pancake
4e0a71c0c3 Fix #4573 - fix oobread in java disassembler 2016-04-10 01:23:18 +02:00
pancake
3f7a70fb7d Fix #4564 - oobread in dalvik disasm+analyzer 2016-04-10 01:12:58 +02:00
pancake
6f4518a247 Fix #4588 - uninit memory in m68k dis 2016-04-10 01:06:16 +02:00
pancake
eb99ec8580 Fix android build 2016-04-07 16:20:29 +02:00
Anton Kochkov
d558dec5b7 Fix CID 1353073 2016-04-05 12:38:34 +03:00
pancake
62195cc005 Fix #4502 - Implement blx for thumb 2016-04-05 00:15:45 +02:00
Anders Kaare
cb2d45e491 fixing m68k branch disasm bug 
16bit displacement must be signed, but were unsigned. I've converted the
branch variants to 8/16/32bit signed casts rather than duplicating the
8bit ISBITSET() special case.
 2016-04-04 21:27:06 +02:00
pancake
e8263655be Fix more memleaks 2016-04-04 00:17:57 +02:00
pancake
9eb63df89f Fix #4502 - Implement blx address for arm32 assembler 2016-04-03 17:35:52 +02:00
Evan Shaw
58328def22 Show absolute offsets for relative branches in SNES disassembly 
This makes the disassembly easier to read.
 2016-04-02 10:02:27 +02:00
Anders Kaare
ff21bb5fbf fixing 6502 analysis 
36e42b33fe broke analysis by introducing a
new enum value. The analysis code didn't switch on the enum but rather
used it directly as an integer, so since the new SNES_OP_IMM has 5 as
its integer value the analysis code would think that the op was 5 bytes
in length.
 2016-03-30 22:08:52 +02:00
Léo Gaspard
353ff45443 Add EBC 'not' instruction decoding 2016-03-29 17:10:04 +02:00
Léo Gaspard
5c8a663e23 Identify external calls for EBC 2016-03-29 01:22:48 +02:00
Léo Gaspard
7595af19e3 Use decode_index32 for EBC calls 2016-03-29 01:22:48 +02:00
Léo Gaspard
ff4bce16db Actually follow UEFI spec for index{32,64} 2016-03-29 01:22:48 +02:00
pancake
d629165ec8 Remove unnecessary = NULL in bin/p/*.c 2016-03-27 23:02:29 +02:00
pancake
9d62ee0ddf Fix m68k.cs disassembler issue, honor asm.cpu in anal.m68k.cs 2016-03-24 16:21:49 +01:00
pancake
a461bbc536 Fix #4304 - asm.filter for m68k 2016-03-22 12:45:05 +01:00
pancake
76fa5bddcf Add missing signature 2016-03-18 17:19:06 +01:00
pancake
446add902f Fix #4345 - Add scas{bwd} for x86.nz 2016-03-18 16:59:47 +01:00
pancake
dc33b03011 Handle movk and movz in the arm64 assembler and pseudo disassembler 2016-03-17 17:26:08 +01:00
pancake
ae32acc5bc Add missing space after commas in m68k 2016-03-15 11:59:19 +01:00
pancake
1c443caccf Fix some COVs in snes disassembler 2016-03-13 21:04:12 +01:00
pancake
526d8d8e63 Fix #4275 - Fix lanai format string warnings 2016-03-13 03:23:54 +01:00
Evan Shaw
36e42b33fe Support 16-bit immediate operands in SNES 
Size for immediate operands depends on the value of the M flag
(for register A) or the X flag (for registers X and Y). A register is
8-bit when its respective flag is set and 16-bit when clear.

These flags can be set or unset independently, so this still isn't quite right
for when one flag is set and the other isn't, but it's an improvement. It's
possible to force a particular instruction to decode correctly by using the
`afh` command.
 2016-03-12 03:06:46 +01:00
oddcoder
966900121d adding bunch of another esil & fixing the bits 2016-03-09 15:32:50 +01:00
oddcoder
888b7d575d fixing bug in goto disassmebly 2016-03-09 12:21:56 +01:00
Álvaro Felipe Melchor
0efdf9cf97 Fix again #4215 2016-03-07 22:17:59 +01:00
pancake
d00beba767 Fix arm.cs thumb thing 2016-03-07 17:06:26 +01:00
pancake
75bf9b233a Fix aat->aap typo and add no-mclass option for x86.arm.cs 2016-03-07 12:31:50 +01:00
pancake
be9d53417e Fix #4215 - Fix disasm of thumb mrs 0, primask 2016-03-07 04:50:06 +01:00
pancake
650e99407b Oops. copypaste error in 6502dis 2016-03-07 04:44:42 +01:00
pancake
8de14dc2b6 Fix #4242 - OOB read in riscv disassembler 2016-03-07 00:21:49 +01:00
pancake
36ce331815 Fix #4239 - oobread in 6502 disassembler 2016-03-06 23:43:07 +01:00
oddcoder
9b21040898 fixing logic error in rcall instruction 
I just misread the operands of the rcall instruction
their is 2 similar types of instruction (naming conveintions used only
by me and mentioned no where in the manual) the N_T where the n operand
is 8 bit and NET_T where the n operand is 11 bit
the rcall looks like the following 1101 1nnn nnnn nnnn which is obviosly
NEX_T
 2016-03-05 19:54:31 +01:00
oddcoder
115c0bd40d fixing OSX Darwin compilation error #4218 2016-03-04 15:20:20 +01:00
oddcoder
599cbcd3c7 attempt to fix scan.converity bugs 
I also hunted 4th illegal memory read
the first 2 bytes of b is always casted to (ut16) type
with out checking if b even contains 2 bytes
now it is handled it correctly
 2016-03-04 00:50:25 +01:00
oddcoder
87b6ada97a Add asm.describe for pic18c 2016-03-03 03:18:03 +01:00
oddcoder
7fe6c6dff2 Adding initial support for PIC18C diassembler 2016-03-02 11:55:22 +01:00
mrdanielps
7fe1d56932 V810: fixes 
* Proper bound checking when decoding.
* Reuse some macros.
* Follow code style guidelines.
 2016-02-28 17:43:40 +01:00
Prasanna Balan
d9f4bce40b MSP430: add support for illegal opcodes 
Before this commit,any illegal opcode would return -1 which
would make r2 use 1 byte as default opcode width.This was
wrong on MSP430 as it uses fixed 2 byte opcodes.Fix this
 2016-02-25 02:58:38 +01:00
pancake
af2f02515f Support and load r_fs plugins 2016-02-21 02:32:28 +01:00
pancake
7c76d45ab7 Fix #4114 - Remove the use of setjmp in xtensa arch 2016-02-20 23:41:23 +01:00
William Robinet
a67adbcbb8 Typos 2016-02-17 13:38:43 +01:00
pancake
f52d3c114c Add missing signature for the lanai disassembler 2016-02-16 23:26:55 +01:00
William Robinet
d3ab5f38aa Remove execution bit from source files 2016-02-16 23:21:46 +01:00
William Robinet
0c7cacc2dc Fix typos 2016-02-16 23:21:24 +01:00
pancake
55eee73c6d Fix #4061 - properly assemble ldr.w thumb instruction 2016-02-16 17:12:37 +01:00
pancake
384cfb1042 Fix last coverities 2016-02-16 02:08:09 +01:00
mrdanielps
d6f49bc54e V810: Implement ESIL 2016-02-16 00:57:42 +01:00
pancake
ce7ca97cb6 Wip fixes for r_strbuf 2016-02-16 00:28:57 +01:00
pancake
fd359e9121 Implement radiff2 -D and optimize r_strbuf 2016-02-15 23:51:20 +01:00
pancake
cdf63617d7 Initial support for LANAI disassembler 2016-02-15 13:27:23 +01:00
pancake
838b254cc8 Fix #4090 - Do not assemble one-arg xors in x86.nz 2016-02-11 07:35:51 -06:00
mrdanielps
8ee43270e8 V810: Add opcode descriptions 2016-02-11 00:13:27 -06:00
evanrichter
7f43919750 add propeller architecture to asm.describe 
source: http://nagasm.org/ASL/Propeller/printedPDF/QuickReference-v15.pdf
 2016-02-10 17:21:08 -05:00
Jonathan Neuschäfer
91c940738c Add opcode descriptions for riscv 2016-02-03 11:29:32 +01:00
Jonathan Neuschäfer
edbb677a79 libr/asm/d/arm: Fix description of ORR opcode 2016-02-03 11:22:13 +01:00
condret
44b06b11de fix something 2016-02-01 14:10:09 +00:00
condret
b1d894ab7b fix some warning 2016-02-01 10:58:36 +00:00
condret
f66e7a4c46 fix #4012 2016-02-01 10:09:20 +00:00
pancake
bb073cf5db Modernize asm/code.c 2016-01-30 03:02:06 +01:00
pancake
b08892dbb3 Fix Tricore warnings and handle in ELF 2016-01-30 02:58:45 +01:00
Kitsu
73f2995d2e Added tms320 description 2016-01-30 02:50:41 +01:00
pancake
d7a244f010 Initial import of asm.tricore disassembler plugin 2016-01-30 02:47:17 +01:00
pancake
d30b2f4894 Initial import of the anal.xtensa plugin 2016-01-30 01:37:04 +01:00
Bigendian Smalls
6d1242c18d Added initial documentation for sysz architecture 
This will cover 99% of the commands implemented correctly/currently (via
capstone). However, since this doco is a complete list of mnemonics as
of 2016, it will cover all the instructions when a more complete
implementation of sysz is build for r2. Thanks to @mainframed for
parsing the original docs to create the raw instruction files.
 2016-01-29 00:02:48 +01:00
pancake
6f1655c491 Initial support for xtensa CPU disassmbler (from GNU binutils) 2016-01-28 23:59:50 +01:00
Kitsu
a1b872517a Added lm32 description 2016-01-28 23:17:12 +01:00