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3200e99109
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7914 Commits

Author SHA1 Message Date
Devang Patel
3200e99109 Remove dead code. 
llvm-svn: 83362
 2009-10-06 02:01:32 +00:00
Devang Patel
0141a90812 Add utility routine to set begin and end labels for DbgScopes. 
This will be used by processDebugLoc().

llvm-svn: 83361
 2009-10-06 01:50:42 +00:00
Devang Patel
2001f5878b Remove unintentional function decl. 
llvm-svn: 83356
 2009-10-06 01:31:35 +00:00
Devang Patel
ac511d1acf Add utility routine to collect variable debug info. This is not yet used. 
llvm-svn: 83355
 2009-10-06 01:26:37 +00:00
Devang Patel
6a7f2ee022 Set default location for the function if it is not already set. 
This code is not  yet enabled.

llvm-svn: 83349
 2009-10-06 00:09:08 +00:00
Devang Patel
3b3d8a9d09 Existence of a compile unit for input source file is a good indicator to check debug info's presence in a module. 
llvm-svn: 83348
 2009-10-06 00:03:14 +00:00
Devang Patel
f129b0d44f If subprogram die is not available then construct new one. 
This can happen if debug info is processed lazily.

llvm-svn: 83347
 2009-10-05 23:59:00 +00:00
Devang Patel
dff583ac49 Adjust context for the global variables that are not at file scope, e.g. 
void foo() { static int bar = 42; }
Here, foo's DIE is parent of bar's DIE.

llvm-svn: 83344
 2009-10-05 23:40:42 +00:00
Devang Patel
4e9591a170 Set address while constructing DIE. 
llvm-svn: 83343
 2009-10-05 23:22:08 +00:00
Jim Grosbach
d6da133b85 In Thumb1, the register scavenger is not always able to use an emergency 
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.

llvm-svn: 83336
 2009-10-05 22:30:23 +00:00
Devang Patel
28b7c6155c Gracefully handle various scopes while recording source line info. 
llvm-svn: 83317
 2009-10-05 18:03:19 +00:00
Chris Lattner
a3cf123e86 strength reduce a ton of type equality tests to check the typeid (Through 
the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297
 2009-10-05 05:54:46 +00:00
Chris Lattner
2c0a4fb325 stop MachineFunctionPass from claiming that it preserves LoopDependence info, 
which causes dependence info to be linked into lli.

llvm-svn: 83289
 2009-10-05 02:35:05 +00:00
Jakob Stoklund Olesen
61a76937ee Whitespace and formatting. 
llvm-svn: 83285
 2009-10-04 18:18:39 +00:00
Lang Hames
40530eacdb Oops. Renamed remaining MachineInstrIndex references. 
llvm-svn: 83255
 2009-10-03 04:31:31 +00:00
Lang Hames
f6903a7043 Renamed MachineInstrIndex to LiveIndex. 
llvm-svn: 83254
 2009-10-03 04:21:37 +00:00
Benjamin Kramer
aa33886dd7 Fix a use-after-free in post-ra-scheduling. 
MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.

llvm-svn: 83249
 2009-10-02 15:59:52 +00:00
David Goodwin
cb4a66977c All callee-saved registers are live-out of a return block. 
llvm-svn: 83223
 2009-10-01 23:28:47 +00:00
David Goodwin
a4b73e486e Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
llvm-svn: 83218
 2009-10-01 22:19:57 +00:00
David Goodwin
d0edce4c0d Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
llvm-svn: 83215
 2009-10-01 21:46:35 +00:00
Devang Patel
7aa19711f8 Add support to extract lexical scope information from DebugLoc attached with an machine instruction. 
This is not yet enabled.

llvm-svn: 83210
 2009-10-01 20:31:14 +00:00
David Goodwin
0a7770b3e0 Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup. 
llvm-svn: 83208
 2009-10-01 19:45:32 +00:00
Devang Patel
7b4ba71afa Record first and last instruction of a scope in DbgScope. 
llvm-svn: 83207
 2009-10-01 18:25:23 +00:00
Evan Cheng
68d79a17a0 Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change 
operands of instructions with these properties while breaking anti-dep.

llvm-svn: 83198
 2009-10-01 08:26:23 +00:00
Devang Patel
4f1147e386 Add another MDNode into DebugLocTuple. This will be used to keep track of inlined functions. 
llvm-svn: 83190
 2009-10-01 01:15:28 +00:00
Devang Patel
d24ba7a101 If location info is attached with an instruction then keep track of alloca slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables. 
llvm-svn: 83189
 2009-10-01 01:03:26 +00:00
Devang Patel
e097bf49d0 Use MachineInstr as an processDebugLoc() argument. 
This will allow processDebugLoc() to handle scopes for DWARF debug info. 

llvm-svn: 83183
 2009-09-30 23:12:50 +00:00
Devang Patel
044648c2d7 Use MDNode * directly as an RecordSourceLine() argument. 
llvm-svn: 83182
 2009-09-30 22:51:28 +00:00
Devang Patel
ef84ca6011 Remove dead code. 
llvm-svn: 83181
 2009-09-30 22:43:52 +00:00
Bob Wilson
1cf44c8225 Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this 
to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.

llvm-svn: 83176
 2009-09-30 22:06:26 +00:00
Bob Wilson
44b5a5a58c Fix a comment. 
llvm-svn: 83171
 2009-09-30 21:26:13 +00:00
Reid Kleckner
4c0732ea64 Silence comparison always false warning in -Asserts mode. 
llvm-svn: 83164
 2009-09-30 20:43:07 +00:00
Jim Grosbach
b4fdc9252d Add additional assert() to verify no extraneous use of a scavenged register. 
llvm-svn: 83163
 2009-09-30 20:35:36 +00:00
Reid Kleckner
ffe2b97d7a Fix integer overflow in instruction scheduling. This can happen if we have 
basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.

llvm-svn: 83159
 2009-09-30 20:15:38 +00:00
Evan Cheng
bb0561f2dd Add a target hook to add pre- post-regalloc scheduling passes. 
llvm-svn: 83144
 2009-09-30 08:49:50 +00:00
Jim Grosbach
d885068ad4 replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister() 
per customary usage

llvm-svn: 83137
 2009-09-30 01:47:59 +00:00
Jim Grosbach
5cc33f7dac fix compiler warning 
llvm-svn: 83132
 2009-09-30 00:37:40 +00:00
Devang Patel
0136a7ebec Simplify. 
llvm-svn: 83123
 2009-09-30 00:14:40 +00:00
David Goodwin
a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
llvm-svn: 83122
 2009-09-30 00:10:16 +00:00
Mike Stump
a3bce35a07 Add a way for a frontend to generate more complex dwarf location 
information.  This allows arbitrary code involving DW_OP_plus_uconst
and DW_OP_deref.  The scheme allows for easy extention to include,
any, or all of the DW_OP_ opcodes.  I thought about just exposing all
of them, but, wasn't sure if people wanted the dwarf opcodes exposed
in the api.  Is that a layering violation?

With this scheme, the entire existing block scheme used by llvm-gcc
can be switched over to the new scheme.  I think that would be
cleaner, as then the compiler specific bits are not present in llvm
proper.  Before the old code can be yanked however, similar code in
clang would have to be removed.

Next up, more testing.

llvm-svn: 83120
 2009-09-30 00:08:22 +00:00
Jim Grosbach
f759d3c1c5 Additional check for regno==0 
llvm-svn: 83103
 2009-09-29 20:11:10 +00:00
Devang Patel
5dcd8e1d86 Remove unnecessary cast. 
llvm-svn: 83100
 2009-09-29 19:56:13 +00:00
Devang Patel
e5be8e79df Remove std::string uses from DebugInfo interface. 
llvm-svn: 83083
 2009-09-29 18:40:58 +00:00
Jim Grosbach
0e6ac9047c Simplify the tracking of virtual frame index registers. Ranges cannot overlap, 
so a simple "current register" will suffice. Also add some additional
sanity-checking assertions to make sure things are as we expect.

llvm-svn: 83081
 2009-09-29 18:23:15 +00:00
Jim Grosbach
6f6bc51d3b Moving register scavenging to a post pass results in virtual registers in 
the instruction we're scavenging for. The scavenger needs to know to avoid
them when analyzing register usage.

llvm-svn: 83077
 2009-09-29 17:24:37 +00:00
Devang Patel
1070b7a713 s/class Metadata/class MetadataContext/g 
llvm-svn: 83019
 2009-09-28 21:41:20 +00:00
Devang Patel
d836a7d651 Do not use global typedef for MDKindID. 
llvm-svn: 83016
 2009-09-28 21:14:55 +00:00
Jakob Stoklund Olesen
5be0f6cfb4 Use KILL instead of IMPLICIT_DEF in LowerSubregs pass. 
llvm-svn: 83007
 2009-09-28 20:32:46 +00:00
Dan Gohman
ffa11ade11 Use VerifySchedule instead of doing the work manually. 
llvm-svn: 82995
 2009-09-28 16:09:41 +00:00
Evan Cheng
ddc8678b00 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.

llvm-svn: 82968
 2009-09-28 05:28:43 +00:00