Commit Graph

1368 Commits

Author SHA1 Message Date
Alkis Evlogimenos
8d8f872b3d Use correct template for SHLD and SHRD instructions so that the memory
operand size is correctly specified.

llvm-svn: 11997
2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
10f4523e9a Improve allocation order:
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996
2004-02-29 09:17:01 +00:00
Alkis Evlogimenos
7ecfe0a839 A big X86 instruction rename. The instructions are renamed to make
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
2004-02-29 08:50:03 +00:00
Brian Gaeke
8303cb575e Remove dead member variables of SparcV9SchedInfo and TargetSchedInfo
llvm-svn: 11994
2004-02-29 08:40:03 +00:00
Chris Lattner
a7db4ff17a Eliminate the X86-specific BMI functions, using BuildMI instead.
Replace uses of addZImm with addImm.

llvm-svn: 11992
2004-02-29 07:22:16 +00:00
Chris Lattner
e8e0bafbba Fix a miscompilation of 197.parser that occurs when you have single basic
block loops.

llvm-svn: 11990
2004-02-29 07:10:16 +00:00
Chris Lattner
c2977ac665 Adjust to change in TII ctor arguments
llvm-svn: 11987
2004-02-29 06:31:44 +00:00
Chris Lattner
b5f0e162c7 Eliminate the distinction between "real" and "unreal" instructions
llvm-svn: 11986
2004-02-29 06:31:16 +00:00
Chris Lattner
cfc8f02250 These two virtual methods are never called.
llvm-svn: 11984
2004-02-29 05:59:33 +00:00
Chris Lattner
dd752eec34 Remove a TON of flags that noone cares about
llvm-svn: 11983
2004-02-29 05:58:30 +00:00
Chris Lattner
d80ff1bdc0 Noone calls these virtual methods
llvm-svn: 11982
2004-02-29 05:58:16 +00:00
Chris Lattner
dded7ad224 This is the only file in the system that uses this enum. eliminate it.
llvm-svn: 11981
2004-02-29 05:57:59 +00:00
Chris Lattner
7cb71a20ca Implement initial prolog/epilog code insertion methods.
llvm-svn: 11979
2004-02-29 05:18:30 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands.
llvm-svn: 11974
2004-02-29 02:18:17 +00:00
Chris Lattner
800f720e7b Add an instruction selector capable of selecting 'ret void'
llvm-svn: 11973
2004-02-29 00:27:00 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
to denote this fact.

llvm-svn: 11972
2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to
denote this fact.

llvm-svn: 11971
2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
6038a89025 Uncomment instructions that take both an immediate and a memory
operand but their sizes differ.

llvm-svn: 11969
2004-02-28 22:06:59 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
2004-02-28 22:02:05 +00:00
Chris Lattner
3583890ab7 Change this so that LLC actually tries to run the code generator, though it will
immediately abort due to lack of an instruction selector. :)

llvm-svn: 11963
2004-02-28 20:21:45 +00:00
Chris Lattner
529a354ea4 SparcV8 now builds.
llvm-svn: 11960
2004-02-28 19:54:00 +00:00
Chris Lattner
5effdb67b7 fine grainify namespacification
llvm-svn: 11959
2004-02-28 19:53:18 +00:00
Chris Lattner
3852b0c3b8 Finegrainify namespacification
llvm-svn: 11958
2004-02-28 19:52:49 +00:00
Chris Lattner
88268605ec Tab completion is our friend.
llvm-svn: 11957
2004-02-28 19:45:39 +00:00
Chris Lattner
013aa47975 Clean up rules
llvm-svn: 11956
2004-02-28 19:43:40 +00:00
Chris Lattner
d2bb7e91b0 Bring this directory into "it actually compiles" land
llvm-svn: 11955
2004-02-28 19:37:18 +00:00
Chris Lattner
3f70429d28 Fix multiple inclusion problem
llvm-svn: 11954
2004-02-28 19:31:32 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates.
llvm-svn: 11933
2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments.
llvm-svn: 11932
2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
2004-02-28 02:56:26 +00:00
Brian Gaeke
6afa0813d2 Turn off the SparcV9MachineCodeDestructionPass for now, because it's buggy
llvm-svn: 11930
2004-02-27 21:15:40 +00:00
Brian Gaeke
0e74ff91a0 Correct DestroyMachineFunction's getPassName
llvm-svn: 11929
2004-02-27 21:01:14 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
instructions.

llvm-svn: 11923
2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d Fix encoding of ADD and SUB family of instructions. Also rearrange
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23 Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
llvm-svn: 11921
2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
5ac109957f Add memory operand folding support for the SETcc family of
instructions.

llvm-svn: 11907
2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9 Add memory operand folding support for SHLD and SHRD instructions.
llvm-svn: 11905
2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
llvm-svn: 11903
2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2 Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
2004-02-27 06:57:05 +00:00
John Criswell
0b01bff060 Fixes for PR258 and PR259.
Functions with linkonce linkage are declared with weak linkage.
Global floating point constants used to represent unprintable values
(such as NaN and infinity) are declared static so that they don't interfere
with other CBE generated translation units.

llvm-svn: 11884
2004-02-26 22:20:58 +00:00
Alkis Evlogimenos
b15631fcfa Uncomment assertions that register# != 0 on calls to
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.

llvm-svn: 11882
2004-02-26 22:00:20 +00:00
Chris Lattner
4aff6ec077 Use a map instead of annotations
llvm-svn: 11875
2004-02-26 08:02:17 +00:00
Chris Lattner
6a3796eaf9 Fix some warnings, some of which were spurious, and some of which were real
bugs.  Thanks Brian!

llvm-svn: 11859
2004-02-26 01:20:02 +00:00
Misha Brukman
3d1720cdb9 Instructions to call and return from functions.
llvm-svn: 11858
2004-02-26 00:37:12 +00:00
Misha Brukman
6a13621948 SparcV8 regs are really 32-bit, not 64! Thanks, Chris.
llvm-svn: 11835
2004-02-25 21:03:02 +00:00
Misha Brukman
f12c1e5a55 Clean up the tablegen descriptions for SparcV8.
llvm-svn: 11834
2004-02-25 21:02:21 +00:00
Misha Brukman
c8801eb5be Fix the SparcV8 register definitions that were imported from PPC template.
llvm-svn: 11833
2004-02-25 21:00:05 +00:00
Misha Brukman
a4b3e0f01b SparcV8 has different types of instructions, but F1 is only used for CALL.
llvm-svn: 11832
2004-02-25 20:52:20 +00:00