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550 Commits

Author SHA1 Message Date
Chris Lattner
50411d5be7 Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to: 
_test:
        lis r2, 743
        li r3, 0
        stw r3, 32751(r2)
        blr

instead of:

_test:
        li r2, 0
        stw r2, 32751(48693248)
        blr

Implement support for ppc64 as well, allowing it to produce better code.

llvm-svn: 34371
 2007-02-17 06:44:03 +00:00
Nate Begeman
dc46021355 Finish off bug 680, allowing targets to custom lower frame and return 
address nodes.

llvm-svn: 33636
 2007-01-29 22:58:52 +00:00
Anton Korobeynikov
611d5e2eda Propagate changes from my local tree. This patch includes: 
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.
llvm-svn: 33597
 2007-01-28 13:31:35 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
5ba049eabf setSetCCIsExpensive is gone. 
llvm-svn: 32941
 2007-01-05 23:42:53 +00:00
Jim Laskey
721e7d2129 Provide support for FP_TO_UINT. 
llvm-svn: 32599
 2006-12-15 14:32:57 +00:00
Chris Lattner
fb4898fdd8 Another step forward in PPC64 JIT support: we now no-longer need stubs 
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).

This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.

llvm-svn: 32451
 2006-12-11 23:22:45 +00:00
Jim Laskey
e2a261ad36 Missing opcode. 
llvm-svn: 32439
 2006-12-11 18:45:56 +00:00
Anton Korobeynikov
e76b69846d Cleaned setjmp/longjmp lowering interfaces. Now we're producing right 
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.

llvm-svn: 32415
 2006-12-10 23:12:42 +00:00
Chris Lattner
f5fd4be9dd Fix i64 uint_to_fp on ppc64 
llvm-svn: 32297
 2006-12-07 01:24:16 +00:00
Jim Laskey
1dcda902cd Restoration of the stack pointer after a deallocation of a alloca was not 
updating the SP link.

llvm-svn: 32202
 2006-12-04 22:04:42 +00:00
Jim Laskey
8f43fbf759 1. In ppc64 mode we need only use one GPR. 
2. Float values need to be promoted to double when they are vararg.

llvm-svn: 32074
 2006-12-01 16:30:47 +00:00
Chris Lattner
860908f98c Fix the CodeGen/PowerPC/vec_constants.ll regression. 
llvm-svn: 32057
 2006-12-01 01:45:39 +00:00
Chris Lattner
3219b522c8 Fix bug codegen'ing FP constant vectors with integer splats. Make sure the 
created intrinsics have the right integer types.  This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll

llvm-svn: 32024
 2006-11-29 19:58:49 +00:00
Jim Laskey
00bcb51943 Offset for load of 32-bit arg in 64-bit world was incorrect. 
llvm-svn: 32019
 2006-11-29 13:37:09 +00:00
Jim Laskey
7b0a74da3c Remove debug code. 
llvm-svn: 31970
 2006-11-28 18:27:02 +00:00
Jim Laskey
a5c5ceb212 32-bit int space was not accounted for properly in lowerCall. 
llvm-svn: 31966
 2006-11-28 14:53:52 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Chris Lattner
eb9b1840b3 on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots. 
Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840
 2006-11-18 01:57:19 +00:00
Chris Lattner
0d88b19f2f convert PPC::BCC to use the 'pred' operand instead of separate predicate 
value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835
 2006-11-17 22:37:34 +00:00
Chris Lattner
73329ae80d rename PPC::COND_BRANCH to PPC::BCC 
llvm-svn: 31834
 2006-11-17 22:14:47 +00:00
Chris Lattner
1527483a15 start using PPC predicates more consistently. 
llvm-svn: 31833
 2006-11-17 22:10:59 +00:00
Jim Laskey
8aac7dc0ee This is a general clean up of the PowerPC ABI. Address several problems and 
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792
 2006-11-16 22:43:37 +00:00
Chris Lattner
9bc55a6c38 fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri 
addrmodes.

llvm-svn: 31757
 2006-11-15 19:55:13 +00:00
Chris Lattner
e3a81b796c lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of 
'(shr (ctlz (sub Y, Z)), 5)'.

The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner.  For example, this:

typedef struct {
  unsigned prefix : 4;
  unsigned code : 4;
  unsigned unsigned_p : 4;
} tree_common;

int foo(tree_common *a, tree_common *b) {
  return a->code == b->code;
}

Now compiles to:

_foo:
        lwz r2, 0(r4)
        lwz r3, 0(r3)
        xor r2, r3, r2
        rlwinm r2, r2, 28, 28, 31
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

instead of:

_foo:
        lbz r2, 3(r4)
        lbz r3, 3(r3)
        srwi r2, r2, 4
        srwi r3, r3, 4
        subf r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

saving a cycle.

llvm-svn: 31725
 2006-11-14 05:28:08 +00:00
Chris Lattner
fdffc51d57 minor tweaks, reject vector preinc. 
llvm-svn: 31717
 2006-11-14 01:38:31 +00:00
Chris Lattner
9c5d395b0e ppc64 doesn't have lwau, don't attempt to form it. 
llvm-svn: 31656
 2006-11-11 00:08:42 +00:00
Chris Lattner
1aaa5f904c implement preinc support for r+i loads on ppc64 
llvm-svn: 31654
 2006-11-10 23:58:45 +00:00
Chris Lattner
1604b6a873 add an initial cut at preinc loads for ppc32. This is broken for ppc64 
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621
 2006-11-10 02:08:47 +00:00
Evan Cheng
d7df1a37bc PPC supports i32 / i64 pre-inc load / store. 
llvm-svn: 31599
 2006-11-09 19:11:50 +00:00
Evan Cheng
89ee587963 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
llvm-svn: 31595
 2006-11-09 17:55:04 +00:00
Chris Lattner
bd39c99fd1 Refactor all the addressing mode selection stuff into the isel lowering 
class, where it can be used for preinc formation.

llvm-svn: 31536
 2006-11-08 02:15:41 +00:00
Reid Spencer
4bafa71dc1 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
 2006-11-02 20:25:50 +00:00
Chris Lattner
38c04a6bd6 Implement the getRegForInlineAsmConstraint method for PPC. With recent 
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr

llvm-svn: 31367
 2006-11-02 01:44:04 +00:00
Chris Lattner
d9afd310a6 Change the prototype for TargetLowering::isOperandValidForConstraint 
llvm-svn: 31318
 2006-10-31 19:40:43 +00:00
Evan Cheng
5766dd6455 All targets expand BR_JT for now. 
llvm-svn: 31294
 2006-10-30 08:02:39 +00:00
Chris Lattner
0f686ec438 set the ppc64 stack pointer right, dynamic alloca now works for ppc64 
llvm-svn: 31028
 2006-10-18 01:20:43 +00:00
Chris Lattner
6c403f7102 Expand alloca for ppc64 
llvm-svn: 31027
 2006-10-18 01:18:48 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Evan Cheng
275825195a Make use of getStore(). 
llvm-svn: 30759
 2006-10-05 23:01:46 +00:00
Evan Cheng
494e8e6971 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
 2006-10-04 00:56:09 +00:00
Chris Lattner
3057944738 Legalize is no longer limited to cleverness with just constant shift amounts. 
Allow it to be clever when possible and fall back to the gross code when needed.

This allows us to compile:

long long foo1(long long X, int C) {
  return X << (C|32);
}
long long foo2(long long X, int C) {
  return X << (C&~32);
}

to:
_foo1:
        rlwinm r2, r5, 0, 27, 31
        slw r3, r4, r2
        li r4, 0
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        slw r3, r3, r2
        srw r5, r4, r5
        or r3, r3, r5
        slw r4, r4, r2
        blr

instead of:

_foo1:
        ori r2, r5, 32
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr

llvm-svn: 30507
 2006-09-20 03:47:40 +00:00
Chris Lattner
92c8924309 Fold the PPCISD shifts when presented with 0 inputs. This occurs for code 
like:
long long test(long long X, int Y) {
  return 1ULL << Y;
}
long long test2(long long X, int Y) {
  return -1LL << Y;
}

which we used to compile to:

_test:
        li r2, 1
        subfic r3, r5, 32
        li r4, 0
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r4, r5
        slw r6, r2, r6
        or r3, r4, r3
        slw r4, r2, r5
        or r3, r3, r6
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

Now we produce:

_test:
        li r2, 1
        addi r3, r5, -32
        subfic r4, r5, 32
        slw r3, r2, r3
        srw r4, r2, r4
        or r3, r4, r3
        slw r4, r2, r5
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

llvm-svn: 30479
 2006-09-19 05:22:59 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Reid Spencer
2567610703 For PR387: 
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.

llvm-svn: 29934
 2006-08-28 01:02:49 +00:00
Chris Lattner
c482a5d057 Fix a bug in a recent refactoring that broke a bunch of stuff. 
llvm-svn: 29649
 2006-08-12 07:20:05 +00:00
Chris Lattner
8ca6e82bce Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner
2f9c4426fc Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector. 
llvm-svn: 29609
 2006-08-11 17:18:05 +00:00
Chris Lattner
7e905fba17 Fix miscompilation of float vector returns. Compile code to this: 
_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
        blr

instead of:

_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
***     vor f1, v2, v2
        blr

llvm-svn: 29607
 2006-08-11 16:47:32 +00:00