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Author SHA1 Message Date
Andrew Trick
a1c4f73f87 Unit test for r146950: LSR postinc expansion, PR11571. 
llvm-svn: 146951
 2011-12-20 01:43:20 +00:00
Bob Wilson
8439df9506 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

llvm-svn: 146949
 2011-12-20 01:29:27 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Chris Lattner
c1d9c0a2a3 Now that PR11464 is fixed, reapply the patch to fix PR11464, 
merging types by name when we can.  We still don't guarantee type name linkage
but we do it when obviously the right thing to do.  This makes LTO type names 
easier to read, for example.

llvm-svn: 146932
 2011-12-20 00:12:26 +00:00
Chris Lattner
998998b3e7 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. 
llvm-svn: 146929
 2011-12-20 00:03:52 +00:00
Evan Cheng
9362ee62bc Move tests to FileCheck. 
llvm-svn: 146923
 2011-12-19 23:26:44 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Akira Hatanaka
7ef923c1f0 Add a test case for r146900. 
llvm-svn: 146901
 2011-12-19 20:24:28 +00:00
Akira Hatanaka
e54da3bfa2 Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
 2011-12-19 20:21:18 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Akira Hatanaka
804863071f Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
 2011-12-19 19:44:09 +00:00
Akira Hatanaka
b7ebcb2ded Remove the restriction on the first operand of the add node in SelectAddr. 
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888
 2011-12-19 19:28:37 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Joerg Sonnenberger
8cf8d64d19 Allow inlining of functions with returns_twice calls, if they have the 
attribute themselve.

llvm-svn: 146851
 2011-12-18 20:35:43 +00:00
Chad Rosier
b870a13cd8 Revert 146728 as it's causing failures on some of the external bots as well as 
internal nightly testers.  Original commit message:

By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.

llvm-svn: 146838
 2011-12-17 22:19:53 +00:00
Kevin Enderby
42fffe915a Revert r146822 at Pete Cooper's request as it broke clang self hosting. 
Hope I did this correctly :)

llvm-svn: 146834
 2011-12-17 19:48:52 +00:00
Pete Cooper
0ec73f6e98 SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. 
For example, 

if (a == b) {
    if (a > b) // this is false
    
Fixes some of the issues on <rdar://problem/10554090>

llvm-svn: 146822
 2011-12-17 06:32:38 +00:00
Manuel Klimek
09f4d148b8 Deleting the json-bench-test until I understand why it is flaky. 
llvm-svn: 146821
 2011-12-17 06:29:32 +00:00
Evan Cheng
23574ec02a Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
llvm-svn: 146805
 2011-12-17 01:25:34 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

llvm-svn: 146801
 2011-12-17 01:14:52 +00:00
Lang Hames
e32ef23ba8 Make sure that the lower bits on the VSELECT condition are properly set. 
llvm-svn: 146800
 2011-12-17 01:08:46 +00:00
Dan Gohman
9c8c9a8f62 The powers that be have decided that LLVM IR should now support 16-bit 
"half precision" floating-point with a first-class type.

This patch adds basic IR support (but not codegen support).

llvm-svn: 146786
 2011-12-17 00:04:22 +00:00
Eric Christopher
38b0b94ef2 When recursing for the original size of a type, stop if we are at a 
pointer or a reference type - we actually just want the size of the
pointer then for that.

Fixes rdar://10335756

llvm-svn: 146785
 2011-12-16 23:42:45 +00:00
Jakob Stoklund Olesen
445cdbb987 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

llvm-svn: 146767
 2011-12-16 23:00:05 +00:00
Benjamin Kramer
04d6a4c456 Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

llvm-svn: 146750
 2011-12-16 19:08:59 +00:00
Manuel Klimek
2f7cf4e64b Adds a JSON parser and a benchmark (json-bench) to catch performance regressions. 
llvm-svn: 146735
 2011-12-16 13:09:10 +00:00
Chris Lattner
26f06c927f By popular demand, link up types by name if they are isomorphic and one is an 
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.

llvm-svn: 146728
 2011-12-16 08:36:07 +00:00
Craig Topper
88e2bfef0a Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
llvm-svn: 146726
 2011-12-16 08:06:31 +00:00
Kostya Serebryany
c78b00cab4 [asan] add a test for instrumenting globals 
llvm-svn: 146718
 2011-12-16 01:28:19 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Lang Hames
d5cee672a7 Set specific target cpu for testcase. 
llvm-svn: 146678
 2011-12-15 20:22:34 +00:00
Lang Hames
0e361e816d Added test case for r146671. 
llvm-svn: 146675
 2011-12-15 19:56:07 +00:00
Hal Finkel
e8220d9927 Add a test case to make sure that the nop really does follow the bl on ppc64 elf 
llvm-svn: 146666
 2011-12-15 17:59:23 +00:00
Eli Friedman
09abc453ac Fix test. 
llvm-svn: 146642
 2011-12-15 04:52:47 +00:00
Eli Friedman
f6ae3a7caf Make constant folding for GEPs a bit more aggressive. 
llvm-svn: 146639
 2011-12-15 04:33:48 +00:00
Eli Friedman
71c0914b64 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. 
llvm-svn: 146630
 2011-12-15 02:07:20 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00
Pete Cooper
550b96ab46 Added InstCombine for "select cond, ~cond, x" type patterns 
These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624
 2011-12-15 00:56:45 +00:00
Eli Friedman
5dd57bb40a Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. 
llvm-svn: 146621
 2011-12-15 00:50:34 +00:00
Dan Gohman
1add31cc93 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and 
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610
 2011-12-14 23:49:11 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Devang Patel
0db1ed1a48 Do not sink instruction, if it is not profitable. 
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604
 2011-12-14 23:20:38 +00:00
Kevin Enderby
bc6d6388c2 Improve the implementation of .incbin directive by replacing a loop by using 
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!

llvm-svn: 146599
 2011-12-14 22:34:45 +00:00
Andrew Trick
9c88f32f94 LSR: Fold redundant bitcasts on-the-fly. 
llvm-svn: 146597
 2011-12-14 22:07:19 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Kevin Enderby
b0b669eb26 Add the .incbin directive which takes the binary data from a file and emits 
it to the streamer.  rdar://10383898

llvm-svn: 146592
 2011-12-14 21:47:48 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Stepan Dyatkovskiy
14cb78c6fb Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. 
llvm-svn: 146578
 2011-12-14 19:19:17 +00:00
Dan Gohman
e9572aa680 It turns out that clang does use pointer-to-function types to 
point to ARC-managed pointers sometimes. This fixes rdar://10551239.

llvm-svn: 146577
 2011-12-14 19:10:53 +00:00
Akira Hatanaka
3fca32d88e Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572
 2011-12-14 18:26:41 +00:00
Jim Grosbach
54372eef76 ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
 2011-12-14 17:30:24 +00:00
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive. 
rdar://10549683

llvm-svn: 146543
 2011-12-14 02:16:11 +00:00
Evan Cheng
68ba5536f3 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
 2011-12-14 02:11:42 +00:00
Chad Rosier
33f40b2c25 Add newline at EOF. 
llvm-svn: 146538
 2011-12-14 01:34:39 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants. 
rdar://10550269

llvm-svn: 146519
 2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc Test for 146516 
llvm-svn: 146517
 2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Chad Rosier
8af97606a9 [fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular 
load and then move the result from a GPR to a FPR.

llvm-svn: 146502
 2011-12-13 19:22:14 +00:00
Akira Hatanaka
23f439aca1 Add test/MC/Mips/dg.exp. 
llvm-svn: 146472
 2011-12-13 04:12:49 +00:00
Akira Hatanaka
a9290d5ab9 Move direct object emitter test to directory test/MC/Mips. Rename it to 
elf-relsym.ll.

llvm-svn: 146470
 2011-12-13 03:50:34 +00:00
Akira Hatanaka
28140f744a Relocation against a symbol, instead of against section. We had some extreme 
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.

Patch by Jack Carter.

llvm-svn: 146468
 2011-12-13 02:27:40 +00:00
Nick Lewycky
90a4c39a28 Don't rely on a particular version string for llvm. 
llvm-svn: 146456
 2011-12-13 00:34:14 +00:00
Tony Linthicum
da0dd81cf1 Temporarily disable Hexagon tests. They are failing on OS X 
llvm-svn: 146455
 2011-12-13 00:33:45 +00:00
Akira Hatanaka
46dd9e66a6 Test case for r146432 by Jack Carter. 
llvm-svn: 146433
 2011-12-12 22:41:39 +00:00
Bob Wilson
70f6f24d68 Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006> 
These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417
 2011-12-12 21:45:15 +00:00
Tony Linthicum
61adbf8dc5 Hexagon backend support 
llvm-svn: 146412
 2011-12-12 21:14:40 +00:00
Joerg Sonnenberger
5b25b4d437 Only replace fwrite with fputc, if the return value is unused. 
llvm-svn: 146411
 2011-12-12 20:18:31 +00:00
Jan Sjödin
b9e2da0d9a XOP instructions and encoding tests. 
llvm-svn: 146407
 2011-12-12 19:37:49 +00:00
Roman Divacky
a450b8b2c8 Add support for gnu_indirect_function. 
llvm-svn: 146377
 2011-12-12 17:34:04 +00:00
Chandler Carruth
2bedf185c9 Manually upgrade the test suite to specify the flag to cttz and ctlz. 
I followed three heuristics for deciding whether to set 'true' or
'false':

- Everything target independent got 'true' as that is the expected
  common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
  set the flag in the way that exercises the most of codegen. For most
  architectures this is also the likely path from a GCC builtin, with
  'true' being set. It will (eventually) require lowering away that
  difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
  operation should be tested.

Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.

llvm-svn: 146370
 2011-12-12 11:59:10 +00:00
Chandler Carruth
36be5dd1e8 Add an explicit test of the auto-upgrade functionality for the new 
intrinsic syntax.

Now that this is explicitly covered, I plan to upgrade the existing test
suite to use an explicit immediate. Note that I plan to specify 'true'
in most places rather than the auto-upgraded value as that is the far
more common value to end up here as that is the value coming from GCC's
builtins. The only place I'm likely to put a 'false' in is when testing
x86 which actually has different instructions for the two variants.

llvm-svn: 146369
 2011-12-12 11:23:11 +00:00
Chandler Carruth
d733f059d0 Teach the verifier to reject all non-constant arguments to the second 
argument of the cttz and ctlz intrinsics.

llvm-svn: 146360
 2011-12-12 04:36:02 +00:00
Stepan Dyatkovskiy
bf1423bdcd Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. 
llvm-svn: 146341
 2011-12-11 14:35:48 +00:00
Chandler Carruth
afb8199f38 Don't assume things about the exact details of the LLVM version number, 
such as what VCS information is attached.

llvm-svn: 146333
 2011-12-10 21:40:31 +00:00
Chad Rosier
fa74c25947 Revert associate SelectInsertValue test as well. 
llvm-svn: 146332
 2011-12-10 21:34:28 +00:00
Chad Rosier
d8a265c838 Revert r146322 to appease buildbots. Original commit message: 
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328
 2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy
5b2b42e8c9 Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. 
llvm-svn: 146322
 2011-12-10 08:42:24 +00:00
Hal Finkel
d591c94df7 Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. 
llvm-svn: 146318
 2011-12-10 04:50:53 +00:00
Rafael Espindola
9b9d35cc05 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
 2011-12-10 02:28:43 +00:00
Eli Friedman
ca06c3a2bd Splats can contain undef's; make sure to handle them correctly. PR11526. 
llvm-svn: 146299
 2011-12-09 23:54:42 +00:00
Jim Grosbach
356ad6d232 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
 2011-12-09 22:02:17 +00:00
Evan Cheng
77f0fb0296 Update test to something more sensible. 
llvm-svn: 146282
 2011-12-09 21:54:10 +00:00
Jim Grosbach
489e81da30 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Chad Rosier
7e0dc23863 [fast-isel] Add support for selecting insertvalue. 
rdar://10530851

llvm-svn: 146276
 2011-12-09 20:09:54 +00:00
Rafael Espindola
b5c511f7b7 Handle reloc_signed_4byte in here. Not doing so was a regression from my 
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

llvm-svn: 146273
 2011-12-09 19:57:29 +00:00
Kevin Enderby
63cf89d532 The second part of support for generating dwarf for assembly source files. This 
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.

The next part will be to get the clang driver to enable this when assembling
a .s file.  rdar://9275556

llvm-svn: 146262
 2011-12-09 18:09:40 +00:00
Benjamin Kramer
06cd66b1d7 X86: Add patterns for the various rounding ops for SSE4.1 and AVX. 
llvm-svn: 146257
 2011-12-09 15:44:03 +00:00
Andrew Trick
4f0b3bb42b Add -unroll-runtime for unrolling loops with run-time trip counts. 
Patch by Brendon Cahoon!

This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.

llvm-svn: 146245
 2011-12-09 06:19:40 +00:00
Evan Cheng
2c8bac6b4c Forgot setting -march. 
llvm-svn: 146244
 2011-12-09 06:15:00 +00:00
Rafael Espindola
82e22767cf Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a 
symbol difference. This matches gas behavior and fixes PR11513.

We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.

llvm-svn: 146238
 2011-12-09 03:03:58 +00:00
Akira Hatanaka
ce89ae9f84 jalr should use t9 ($25) for indirect calls regardless of the relocation model 
specified.

llvm-svn: 146229
 2011-12-09 01:45:12 +00:00
Eli Friedman
8f3db3867c Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514. 
llvm-svn: 146219
 2011-12-09 01:16:26 +00:00
Nick Lewycky
d2c1661e9f Fix infinite loop in DSE when deleting a free in a reachable loop that's also 
trivially infinite.

llvm-svn: 146197
 2011-12-08 22:36:35 +00:00
Evan Cheng
ad8debd736 Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417 
llvm-svn: 146196
 2011-12-08 22:30:45 +00:00
Jim Grosbach
62873cae5f ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88 ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Evan Cheng
d8a73b8918 Add various missing AVX patterns which was causing crashes. Sadly, the generated 
code looks pretty bad compared to SSE.

rdar://10538793

llvm-svn: 146191
 2011-12-08 22:05:28 +00:00
Jim Grosbach
af9cc198cf Tidy up a bit. 
llvm-svn: 146190
 2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642 ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf Tidy up a bit. 
llvm-svn: 146181
 2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Owen Anderson
d003a613e7 Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. 
llvm-svn: 146171
 2011-12-08 19:32:14 +00:00
Evan Cheng
0e0e920975 Add test for r146163. 
llvm-svn: 146167
 2011-12-08 19:21:39 +00:00
Daniel Dunbar
c192ce505d Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics 
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

llvm-svn: 146157
 2011-12-08 17:32:18 +00:00
NAKAMURA Takumi
671c1da473 test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 146152
 2011-12-08 15:24:09 +00:00
Nadav Rotem
341b30a457 Fix a bug in the integer-promotion of bitcast operations on vector types. 
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.

llvm-svn: 146150
 2011-12-08 13:10:01 +00:00
Stepan Dyatkovskiy
8fde5b6eb4 Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). 
llvm-svn: 146143
 2011-12-08 07:55:03 +00:00
Jim Grosbach
e1fe053f6e ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
7db0038ac0 32 to 64-bit zext pattern. 
llvm-svn: 146096
 2011-12-07 23:14:41 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Akira Hatanaka
b8e63b4c07 64-bit WrapperPICPat patterns. 
llvm-svn: 146086
 2011-12-07 22:11:43 +00:00
Akira Hatanaka
2b45547782 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Akira Hatanaka
19d6cd4d0e Fix 64-bit immediate patterns. 
llvm-svn: 146059
 2011-12-07 20:10:24 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
 2011-12-07 19:46:59 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory. 
llvm-svn: 146038
 2011-12-07 17:50:28 +00:00
Eli Friedman
9e8d557cd1 Support vector bitcasts in the AsmPrinter. PR11495. 
llvm-svn: 146001
 2011-12-07 00:50:54 +00:00
Eli Friedman
5545db0906 Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494. 
llvm-svn: 145996
 2011-12-07 00:11:56 +00:00
Hal Finkel
a76ada827b delaying restore-cr changed assigned registers in some tests 
llvm-svn: 145963
 2011-12-06 20:55:46 +00:00
Hal Finkel
7d78f1a8a4 add a test case that uses RESTORE_CR 
llvm-svn: 145962
 2011-12-06 20:55:41 +00:00
Justin Holewinski
c9457b712c PTX: Continue to fix up the register mess. 
llvm-svn: 145947
 2011-12-06 17:39:48 +00:00
Craig Topper
8b05e7d035 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
llvm-svn: 145927
 2011-12-06 09:04:59 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
 2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Craig Topper
72b41227d8 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
llvm-svn: 145921
 2011-12-06 04:59:07 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

llvm-svn: 145916
 2011-12-06 03:56:05 +00:00
Andrew Trick
04c98888bc LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.

llvm-svn: 145906
 2011-12-06 03:13:31 +00:00
Chad Rosier
70dd1f98af [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
af85f53dd0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Chad Rosier
7096fea51c Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

llvm-svn: 145879
 2011-12-06 00:19:08 +00:00
Chad Rosier
c50cbc5a65 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

llvm-svn: 145865
 2011-12-05 22:37:00 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Akira Hatanaka
bdefd49aa5 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
b119dd5891 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Hal Finkel
c8d6ce5e09 Add test case - this input used to crash because of duplicate generation of SPILL_CRs 
llvm-svn: 145820
 2011-12-05 17:55:22 +00:00
Hal Finkel
8b1e460cd9 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
llvm-svn: 145819
 2011-12-05 17:55:17 +00:00
Hal Finkel
68e102ed41 remove wasted space for extra bit copies of CR2 subregs 
llvm-svn: 145817
 2011-12-05 17:55:06 +00:00
NAKAMURA Takumi
c6a187dfdd test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 145805
 2011-12-05 07:54:57 +00:00
Nadav Rotem
1a91e4381d Add support for vectors of pointers. 
llvm-svn: 145801
 2011-12-05 06:29:09 +00:00
Anton Korobeynikov
e2277de6a7 Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
a942dee2b8 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.

llvm-svn: 145779
 2011-12-03 21:24:48 +00:00
Sanjoy Das
fe35e107cd Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.

llvm-svn: 145766
 2011-12-03 09:32:07 +00:00
Sanjoy Das
d1c3d82afe Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.

llvm-svn: 145765
 2011-12-03 09:21:07 +00:00
Chad Rosier
d1968c9ed6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Pete Cooper
32e376f7e1 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

llvm-svn: 145731
 2011-12-03 00:04:30 +00:00
Chad Rosier
d830d783e2 Add support for constant folding the pow intrinsic. 
rdar://10514247

llvm-svn: 145730
 2011-12-03 00:00:03 +00:00
Akira Hatanaka
16d404cca1 Test cases for 64-bit multiplication and division. 
llvm-svn: 145717
 2011-12-02 22:31:36 +00:00
Akira Hatanaka
8a6af7933c Fix test cases to use FileCheck. 
llvm-svn: 145716
 2011-12-02 22:28:09 +00:00
Jim Grosbach
6ae4df64e7 ARM tests for VLD1 single lane w/ writeback. 
llvm-svn: 145713
 2011-12-02 22:03:52 +00:00
Chad Rosier
b3b2871bbf [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Hal Finkel
a5b78f0e58 specify cpu for test to fix failure on some darwin systems with a g4+ cpu 
llvm-svn: 145699
 2011-12-02 19:38:17 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Craig Topper
d381116357 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
llvm-svn: 145680
 2011-12-02 07:16:01 +00:00
Hal Finkel
2984a1dfcb adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec. 
llvm-svn: 145678
 2011-12-02 04:58:12 +00:00
Chad Rosier
4d25975a28 Prevent library calls from being folded if -fno-builtin has been specified. 
rdar://10500969

llvm-svn: 145639
 2011-12-01 22:14:50 +00:00
Pete Cooper
c708e83499 Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment 
llvm-svn: 145618
 2011-12-01 19:13:26 +00:00
Eric Christopher
4aa8024569 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

llvm-svn: 145579
 2011-12-01 08:12:41 +00:00
Eli Friedman
ad916965a6 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
llvm-svn: 145573
 2011-12-01 04:49:21 +00:00
Pete Cooper
d4569610df Removed use of grep from test and moved it to be with other icmp tests 
llvm-svn: 145570
 2011-12-01 04:35:26 +00:00
Pete Cooper
7e03b7250d Added instcombine pattern to spot comparing -val or val against 0. 
(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>

llvm-svn: 145563
 2011-12-01 03:58:40 +00:00
Jan Sjödin
2dfb343ffa Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
 2011-11-30 22:09:42 +00:00
Eli Friedman
2d9e4aa665 Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment. 
<rdar://problem/10497732>.

llvm-svn: 145523
 2011-11-30 21:54:15 +00:00
Jim Grosbach
3129a92b38 Add some tests for all-lanes VLD1 parsing. 
llvm-svn: 145512
 2011-11-30 19:37:38 +00:00
Nadav Rotem
148d347bb7 Add test arch to make it pass on non x86 targets 
llvm-svn: 145498
 2011-11-30 17:34:28 +00:00
Nadav Rotem
bef49f31be Add a tripple to the test 
llvm-svn: 145489
 2011-11-30 11:20:56 +00:00
Nadav Rotem
f8e096f4ee X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). 
llvm-svn: 145488
 2011-11-30 10:13:37 +00:00
Andrew Trick
8da55f9048 Better test case found in duplicate PR10570. 
llvm-svn: 145484
 2011-11-30 06:26:42 +00:00
Andrew Trick
247f749767 LSR: handle the expansion of phi operands that use postinc forms of the IV. 
Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.

llvm-svn: 145482
 2011-11-30 06:07:54 +00:00
Chad Rosier
c5fa9f413a Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable 
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

llvm-svn: 145460
 2011-11-29 23:57:10 +00:00
Jakob Stoklund Olesen
f227c539d4 FileCheckize. 
llvm-svn: 145452
 2011-11-29 23:09:16 +00:00
Akira Hatanaka
fd548b69f5 Change names for MIPS "generic" processors defined in Mips.td to match what GNU 
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451
 2011-11-29 23:08:41 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Evan Cheng
5c1efd630b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
llvm-svn: 145448
 2011-11-29 22:48:34 +00:00
Jim Grosbach
fc7e76b194 Enable some VST1 tests and add a few more. 
llvm-svn: 145443
 2011-11-29 22:40:32 +00:00
Jakob Stoklund Olesen
5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
 2011-11-29 22:27:25 +00:00
Chad Rosier
0ff2f46d12 If fast-isel fails, remove dead instructions generated during the failed 
attempt.  

llvm-svn: 145425
 2011-11-29 19:40:47 +00:00