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4560 Commits

Author SHA1 Message Date
Eric Christopher
e02bd15dbc Clean up comment a bit. 
llvm-svn: 132083
 2011-05-25 21:19:19 +00:00
Eric Christopher
807da21e47 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939

llvm-svn: 132081
 2011-05-25 20:51:58 +00:00
Eli Friedman
2bdd096540 Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
llvm-svn: 132073
 2011-05-25 19:09:45 +00:00
Cameron Zwarich
5c410bd5f6 Restore an accidentally removed comment. 
llvm-svn: 132044
 2011-05-25 04:48:17 +00:00
Cameron Zwarich
4f47b296d8 Move some code to a more logical place. 
llvm-svn: 132043
 2011-05-25 04:45:29 +00:00
Cameron Zwarich
beae5f20e8 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

llvm-svn: 132042
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
5a32e53e3f Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041
 2011-05-25 04:45:23 +00:00
Cameron Zwarich
08753a605b Rename tBX_Rm to tBX. 
llvm-svn: 132040
 2011-05-25 04:45:20 +00:00
Cameron Zwarich
d9707488bb Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Bruno Cardoso Lopes
3a4aae57f4 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026
 2011-05-25 00:35:03 +00:00
Eric Christopher
4f193f9555 Implement the arm 'L' asm modifier. 
Part of rdar://9119939

llvm-svn: 132024
 2011-05-24 23:27:13 +00:00
Eric Christopher
a6d7ccb170 Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939

llvm-svn: 132023
 2011-05-24 23:15:43 +00:00
Eric Christopher
4783e5e316 Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.

llvm-svn: 132015
 2011-05-24 22:27:43 +00:00
Eric Christopher
03965fa3b6 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657

llvm-svn: 132011
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
5a416bda73 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

llvm-svn: 131894
 2011-05-23 01:57:17 +00:00
Renato Golin
759db3cbe3 RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
llvm-svn: 131868
 2011-05-22 21:41:23 +00:00
Johnny Chen
6e8aeaa2f4 Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.

llvm-svn: 131859
 2011-05-22 17:51:04 +00:00
Rafael Espindola
f114810ec8 adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
 2011-05-20 20:10:34 +00:00
Rafael Espindola
27dbdbdf4c fixes target address tBL and tBLX and sets relocation type 
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

llvm-svn: 131748
 2011-05-20 20:01:01 +00:00
Evan Cheng
9dbb570612 Revert accidental commit. 
llvm-svn: 131739
 2011-05-20 17:38:48 +00:00
Evan Cheng
a3f5204c82 Revert r131664 and fix it in instcombine instead. rdar://9467055 
llvm-svn: 131708
 2011-05-20 00:54:37 +00:00
Jason W Kim
93cb3f967d This fixes one divergence between LLVM and binutils for ARM in the 
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674
 2011-05-19 20:55:25 +00:00
Jim Grosbach
db1450056a 80 columns. 
llvm-svn: 131649
 2011-05-19 17:34:53 +00:00
Mon P Wang
9c138e7a7d Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
llvm-svn: 131630
 2011-05-19 04:15:07 +00:00
Cameron Zwarich
860c52b752 Reuse the TargetInstrDesc. 
llvm-svn: 131625
 2011-05-19 02:56:23 +00:00
Cameron Zwarich
eadbf0c427 Correctly constrain a register class when computing frame offsets, as the Thumb2 
add instruction takes an rGPR. This fixes the last of PR8825.

llvm-svn: 131619
 2011-05-19 02:18:27 +00:00
Tanya Lattner
6814933ea6 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.

llvm-svn: 131582
 2011-05-18 21:44:54 +00:00
Cameron Zwarich
f0b9f9d4c9 Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. 
llvm-svn: 131578
 2011-05-18 21:25:14 +00:00
Johnny Chen
3d6c5f4876 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
llvm-svn: 131565
 2011-05-18 20:32:41 +00:00
Evan Cheng
4787dc8f70 Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
llvm-svn: 131555
 2011-05-18 18:59:17 +00:00
Evan Cheng
ea3c2f0e60 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
llvm-svn: 131553
 2011-05-18 18:47:27 +00:00
Tanya Lattner
06cb9cbf98 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
b89a768a61 Fix typo. 
llvm-svn: 131519
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
b922060f98 Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

llvm-svn: 131518
 2011-05-18 02:20:07 +00:00
Cameron Zwarich
ed470705c0 Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* 
take r13, so we can just make it a GPR. This fixes PR8825.

llvm-svn: 131507
 2011-05-17 23:26:20 +00:00
Cameron Zwarich
15807bac51 Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They 
were marked as taking a tGPR when in reality they take an rGPR.

llvm-svn: 131506
 2011-05-17 23:11:12 +00:00
Tanya Lattner
7145d69427 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
llvm-svn: 131488
 2011-05-17 20:48:40 +00:00
Jim Grosbach
d7352e9b02 Kill some dead code. 
llvm-svn: 131431
 2011-05-16 22:24:07 +00:00
Rafael Espindola
e0b15205c1 sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

llvm-svn: 131406
 2011-05-16 16:17:21 +00:00
Owen Anderson
50766bc2f2 Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
llvm-svn: 131189
 2011-05-11 17:00:48 +00:00
Bill Wendling
453a924d29 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>

llvm-svn: 131174
 2011-05-11 01:11:55 +00:00
Jason W Kim
5b6e73e499 First cut at getting debugging support for ARM/MC/ELF/.o 
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data. 

llvm-svn: 131137
 2011-05-10 18:07:25 +00:00
Mon P Wang
08d3b69861 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
llvm-svn: 131085
 2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
4a57c64408 Eliminate the ARM sub-register indexes that are not needed by the sources. 
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

llvm-svn: 131059
 2011-05-07 21:22:42 +00:00
Eric Christopher
47f9c0695c Fix the non-MC encoding of pkhbt and pkhtb. 
Patch by Stephen Hines.

llvm-svn: 131045
 2011-05-07 04:37:27 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Rafael Espindola
59462d8ae3 Dead code elimination. 
llvm-svn: 130984
 2011-05-06 14:56:22 +00:00
Devang Patel
8823e24dde Do not emit location expression size twice. 
llvm-svn: 130854
 2011-05-04 19:00:57 +00:00
Jakob Stoklund Olesen
da28d31f03 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

llvm-svn: 130801
 2011-05-03 22:31:24 +00:00
Bob Wilson
7ca16f2c1f Temporarily disable use of divmod compiler-rt functions for iOS. 
llvm-svn: 130766
 2011-05-03 17:33:22 +00:00