4560 Commits

Author SHA1 Message Date
Johnny Chen
4c81015af7 Sanity check MSRi for invalid mask values and reject it as invalid.
rdar://problem/9246844

llvm-svn: 129050
2011-04-07 01:37:34 +00:00
Johnny Chen
1f028bb23e The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
2011-04-07 01:05:52 +00:00
Evan Cheng
859dff2c87 Change -arm-divmod-libcall to a target neutral option.
llvm-svn: 129045
2011-04-07 00:58:44 +00:00
Johnny Chen
523f8f38f7 Should also check SMLAD for invalid register values.
rdar://problem/9246650

llvm-svn: 129042
2011-04-07 00:50:25 +00:00
Owen Anderson
37b60bdf09 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
llvm-svn: 129038
2011-04-06 23:35:59 +00:00
Owen Anderson
7f766b61a1 Cleanups from Jim: remove redundant constraints and a dead FIXME.
llvm-svn: 129036
2011-04-06 22:45:55 +00:00
Jim Grosbach
0510dc2765 Tidy up.
llvm-svn: 129034
2011-04-06 22:35:47 +00:00
Johnny Chen
81aa7d84be A8.6.393
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
2011-04-06 22:14:48 +00:00
Johnny Chen
96fd9620c8 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Johnny Chen
765dec3867 Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
2011-04-06 01:18:32 +00:00
Owen Anderson
b59504a1a1 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
llvm-svn: 128965
2011-04-05 23:55:28 +00:00
Johnny Chen
48b39632aa Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Bob Wilson
89dce9ab06 Clean up some code for clarity.
llvm-svn: 128953
2011-04-05 23:03:25 +00:00
Owen Anderson
c8ceb7246f Revert r128946 while I figure out why it broke the buildbots.
llvm-svn: 128951
2011-04-05 23:03:06 +00:00
Johnny Chen
359b9a2331 A7.3 register encoding
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Owen Anderson
809f1a74d1 Give RSBS and RSCS the pseudo treatment.
llvm-svn: 128946
2011-04-05 22:42:54 +00:00
Johnny Chen
cf11408b65 ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
2011-04-05 21:49:44 +00:00
Owen Anderson
b73d1741c6 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
Johnny Chen
b50ab34083 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
2011-04-05 20:32:23 +00:00
Johnny Chen
4a15bdc1aa ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
Jim Grosbach
7bdaed671d Make second source operand of LDRD pre/post explicit.
Finish what r128736 started.

llvm-svn: 128903
2011-04-05 18:40:13 +00:00
Johnny Chen
d37098ae32 Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
2011-04-05 18:02:46 +00:00
Johnny Chen
626c0a35f6 Check for invalid register encodings for UMAAL and friends where:
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
2011-04-05 17:43:10 +00:00
Owen Anderson
b314020ff7 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
Bill Wendling
a8db395dc1 Revamp the SjLj "dispatch setup" intrinsic.
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>

llvm-svn: 128873
2011-04-05 01:37:43 +00:00
Eric Christopher
b04934036a Just use BL all the time. It's safer that way.
Fixes rdar://9184526

llvm-svn: 128869
2011-04-05 00:39:26 +00:00
Johnny Chen
785ab1531b Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

llvm-svn: 128864
2011-04-05 00:16:18 +00:00
Johnny Chen
92c33bafac A8.6.105 MUL
Inst{15-12} should be specified as 0b0000.

rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL

llvm-svn: 128862
2011-04-04 23:57:05 +00:00
Johnny Chen
eb8e7684b9 RFE encoding should also specify the "should be" encoding bits.
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.

llvm-svn: 128859
2011-04-04 23:39:08 +00:00
Johnny Chen
7fb247299a Fix incorrect alignment for NEON VST2b32_UPD.
rdar://problem/9225433

llvm-svn: 128841
2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
74363376e4 - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
2011-04-04 17:18:19 +00:00
Cameron Zwarich
9573b6277e Do some peephole optimizations to remove pointless VMOVs from Neon to integer
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

llvm-svn: 128759
2011-04-02 02:40:43 +00:00
Johnny Chen
dcd29e054c Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757
2011-04-02 02:24:54 +00:00
Johnny Chen
6f10cfdf01 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
rdar://problem/9224276

llvm-svn: 128749
2011-04-01 23:30:25 +00:00
Johnny Chen
b308662930 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
rdar://problem/9224120

llvm-svn: 128748
2011-04-01 23:15:50 +00:00
Johnny Chen
845caa871c Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746
2011-04-01 22:32:51 +00:00
Evan Cheng
4531994839 Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
Owen Anderson
48048d179c When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
llvm-svn: 128739
2011-04-01 21:07:39 +00:00
Jim Grosbach
039844acc5 LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
llvm-svn: 128736
2011-04-01 20:26:57 +00:00
Johnny Chen
65fe34ae00 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.

llvm-svn: 128734
2011-04-01 20:21:38 +00:00
Johnny Chen
17f1f7c322 Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
rdar://problem/9219356

llvm-svn: 128722
2011-04-01 18:26:38 +00:00
Benjamin Kramer
aff6a9e50a Initialize HasVMLxForwarding.
llvm-svn: 128709
2011-04-01 09:20:31 +00:00
Evan Cheng
39574b2766 Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
rdar://8911343

llvm-svn: 128696
2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
2520bb8022 Remove unused variables
llvm-svn: 128692
2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
d285a7f27e Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
5421130bfc Provide a legal pointer register class when targeting thumb1.
The LocalStackSlotAllocation pass was creating illegal registers.

llvm-svn: 128687
2011-03-31 23:02:15 +00:00
Evan Cheng
64850406cf Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

llvm-svn: 128665
2011-03-31 19:38:48 +00:00
Johnny Chen
2c5149791a Fix single word and unsigned byte data transfer instruction encodings so that
Inst{4} = 0.

rdar://problem/9213022

llvm-svn: 128662
2011-03-31 19:28:35 +00:00