176230 Commits

Author SHA1 Message Date
Matt Arsenault
ef9e376272 ARM: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356144
2019-03-14 13:46:14 +00:00
Matt Arsenault
fd11c30e7f AMDGPU: Don't add unnecessary convergent attributes
These are redundant with the intrinsic declaration.

llvm-svn: 356143
2019-03-14 13:46:09 +00:00
Hans Wennborg
9f89f54753 gn build: Merge r356080
llvm-svn: 356139
2019-03-14 12:22:50 +00:00
Simon Pilgrim
b87caf8a26 [SystemZ] Remove icmp undef
Prep-work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)

llvm-svn: 356138
2019-03-14 11:56:41 +00:00
Simon Pilgrim
ec1925ae75 [SystemZ] Regenerate tests to make complete codegen more obvious
llvm-svn: 356137
2019-03-14 11:54:46 +00:00
James Henderson
f563d45752 [llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.

This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.

Reviewed by: grimar, rupprecht, jakehehrlich

Differential Revision: https://reviews.llvm.org/D59293

This is a reland of r356129, attempting to fix greendragon failures
due to a suspected compatibility issue with od on the greendragon bots
versus other versions.

llvm-svn: 356136
2019-03-14 11:47:41 +00:00
Sam Parker
4a0b23b067 Fix for buildbots
Remove unused private field.

llvm-svn: 356135
2019-03-14 11:38:55 +00:00
James Henderson
88e40ab1b8 Revert r356129 due to greendragon bot failures
llvm-svn: 356133
2019-03-14 11:23:04 +00:00
Sam Parker
923be8eb23 [ARM][ParallelDSP] Enable multiple uses of loads
When choosing whether a pair of loads can be combined into a single
wide load, we check that the load only has a sext user and that sext
also only has one user. But this can prevent the transformation in
the cases when parallel macs use the same loaded data multiple times.
    
To enable this, we need to fix up any other uses after creating the
wide load: generating a trunc and a shift + trunc pair to recreate
the narrow values. We also need to keep a record of which loads have
already been widened.

Differential Revision: https://reviews.llvm.org/D59215

llvm-svn: 356132
2019-03-14 11:14:13 +00:00
Sam Parker
432549184c [NFC][LSR] Cleanup Cost API
Create members for Loop, ScalarEvolution, DominatorTree,
TargetTransformInfo and Formula.

Differential Revision: https://reviews.llvm.org/D58389

llvm-svn: 356131
2019-03-14 11:05:07 +00:00
Sam Parker
df3e0498f9 [ARM] Run ARMParallelDSP in the IRPasses phase
Run EarlyCSE before ParallelDSP and do this in the backend IR opt
phase.

Differential Revision: https://reviews.llvm.org/D59257

llvm-svn: 356130
2019-03-14 10:57:40 +00:00
James Henderson
1bd484c2b8 [llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.

This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.

Reviewed by: grimar, rupprecht, jakehehrlich

Differential Revision: https://reviews.llvm.org/D59293

llvm-svn: 356129
2019-03-14 10:20:27 +00:00
Hans Wennborg
8ed06c4dd6 gn build: Merge r356082
llvm-svn: 356128
2019-03-14 10:10:25 +00:00
Alex Bradbury
fcca23e948 [RISCV] Fix rL356123
The wrong version of the patch was committed. This fixes typos that broke the build.

llvm-svn: 356124
2019-03-14 08:31:35 +00:00
Alex Bradbury
d124e6db2b [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
The CSR renaming further prepares the way for an upcoming patch adding support for more
RISC-V ABIs.

Modify RISCVRegisterInfo::getCalleeSavedRegs and
RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>()
once rather than multiple times.

llvm-svn: 356123
2019-03-14 08:28:48 +00:00
Alex Bradbury
b2f7abd4ce [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Add a caller which exhausts regs then calls another function. This allows
getCalleePreservedRegs to be tested.

llvm-svn: 356122
2019-03-14 08:17:44 +00:00
Craig Topper
013902e369 [X86] Add patterns for rotr by immediate to fix PR41057.
Prior to the introduction of funnel shift intrinsics we could count on rotate
by immediates prefering to use rotl since that's what MatchRotate would check
first. The or+shift pattern doesn't have a direction so one must be chosen
arbitrarily.

With funnel shift, there is a direction and fshr will try to use rotr first.
While fshl will try to use rotl first.

This patch adds the isel patterns for rotr to complement the rotl patterns. I've
put the rotr by 1 patterns in the instruction patterns. And moved the rotl by
bitwidth-1 patterns to separate Pat patterns.

Fixes PR41057.

llvm-svn: 356121
2019-03-14 07:07:26 +00:00
Craig Topper
d760da6edd [X86] Add various test cases for PR41057. NFC
llvm-svn: 356120
2019-03-14 07:07:24 +00:00
Quentin Colombet
9785bf9323 [GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrs
getConstantVRegVal used to only look for G_CONSTANT when looking at
unboxing the value of a vreg. However, constants are sometimes not
directly used and are hidden behind trunc, s|zext or copy chain of
computation.

In particular this may be introduced by the legalization process that
doesn't want to simplify these patterns because it can lead to infine
loop when legalizing a constant.

To circumvent that problem, add a new variant of getConstantVRegVal,
named getConstantVRegValWithLookThrough, that allow to look through
extensions.

Differential Revision: https://reviews.llvm.org/D59227

llvm-svn: 356116
2019-03-14 01:37:13 +00:00
Douglas Yung
1bc7d43e99 Fixup tests to check for any MCInst number instead of a specific one.
llvm-svn: 356115
2019-03-14 01:24:35 +00:00
Craig Topper
3d9cbb9557 [ResetMachineFunctionPass] Add visited functions statistics info
Adding a "NumFunctionsVisited" for collecting the visited function number.
It can be used to collect function pass rate in some tests,
the pass rate = (NumberVisited - NumberReset)/NumberVisited.
e.g. it can be used for caculating GlobalISel pass rate in Test-Suite.

Patch by Tianyang Zhu (zhutianyang)

Differential Revision: https://reviews.llvm.org/D59285

llvm-svn: 356114
2019-03-14 01:13:15 +00:00
Craig Topper
67ed851d8a [X86] Add 64-bit mode command lines to rot32.ll so that it will demonstrate PR41055 for 32 bit. NFC
llvm-svn: 356112
2019-03-14 00:23:31 +00:00
Jordan Rupprecht
4047825f64 [llvm-objcopy][NFC] Remove unnecessary llvm-objcopy.h #includes
llvm-svn: 356109
2019-03-13 23:40:16 +00:00
Jessica Paquette
9a354720e0 [AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.

Also better code-reuse, etc., etc.

Differential Revision: https://reviews.llvm.org/D59323

llvm-svn: 356107
2019-03-13 23:29:54 +00:00
Jessica Paquette
4117eab6b5 [GlobalISel][AArch64] Gardening: Factor out vector inserts
Factor out the vector insert code in `selectBuildVector`. Replace part of it
with `emitScalarToVector`, since it was pretty much equivalent.

This will make implementing G_INSERT_VECTOR_ELT easier.

Differential Revision: https://reviews.llvm.org/D59322

llvm-svn: 356106
2019-03-13 23:22:23 +00:00
Jordan Rupprecht
bd637ddd64 [llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency
error() was previously cleaned up from CopyConfig, but new uses were introduced.

This also tweaks the error message for --add-symbol to report all invalid flags.

llvm-svn: 356105
2019-03-13 22:26:01 +00:00
Jason Liu
59e6264189 [AIX][CMake] Changes for building on AIX with XL and GCC
Summary:
In support of IBM's efforts to produce a viable C and C++ LLVM compiler for AIX
(ref: RFC at http://lists.llvm.org/pipermail/llvm-dev/2019-February/130175.html),
this patch adds customizations to the CMake files in order to properly
invoke the host toolchain for the build on AIX.
Additional changes to enable a successful build will follow.

Patch by Xing Xue

Reviewers: hubert.reinterpretcast, jasonliu, sfertile

Reviewed by: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D58250

llvm-svn: 356104
2019-03-13 21:50:25 +00:00
Sam Clegg
30ab5034f3 [WebAssembly] Improve support for "needed" list in dylink section
This change adds basic support for shared library dependencies
via the dylink section.

See https://github.com/WebAssembly/tool-conventions/pull/77

Differential Revision: https://reviews.llvm.org/D59237

llvm-svn: 356102
2019-03-13 21:29:20 +00:00
Jessica Paquette
fcc568af0c [GlobalISel][AArch64] Gardening: Factor out code to find lane indices
Some more refactoring for G_INSERT_VECTOR_ELT.

Factor out the code used to find a lane index from `selectExtractElt`. Put it
into a more general-purpose `getConstantValueForReg` function.

This will be shared with the code for G_INSERT_VECTOR_ELT.

Differential Revision: https://reviews.llvm.org/D59324

llvm-svn: 356101
2019-03-13 21:19:29 +00:00
Stanislav Mekhanoshin
0210f14ed7 [AMDGPU] Silence gcc 7 warnings
Differential Revision: https://reviews.llvm.org/D59330

llvm-svn: 356100
2019-03-13 21:15:52 +00:00
Matt Arsenault
edde3c0772 Verifier: Make sure masked load/store alignment is a power of 2
The same should also be done for scatter/gather, but the verifier
doesn't check those at all now.

llvm-svn: 356094
2019-03-13 19:46:34 +00:00
Matt Arsenault
4715acf963 PowerPC: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356093
2019-03-13 19:46:34 +00:00
Matt Arsenault
df1b94ab2b Hexagon: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356092
2019-03-13 19:46:33 +00:00
Matt Arsenault
e4cca33438 SystemZ: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

llvm-svn: 356091
2019-03-13 19:46:32 +00:00
Matt Arsenault
4fd9f27be3 Mips: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

I'm not sure what's going on with the immediates.ll test. It seems to
be intended to test invalid cases like this, but then tries to handle
some of them anyway. I've moved the cases that were inconsistent with
the GCCBuiltin definition so they don't test the codegen anymore.

llvm-svn: 356085
2019-03-13 19:07:59 +00:00
Simon Pilgrim
62e4fd4760 [X86] Remove icmp undef in more reduced tests
llvm-svn: 356084
2019-03-13 19:07:54 +00:00
Simon Pilgrim
68220b2059 [X86] Regenerate tail call tests
llvm-svn: 356083
2019-03-13 19:04:45 +00:00
Tim Renouf
c1e384ffaa [MsgPack] Removed MsgPackTypes
Summary:
MsgPackTypes has been replaced by the lighter-weight MsgPackDocument.

Differential Revision: https://reviews.llvm.org/D57025

Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4
llvm-svn: 356082
2019-03-13 18:56:33 +00:00
Tim Renouf
0740b7d5b8 [AMDGPU] Switched HSA metadata to use MsgPackDocument
Summary:
MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This
commit switches AMDGPU HSA metadata processing to use MsgPackDocument
instead of MsgPackTypes.

Differential Revision: https://reviews.llvm.org/D57024

Change-Id: I0751668013abe8c87db01db1170831a76079b3a6
llvm-svn: 356081
2019-03-13 18:55:50 +00:00
Tim Renouf
2600aff087 [MsgPack] New MsgPackDocument class
Summary:
A class that exposes a simple in-memory representation of a document of
MsgPack objects, that can be read from and written to MsgPack, read from
and written to YAML, and inspected and modified in memory. This is
intended to be a lighter-weight (in terms of memory allocations)
replacement for MsgPackTypes.

Two subsequent changes will:
1. switch AMDGPU HSA metadata to using MsgPackDocument instead of
   MsgPackTypes;
2. add MsgPack AMDGPU PAL metadata via MsgPackDocument.

Differential Revision: https://reviews.llvm.org/D57023

Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1
llvm-svn: 356080
2019-03-13 18:54:47 +00:00
Craig Topper
53b1ed4a97 [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.

We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.

I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.

Differential Revision: https://reviews.llvm.org/D59308

llvm-svn: 356078
2019-03-13 18:48:50 +00:00
Simon Pilgrim
062a2c49e3 [X86] Avoid icmp undef in reduced tests
Because we don't currently simplify icmp with undef in DAG, bugpoint loves to introduce them during reduction.

This is a small step towards re-adding non-undef values into some of the simpler tests so that they should still test correctly and emit similar/same codegen.

Prep work for PR40800 ([SelectionDAG] Add UNDEF handling to SelectionDAG::FoldSetCC).

llvm-svn: 356076
2019-03-13 18:36:59 +00:00
Alex Bradbury
c2d8f64443 [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to
reflect this, and remove the NOLIB check lines (they're redundant given that
the RV32I and RV64I check lines generated by update_llc_test_checks.py already
demonstrate there is no libcall).

llvm-svn: 356074
2019-03-13 18:25:23 +00:00
Simon Pilgrim
4c49e09099 Regenerate test
llvm-svn: 356071
2019-03-13 18:18:24 +00:00
Nirav Dave
3f1952d8de [DAGCombiner] Fix Comment. NFC.
llvm-svn: 356069
2019-03-13 17:44:40 +00:00
Nirav Dave
6655b5e078 [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.

Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.

CodeGen tests with non-reordering changes:

  X86/aligned-variadic.ll -- memory-based add folded into stored leaq
  value.

  X86/constant-combiners.ll -- Optimizes out overlap between stores.

  X86/pr40631_deadstore_elision -- folds constant byte store into
  preceding quad word constant store.

Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet

Reviewed By: courbet

Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59260

llvm-svn: 356068
2019-03-13 17:07:09 +00:00
Simon Pilgrim
268ff3b066 [X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode
llvm-svn: 356067
2019-03-13 17:00:18 +00:00
Simon Pilgrim
cbbfb5ea0e [X86][AVX] Add combineConcatVectors support to improve subvector handling
Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization.

This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time.

The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit.

llvm-svn: 356064
2019-03-13 16:37:30 +00:00
Alex Bradbury
a678d607a6 [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.

llvm-svn: 356063
2019-03-13 16:33:45 +00:00
Alex Bradbury
262a0524ce [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s
Note that s0 need not be marked reserved if the frame pointer isn't used. For
the ILP32 and LP64 soft float ABIS that are currently support, all FPRs are
always considered temporaries.

llvm-svn: 356061
2019-03-13 16:14:16 +00:00