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51 Commits

Author SHA1 Message Date
Akira Hatanaka f09378397e [MCInstPrinter] Enable MCInstPrinter to change its behavior based on the 
per-function subtarget.

Currently, code-gen passes the default or generic subtarget to the constructors
of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which
enables some targets (AArch64, ARM, and X86) to change their instprinter's
behavior based on the subtarget feature bits. Since the backend can now use
different subtargets for each function, instprinter has to be changed to use the
per-function subtarget rather than the default subtarget.

This patch takes the first step towards enabling instprinter to change its
behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to
AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the
various print methods table-gen auto-generates. 

I will follow up with changes to instprinters of AArch64, ARM, and X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233411 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-27 20:36:02 +00:00
Jozef Kolek db8552c834 [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226657 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 12:39:30 +00:00
Jozef Kolek 8832c6b91e Reverted revision 226577. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226595 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 19:29:28 +00:00
Jozef Kolek 617b574ffb [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226577 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 16:45:27 +00:00
Craig Topper 9bf73516cb Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-05 10:15:49 +00:00
Zoran Jovanovic 78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions 
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 14:59:10 +00:00
Zoran Jovanovic 7dc6143a82 [mips][microMIPS] Implement SWM16 and LWM16 instructions 
Differential Revision: http://reviews.llvm.org/D5579


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222901 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 18:28:59 +00:00
Zoran Jovanovic d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 16:44:02 +00:00
Zoran Jovanovic 61e341e0bf [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 
Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-27 14:58:51 +00:00
Chandler Carruth 42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE 
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 02:41:26 +00:00
Daniel Sanders 1df2ed27dd Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16. 
There's a couple additional bits I missed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205195 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 14:34:36 +00:00
Daniel Sanders 1200528f17 [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 14:30:05 +00:00
Chandler Carruth 1decd56b8d [cleanup] Re-sort all the includes with utils/sort_includes.py. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202811 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-04 10:07:28 +00:00
Petar Jovanovic 7f15e90281 [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions 
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200783 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-04 18:41:57 +00:00
Reed Kotler d194a4ae67 Distinguish and choose 16 or 32 bit forms of save/restore for Mips16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196999 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 03:32:44 +00:00
Reed Kotler c9ea75ee5b Cleaning up of prologue/epilogue code for Mips16. First step 
here is to make save/restore into variable number of argument instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196726 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-08 16:51:52 +00:00
Daniel Sanders c8a1fa77a7 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) 
Updated some of the vshf since they (correctly) emit splati's now



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 11:48:57 +00:00
Daniel Sanders 93d995719e [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 14:20:00 +00:00
Akira Hatanaka d65d2fde4e [mips] Place parentheses around && to silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190234 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:26:26 +00:00
Akira Hatanaka 1d04ca7987 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is 
equivalent to "beq $zero, $zero, offset".




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:40:15 +00:00
Akira Hatanaka d22b327b3d [micromips] Print instruction alias "not" if the last operand of a nor is zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188851 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-21 01:18:46 +00:00
Akira Hatanaka 014096e4d5 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' 
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:35:29 +00:00
Akira Hatanaka a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:20:40 +00:00
Akira Hatanaka 8838da6587 [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that 
turns "bal" into "bgezal".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 20:24:24 +00:00
Akira Hatanaka c0fa31d51b [mips] Add comment and simplify function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187371 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-29 19:08:34 +00:00
Akira Hatanaka 83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:13:47 +00:00
Akira Hatanaka d6a7ea2736 [mips] Delete register print method MipsInstPrinter::printCPURegs that is not 
needed. The generic method printOperand will do.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 18:50:42 +00:00
Akira Hatanaka 9b06dd6ca2 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo 
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 18:34:25 +00:00
Jack Carter 37ef65b9c1 This patch that sets the EmitAlias flag in td files 
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 08:32:10 +00:00
Jack Carter ec3199f675 This patch tackles the problem of parsing Mips 
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-12 01:03:14 +00:00
Akira Hatanaka f09a03776d [mips] Generate big GOT code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 20:40:38 +00:00
Akira Hatanaka b22c9289b0 Add HIGHER and HIGHEST relocations to Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160599 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-21 03:09:04 +00:00
Akira Hatanaka a7e4558ec8 Enclose instruction rdhwr with directives, which are needed when target is 
mips32 rev1 (the directives are emitted when target is mips32r2 too).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-05 19:26:38 +00:00
Benjamin Kramer c97ef618d2 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. 
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 08:32:38 +00:00
Craig Topper 7c0b3c1fb6 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:01:04 +00:00
Jia Liu bb481f8820 remove blanks, and some code format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 07:46:26 +00:00
Jia Liu c5707112e7 remove Emacs-tag form .cpp files in Mips Backend, and fix some typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 08:55:11 +00:00
Jia Liu 8f5e8c1cd6 add Emacs tag and fix some comment error in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 01:23:50 +00:00
Craig Topper bc2198133a Convert assert(0) to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 02:50:20 +00:00
Akira Hatanaka 8209968306 Tidy up. Simplify logic. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:52:25 +00:00
Akira Hatanaka 3faac0a78c Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 18:26:41 +00:00
Bruno Cardoso Lopes e3d3572e28 Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:28:57 +00:00
Akira Hatanaka d5cf5a631f Fix printing of MCSymbolRegExpr. Needs three closing parentheses for 
VK_Mips_GPOFF_HI/LO.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 03:58:36 +00:00
Bruno Cardoso Lopes ce1a538ab5 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-08 22:26:47 +00:00
Benjamin Kramer 5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 20:37:06 +00:00
Owen Anderson 519020adf1 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:58:45 +00:00
Owen Anderson 317eaf1993 In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 00:25:23 +00:00
Owen Anderson 98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Akira Hatanaka 404507e7d8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 00:13:35 +00:00
Benjamin Kramer 70629abe31 Silence compiler warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:18:13 +00:00