Commit Graph

2172 Commits

Author SHA1 Message Date
Scott Michel
1c7a81b0c5 CellSPU:
- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests
  accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 04:05:53 +00:00
Scott Michel
31aa1a1c83 CellSPU:
- Add an 8-bit operation test, which doesn't do much at this point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61665 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 01:35:22 +00:00
Scott Michel
ed741dde28 CellSPU:
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
  loads, test loops and LLVM loop/basic block optimizations; run the
  test harness successfully on real Cell hardware.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 01:34:35 +00:00
Dan Gohman
cc91d63ab7 Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61613 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-03 19:22:06 +00:00
Scott Michel
52d0001cfc CellSPU:
- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
  condition reversal and load/store folding. Updated BrCond test to reflect
  branch reversal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-03 00:27:53 +00:00
Evan Cheng
ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 05:35:45 +00:00
Evan Cheng
52ceafa5c7 Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61555 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 05:29:08 +00:00
Chris Lattner
aca3e68dd8 rename a file to follow naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61550 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 01:52:35 +00:00
Duncan Sands
5480c0469e Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-01 15:52:00 +00:00
Bill Wendling
587cbd0058 This is not failing on Darwin for some reason. XFAIL for other platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-31 19:26:09 +00:00
Scott Michel
477dc85052 XFAIL this for now until I can figure out what's going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61512 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-31 00:08:25 +00:00
Scott Michel
87142b1b0a Fix test erratum (which is wierd: works locally for me?)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61511 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-30 23:52:05 +00:00
Scott Michel
02d711b93e - Start moving target-dependent nodes that could be represented by an
instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-30 23:28:25 +00:00
Scott Michel
f0569be4a9 - Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-27 04:51:36 +00:00
Chris Lattner
1323e8bf6a add PR #
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61427 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-25 05:40:38 +00:00
Chris Lattner
e55484eb45 Add a simple pattern for matching 'bt'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61426 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-25 05:34:37 +00:00
Bill Wendling
e5b7e0ec08 Revert the changes in this testcase until Anton can fix them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61414 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-24 05:23:34 +00:00
Dan Gohman
82779704ff Fix a compiler-abort on a testcase where the stack-pointer is added to
a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61408 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-24 00:27:51 +00:00
Dale Johannesen
f9cbc1f9ac Add another permutation where we should get rid of a-a.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61401 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 23:01:27 +00:00
Anton Korobeynikov
42a8bbce2c Update test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61399 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 22:26:37 +00:00
Mon P Wang
2fe269def2 Added shuffle and splat test cases for r61365.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61366 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 04:05:08 +00:00
Dale Johannesen
58e39b0200 One more permutation of subtracting off a base value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23 01:59:54 +00:00
Dan Gohman
b12b1a27f5 Fix fast-isel to not emit invalid assembly when presented with a
constant shift count that doesn't fit in the shift instruction's
immediate field. This fixes PR3242.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61281 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-20 17:19:40 +00:00
Dan Gohman
f89e6e6577 Use the correct Preds and Succs lists in setHeightDirty()
and setDepthDirty(), respectively. This fixes PR3241.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61276 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-20 16:34:57 +00:00
Evan Cheng
5379f412bc Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this.
172     %ECX<def> = MOV32rr %reg1039<kill>
180     INLINEASM <es:subl $5,$1
        sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
188     %EAX<def> = MOV32rr %EAX<kill>
196     %ECX<def> = MOV32rr %ECX<kill>
204     %ECX<def> = MOV32rr %ECX<kill>
212     %EAX<def> = MOV32rr %EAX<kill>
220     %EAX<def> = MOV32rr %EAX
228     %reg1039<def> = MOV32rr %ECX<kill>

The early clobber operand ties ECX input to the ECX def.

The live interval of ECX is represented as this:
%reg20,inf = [46,47:1)[174,230:0)  0@174-(230) 1@46-(47)

The right way to represent this is something like
%reg20,inf = [46,47:2)[174,182:1)[181:230:0)  0@174-(182) 1@181-230 @2@46-(47)

Of course that won't work since that means overlapping live ranges defined by two val#.

The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61259 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19 20:58:01 +00:00
Evan Cheng
ab63152871 - CodeGenPrepare does not split loop back edges but it only knows about back edges of single block loops. It now does a DFS walk to find loop back edges.
- Use SplitBlockPredecessors to factor out common predecessors of the critical edge destination. This is disabled for now due to some regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61248 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19 18:03:11 +00:00
Rafael Espindola
2f6fea90a5 Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61242 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19 10:55:56 +00:00
Mon P Wang
7538454f9f Fix test to account for generating some vector code for mul v2i64 instead
of incorrectly generating pmuldq


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61228 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18 23:42:37 +00:00
Mon P Wang
1d045486ca Added some basic test cases for r61209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61210 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18 20:05:58 +00:00
Eli Friedman
28dc98f752 Fix for PR3225: disable a broken optimization in
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

In terms of restoring the optimization, the best fix here isn't 
obvious... any ideas?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61119 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-17 03:35:17 +00:00
Dale Johannesen
fd3b7b7df3 A new dag combine; several permutations of this
are there under ADD, this one was missing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 22:13:49 +00:00
Evan Cheng
09dc9c0c83 We have decided not to support inline asm where an output operand with a matching input operand with incompatible type (i.e. either one is a floating point and the other is an integer or the sizes of the types differ). SelectionDAGBuild will catch these and exit with an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61092 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 18:21:39 +00:00
Dan Gohman
812d7506d0 Enable anti-dependence breaking by default when post-RA scheduling is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61078 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 06:21:45 +00:00
Dan Gohman
3f23744df4 Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.

Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.

Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 03:25:46 +00:00
Mon P Wang
93b3b928d7 Added support for splitting and scalarizing vector shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61050 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-15 21:44:00 +00:00
Mon P Wang
d17c030276 Added support to LegalizeType for expanding the operands of scalar to vector
and insert vector element.  Modified extract vector element to extend the
result to match the expected promoted type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61029 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-15 06:57:02 +00:00
Bill Wendling
d350e02e19 - Use patterns instead of creating completely new instruction matching patterns,
which are identical to the original patterns.

- Change the multiply with overflow so that we distinguish between signed and
  unsigned multiplication. Currently, unsigned multiplication with overflow
  isn't working!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60963 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-12 21:15:41 +00:00
Bill Wendling
2476e5d345 If ADD, SUB, or MUL have an overflow bit that's used, don't do transformation on
them. The DAG combiner expects that nodes that are transformed have one value
result.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60857 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10 22:36:00 +00:00
Duncan Sands
ab0c578bfd For amusement, implement SADDO, SSUBO, UADDO, USUBO
for promoted integer types, eg: i16 on ppc-32, or
i24 on any platform.  Complete support for arbitrary
precision integers would require handling expanded
integer types, eg: i128, but I couldn't be bothered.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60834 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10 12:30:42 +00:00
Mon P Wang
bae527d949 Fixed a bug when trying to optimize a extract vector element of a
bit convert that changes the number of elements of a shuffle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10 03:59:02 +00:00
Bill Wendling
30a64a7649 Implement fast-isel conversion of a branch instruction that's branching on an
overflow/carry from the "arithmetic with overflow" intrinsics. It searches the
machine basic block from bottom to top to find the SETO/SETC instruction that is
its conditional. If an instruction modifies EFLAGS before it reaches the
SETO/SETC instruction, then it defaults to the normal instruction emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60807 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 23:19:12 +00:00
Bill Wendling
74c3765291 Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 22:08:41 +00:00
Duncan Sands
47d9dcc584 Fix PR3117: not all nodes being legalized. The
essential problem was that the DAG can contain
random unused nodes which were never analyzed.
When remapping a value of a node being processed,
such a node may become used and need to be analyzed;
however due to operands being transformed during
analysis the node may morph into a different one.
Users of the morphing node need to be updated, and
this wasn't happening.  While there I added a bunch
of documentation and sanity checks, so I (or some
other poor soul) won't have to scratch their head
over this stuff so long trying to remember how it
was all supposed to work next time some obscure
problem pops up!  The extra sanity checking exposed
a few places where invariants weren't being preserved,
so those are fixed too.  Since some of the sanity
checking is expensive, I added a flag to turn it
on.  It is also turned on when building with
ENABLE_EXPENSIVE_CHECKS=1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60797 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 21:33:20 +00:00
Scott Michel
db1b5bf5eb CellSPU:
- Fix call.ll and call_indirect.ll expected results, now that it's using a
  different pre-register allocation scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60741 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 06:12:03 +00:00
Mon P Wang
e9f1015d1f Fix getNode to allow a vector for the shift amount for shifts of vectors.
Fix the shift amount when unrolling a vector shift into scalar shifts.
Fix problem in getShuffleScalarElt where it assumes that the input of
a bit convert must be a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60740 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 05:46:39 +00:00
Dan Gohman
c8a1a3c426 Factor out the code for sign-extending/truncating gep indices
and use it in x86 address mode folding. Also, make
getRegForValue return 0 for illegal types even if it has a
ValueMap for them, because Argument values are put in the
ValueMap. This fixes PR3181.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 07:57:47 +00:00
Evan Cheng
c3ccc1aaaf Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60621 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-06 02:00:55 +00:00
Dale Johannesen
3b954815e1 Fix test to pass on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60614 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 22:38:21 +00:00
Dale Johannesen
203af58aea Make LoopStrengthReduce smarter about hoisting things out of
loops when they can be subsumed into addressing modes.

Change X86 addressing mode check to realize that
some PIC references need an extra register.
(I believe this is correct for Linux, if not, I'm sure
someone will tell me.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60608 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 21:47:27 +00:00
Evan Cheng
9b052cfe52 This test also requires -mattr=+sse41.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 19:26:37 +00:00