Commit Graph

110204 Commits

Author SHA1 Message Date
Rafael Espindola
d8e637eecf Pass the .ll files to llvm-link directly. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 20:35:59 +00:00
Sergey Dmitrouk
cd64acece2 Correct path to regression tests in ExtendingLLVM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 19:40:07 +00:00
Chad Rosier
6b3c567613 [AArch64] Fix clobber computation in A57LoadBalancing pass.
Extremely difficult to reproduce, so no test case included.
PR21637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:57:58 +00:00
Colin LeMahieu
5a6b6744c0 Removing unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:55:32 +00:00
Kostya Serebryany
678af17920 [asan/coverage] change the way asan coverage instrumentation is done: instead of setting the guard to 1 in the generated code, pass the pointer to guard to __sanitizer_cov and set it there. No user-visible functionality change expected
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:49:53 +00:00
Ulrich Weigand
edc6a13992 [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment
When processing an assignment in the integrated assembler that sets
a symbol to the value of another symbol, we need to copy the st_other
bits that encode the local entry point offset.

Modeled after MipsTargetELFStreamer::emitAssignment handling of the
ELF::STO_MIPS_MICROMIPS flag.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222672 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:09:47 +00:00
Paul Robinson
2dc4746332 More long path name support on Windows, this time in program execution.
Allows long paths for the executable and redirected stdin/stdout/stderr.
Addresses PR21563.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:05:29 +00:00
Colin LeMahieu
5de3458c18 [Hexagon] Adding asrh instruction, removing unused multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:04:42 +00:00
Colin LeMahieu
c1c7be0928 [Hexagon] Adding aslh instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 17:44:19 +00:00
Colin LeMahieu
f309d8ee65 [Hexagon] Adding zxth instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 17:11:34 +00:00
Colin LeMahieu
9f1b025b31 Adding const iterator to MCInst. http://reviews.llvm.org/D6359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:50:40 +00:00
Colin LeMahieu
a723df08bb [Hexagon] Adding zxtb instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:48:43 +00:00
David Majnemer
a17a9dc8df InstCombine: Don't create an unused instruction
We would create an instruction but not inserting it.
Not inserting the unused instruction would lead us to verification
failure.

This fixes PR21653.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:41:13 +00:00
Jozef Kolek
c19526770e [mips][microMIPS] Fix JRADDIUSP instruction
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:14:10 +00:00
Yaron Keren
de089dd0c6 Added comment about llvm_execute_on_thread waiting for thread to complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:51:41 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:39:13 +00:00
Jozef Kolek
d49e74eaa5 [mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0
Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:25:53 +00:00
Simon Atanasyan
39e9ec3049 [Mips] Update MIPS relocations list
No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:17:33 +00:00
Craig Topper
170c95ff76 Replace a comment that says 'unreachable' with llvm_unreachable in TableGen AsmWriter output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:09:52 +00:00
Aaron Ballman
8d6f6a27c7 Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:03:16 +00:00
Jozef Kolek
18700de8fc [mips][microMIPS] Implement disassembler support for 16-bit instructions
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 13:29:59 +00:00
Andrea Di Biagio
a1e1f01699 [X86] Improved target specific combine on VSELECT dag nodes.
This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.

Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 12:23:15 +00:00
David Majnemer
4a9d304d9d InstCombine: Don't assume DataLayout is always available
We tried to get the result of DataLayout::getLargestLegalIntTypeSize but
we didn't have a DataLayout.  This resulted in opt crashing.

This fixes PR21651.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 07:26:20 +00:00
Duncan P. N. Exon Smith
5deb1bf97f Support: Add *cast_or_null<> for pointer wrappers
Fill in omission of `cast_or_null<>` and `dyn_cast_or_null<>` for types
that wrap pointers (e.g., smart pointers).

Type traits need to be slightly stricter than for `cast<>` and
`dyn_cast<>` to resolve ambiguities with simple types.

There didn't seem to be any unit tests for pointer wrappers, so I tested
`isa<>`, `cast<>`, and `dyn_cast<>` while I was in there.

This only supports pointer wrappers with a conversion to `bool` to check
for null.  If in the future it's useful to support wrappers without such
a conversion, it should be a straightforward incremental step to use the
`simplify_type` machinery for the null check.  In that case, the unit
tests should be updated to remove the `operator bool()` from the
`pointer_wrappers::PTy`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 03:13:02 +00:00
Craig Topper
84d3252d1b Detect best type for some static index tables instead of just using uint32_t to reduce total data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222643 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 02:08:35 +00:00
Elena Demikhovsky
30f747478a Converted back to Unix format (after my last commit 222632)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 15:21:53 +00:00
Michael Kuperstein
d539147834 [X86] Fixes bug in build_vector v4x32 lowering
r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where:

1. A single extracted element is used twice.
2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask.

This caused a crash, since the source value for the insertps ends-up uninitialized.

Differential Revision: http://reviews.llvm.org/D6377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 13:09:06 +00:00
Craig Topper
71777d18ad Add missing override keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 09:40:13 +00:00
Craig Topper
e4d91ca81e Tablegen output formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222633 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 09:40:10 +00:00
Elena Demikhovsky
ae1ae2c3a1 Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 08:07:43 +00:00
Matt Arsenault
4f5aa5994e R600: Fix extloads of i1 on R600/Evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:54 +00:00
Matt Arsenault
716ce08250 R600: Fix assert on copy of an i1 on pre-SI
i1 is not a legal type on Evergreen, so this combine proceeded
and tried to produce a bitcast between i1 and i8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222630 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:52 +00:00
Matt Arsenault
2be9044ffc R600/SI: Add additional tests for i1 loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222629 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:50 +00:00
Matt Arsenault
5cd4913c8f R600/SI: Fix broken check lines and modernize prefixes
Use -LABEL and remove -CHECK

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:49 +00:00
Matt Arsenault
023311333a R600/SI: Fix missing -verify-machineinstrs on a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:47 +00:00
David Majnemer
369d8fa34f InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222625 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 20:00:41 +00:00
David Majnemer
89bcfdb956 InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 20:00:38 +00:00
David Majnemer
91349eecb0 InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222623 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 20:00:34 +00:00
Simon Pilgrim
53a43d38df Tidied up target triple OS detection. NFC
Use Triple::isOS*() helper functions where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 19:12:10 +00:00
Craig Topper
2b76e1afc5 Reduce size of some tables in tablegen register info output.
Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 18:30:18 +00:00
David Majnemer
218fe23f41 InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 18:16:54 +00:00
Chandler Carruth
e915b4b7c8 [x86] Teach the vector shuffle yet another step of canonicalization.
No functionality changed yet, but this will prevent subsequent patches
from having to handle permutations of various interleaved shuffle
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 09:18:53 +00:00
David Majnemer
8ff39c5c44 InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<Y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 08:57:02 +00:00
David Majnemer
082eff658e InstCombine: Propagate NSW for -X * -Y -> X * Y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 07:25:19 +00:00
David Majnemer
7eca618dfc InstSimplify: Simplify (sub 0, X) -> X if it's NUW
This is a generalization of the X - (0 - Y) -> X transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 07:15:16 +00:00
David Majnemer
1c4abdb6ab InstCombine: Silence a parenthesis warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 06:09:28 +00:00
Chandler Carruth
06a07dadb9 [x86] Add some tests for a common unpack pattern of vector shuffle that
has a remarkably unique and efficient lowering.

While we get this some of the time already, we miss a few cases and
there wasn't a principled reason we got it. We should at least test
this. v8 already has tests for this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 05:44:43 +00:00
David Majnemer
fc1c5babaf InstCombine: Preserve nsw when folding X*(2^C) -> X << C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 04:52:55 +00:00
David Majnemer
156d6ec86b InstCombine: Preserve nsw/nuw for ((X << C2)*C1) -> (X * (C1 << C2))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 04:52:52 +00:00
David Majnemer
0f8991742c InstCombine: Preserve nsw for (mul %V, -1) -> (sub 0, %V)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 04:52:38 +00:00