2006-09-13 00:46:09 +00:00
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2006-09-13 Alan Modra <amodra@bigpond.net.au>
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PR gas/3165
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* config/tc-sh (DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number
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in parens.
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2006-09-12 23:57:26 +00:00
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2006-09-13 Alan Modra <amodra@bigpond.net.au>
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* input-file.c (input_file_open): Replace as_perror with as_bad
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so that gas exits with error on file errors. Correct error
|
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message.
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(input_file_get, input_file_give_next_buffer): Likewise.
|
2006-09-13 00:00:40 +00:00
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* input-file.h: Update comment.
|
2006-09-12 23:57:26 +00:00
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2006-09-11 14:27:32 +00:00
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2006-09-11 Tomas Frydrych <dr.tomas@yahoo.co.uk>
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PR gas/3172
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* config/tc-arm.c (parse_typed_reg_or_scalar): Accept wCg class
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registers as a sub-class of wC registers.
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2006-09-11 02:32:50 +00:00
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2006-09-11 Alan Modra <amodra@bigpond.net.au>
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PR gas/3165
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* config/tc-mips.h (enum dwarf2_format): Forward declare.
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(DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number in parens.
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* config/tc-alpha.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
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* config/tc-arm.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
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|
2006-09-08 16:25:46 +00:00
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2006-09-08 Nick Clifton <nickc@redhat.com>
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PR gas/3129
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* doc/as.texinfo (Macro): Improve documentation about separating
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|
macro arguments from following text.
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|
2006-09-08 15:51:02 +00:00
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|
2006-09-08 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores.
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|
2006-09-07 17:54:15 +00:00
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|
2006-09-07 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (parse_operands): Mark operand as present.
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|
2006-09-05 14:07:22 +00:00
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|
2006-09-04 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
|
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|
|
(do_neon_dyadic_if_i_d): Avoid setting U bit.
|
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|
(do_neon_mac_maybe_scalar): Ditto.
|
|
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|
|
|
(do_neon_dyadic_narrow): Force operand type to NT_integer.
|
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|
|
(insns): Remove out of date comments.
|
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|
2006-08-29 15:19:43 +00:00
|
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|
|
2006-08-29 Nick Clifton <nickc@redhat.com>
|
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|
|
* read.c (s_align): Initialize the 'stopc' variable to prevent
|
|
|
|
|
|
compiler complaints about it being used without being
|
|
|
|
|
|
initialized.
|
|
|
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|
|
(s_comm_internal, s_mri_common, s_fail, s_globl, s_space,
|
|
|
|
|
|
s_float_space, s_struct, cons_worker, equals): Likewise.
|
|
|
|
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|
|
2006-08-29 01:31:56 +00:00
|
|
|
|
2006-08-29 Malcolm Parsons <malcolm.parsons@gmail.com>
|
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|
|
* ecoff.c (ecoff_directive_val): Fix message typo.
|
|
|
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|
|
* config/tc-ns32k.c (convert_iif): Likewise.
|
|
|
|
|
|
* config/tc-sh64.c (shmedia_check_limits): Likewise.
|
|
|
|
|
|
|
2006-08-25 19:59:31 +00:00
|
|
|
|
2006-08-25 Sterling Augustine <sterling@tensilica.com>
|
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|
|
|
|
Bob Wilson <bob.wilson@acm.org>
|
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|
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|
|
* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Do not check
|
|
|
|
|
|
the state of the absolute_literals directive. Remove align frag at
|
|
|
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|
|
the start of the literal pool position.
|
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|
2006-08-25 19:50:30 +00:00
|
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|
|
2006-08-25 Bob Wilson <bob.wilson@acm.org>
|
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|
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|
|
* doc/c-xtensa.texi: Add @group commands in examples.
|
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|
|
2006-08-25 00:08:55 +00:00
|
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|
|
2006-08-24 Bob Wilson <bob.wilson@acm.org>
|
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|
|
* config/tc-xtensa.c (FINI_LITERAL_SECTION_NAME): Delete.
|
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|
|
|
(INIT_LITERAL_SECTION_NAME): Delete.
|
|
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|
|
|
(lit_state struct): Remove segment names, init_lit_seg, and
|
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|
|
|
|
fini_lit_seg. Add lit_prefix and current_text_seg.
|
|
|
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|
|
(init_literal_head_h, init_literal_head): Delete.
|
|
|
|
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|
(fini_literal_head_h, fini_literal_head): Delete.
|
|
|
|
|
|
(xtensa_begin_directive): Move argument parsing to
|
|
|
|
|
|
xtensa_literal_prefix function.
|
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|
|
|
(xtensa_end_directive): Deallocate lit_prefix field of lit_state.
|
|
|
|
|
|
(xtensa_literal_prefix): Parse the directive argument here and
|
|
|
|
|
|
record it in the lit_prefix field. Remove code to derive literal
|
|
|
|
|
|
section names.
|
|
|
|
|
|
(linkonce_len): New.
|
|
|
|
|
|
(get_is_linkonce_section): Use linkonce_len. Check for any
|
|
|
|
|
|
".gnu.linkonce.*" section, not just text sections.
|
|
|
|
|
|
(md_begin): Remove initialization of deleted lit_state fields.
|
|
|
|
|
|
(xtensa_reorder_segments, xtensa_post_relax_hook): Remove references
|
|
|
|
|
|
to init_literal_head and fini_literal_head.
|
|
|
|
|
|
(xtensa_move_literals): Likewise. Skip literals for .init and .fini
|
|
|
|
|
|
when traversing literal_head list.
|
|
|
|
|
|
(match_section_group): New.
|
|
|
|
|
|
(cache_literal_section): Rewrite to determine the literal section
|
|
|
|
|
|
name on the fly, create the section and return it.
|
|
|
|
|
|
(xtensa_switch_to_literal_fragment): Adjust for cache_literal_section.
|
|
|
|
|
|
(xtensa_switch_to_non_abs_literal_fragment): Likewise.
|
|
|
|
|
|
(xtensa_create_property_segments, xtensa_create_xproperty_segments):
|
|
|
|
|
|
Use xtensa_get_property_section from bfd.
|
|
|
|
|
|
(retrieve_xtensa_section): Delete.
|
|
|
|
|
|
* doc/c-xtensa.texi (Xtensa Options): Fix --text-section-literals
|
|
|
|
|
|
description to refer to plural literal sections and add xref to
|
|
|
|
|
|
the Literal Directive section.
|
|
|
|
|
|
(Literal Directive): Describe new rules for deriving literal section
|
|
|
|
|
|
names. Add footnote for special case of .init/.fini with
|
|
|
|
|
|
--text-section-literals.
|
|
|
|
|
|
(Literal Prefix Directive): Replace old naming rules with xref to the
|
|
|
|
|
|
Literal Directive section.
|
|
|
|
|
|
|
2006-08-21 11:41:24 +00:00
|
|
|
|
2006-08-21 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (s_arm_unwind_save_mmxwr): Correct condition for
|
|
|
|
|
|
merging with previous long opcode.
|
|
|
|
|
|
|
2006-08-21 08:12:46 +00:00
|
|
|
|
2006-08-22 Pedro Alves <pedro_alves@portugalmail.pt>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARG_ENV_HFILES): Add te-wince-pe.h.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* config/tc-arm.h [TARGET_FORMAT]: ARM wince bfd names were
|
|
|
|
|
|
renamed. Adjust.
|
|
|
|
|
|
|
2006-08-16 10:33:50 +00:00
|
|
|
|
2006-08-16 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_assemble): Improve diagnostic when attempting
|
|
|
|
|
|
to use ARM instructions on non-ARM-supporting cores.
|
|
|
|
|
|
(autoselect_thumb_from_cpu_variant): New function. Switch on Thumb
|
|
|
|
|
|
mode automatically based on cpu variant.
|
|
|
|
|
|
(md_begin): Call above function.
|
|
|
|
|
|
|
2006-08-16 10:16:29 +00:00
|
|
|
|
2006-08-16 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (opcode_lookup): Allow Neon type suffixes to be
|
|
|
|
|
|
recognized in non-unified syntax mode.
|
|
|
|
|
|
|
2006-08-15 18:23:11 +00:00
|
|
|
|
2006-08-15 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Handle mips*-sde-elf*.
|
|
|
|
|
|
|
2006-08-12 23:00:35 +00:00
|
|
|
|
2006-08-12 Thiemo Seufer <ths@networkno.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips16_ip): Fix argument register handling
|
|
|
|
|
|
for restore instruction.
|
|
|
|
|
|
|
2006-08-08 19:09:34 +00:00
|
|
|
|
2006-08-08 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2dbg.c (DWARF2_USE_FIXED_ADVANCE_PC): New.
|
|
|
|
|
|
(out_sleb128): New.
|
|
|
|
|
|
(out_fixed_inc_line_addr): New.
|
|
|
|
|
|
(process_entries): Use out_fixed_inc_line_addr when
|
|
|
|
|
|
DWARF2_USE_FIXED_ADVANCE_PC is set.
|
|
|
|
|
|
* config/tc-xtensa.h (DWARF2_USE_FIXED_ADVANCE_PC): Define.
|
|
|
|
|
|
|
2006-08-08 17:21:04 +00:00
|
|
|
|
2006-08-08 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh.c (sh_frob_section): Canonicalize pointers to local
|
|
|
|
|
|
vs full symbols so that we never have more than one pointer value
|
|
|
|
|
|
for any given symbol in our symbol table.
|
|
|
|
|
|
|
2006-08-08 08:29:08 +00:00
|
|
|
|
2006-08-08 Sterling Augustine <sterling@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2dbg.c (out_debug_info): Add new parameter ranges_seg
|
|
|
|
|
|
and emit DW_AT_ranges when code in compilation unit is not
|
|
|
|
|
|
contiguous.
|
|
|
|
|
|
(out_debug_abbrev): Emit DW_AT_ranges abbreviation if code in
|
|
|
|
|
|
is not contiguous.
|
|
|
|
|
|
(dwarf2_finish): Create and pass ranges_seg to out_debug_info.
|
|
|
|
|
|
(out_debug_ranges): New function to emit .debug_ranges section
|
|
|
|
|
|
when code is not contiguous.
|
|
|
|
|
|
|
2006-08-08 08:23:25 +00:00
|
|
|
|
2006-08-08 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (WARN_DEPRECATED): Enable.
|
|
|
|
|
|
|
2006-08-06 15:04:23 +00:00
|
|
|
|
2006-08-05 Pedro Alves <pedro_alves@portugalmail.pt>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c: Move "dwarf2dbg.h" inclusion out of OBJ_ELF
|
|
|
|
|
|
only block.
|
|
|
|
|
|
(pe_directive_secrel) [TE_PE]: New function.
|
|
|
|
|
|
(md_pseudo_table) [!OBJ_ELF]: Handle 2byte, 4byte, 8byte, file,
|
|
|
|
|
|
loc, loc_mark_labels.
|
|
|
|
|
|
[TE_PE]: Handle secrel32.
|
|
|
|
|
|
(output_relax_insn): Remove OBJ_ELF around dwarf2_emit_insn
|
|
|
|
|
|
call.
|
|
|
|
|
|
(output_inst): Remove OBJ_ELF around dwarf2_emit_insn call.
|
|
|
|
|
|
(arm_frob_label): Remove OBJ_ELF around dwarf2_emit_label call.
|
|
|
|
|
|
(md_section_align): Only round section sizes here for AOUT
|
|
|
|
|
|
targets.
|
|
|
|
|
|
(tc_arm_regname_to_dw2regnum): Move out for OBJ_ELF only block.
|
|
|
|
|
|
(tc_pe_dwarf2_emit_offset): New function.
|
|
|
|
|
|
(md_apply_fix) [TE_PE]: Handle BFD_RELOC_32_SECREL.
|
|
|
|
|
|
(cons_fix_new_arm): Handle O_secrel.
|
|
|
|
|
|
* config/tc-arm.h : Move DWARF2_LINE_MIN_INSN_LENGTH,
|
|
|
|
|
|
DWARF2_DEFAULT_RETURN_COLUMN and DWARF2_CIE_DATA_ALIGNMENT out
|
|
|
|
|
|
of OBJ_ELF only block.
|
|
|
|
|
|
[TE_PE]: Define O_secrel, TC_DWARF2_EMIT_OFFSET, and declare
|
|
|
|
|
|
tc_pe_dwarf2_emit_offset.
|
|
|
|
|
|
|
bfd/
2006-08-02 Richard Sandiford <richard@codesourcery.com>
Kazu Hirata <kazu@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
* config.bfd (sh-*-vxworks): Use bfd_elf32_shvxworks_vec and
bfd_elf32_shlvxworks_vec.
* configure.in (bfd_elf32_sh64_vec): Add elf-vxworks.lo.
(bfd_elf32_sh64l_vec, bfd_elf32_sh64lin_vec): Likewise.
(bfd_elf32_sh64blin_vec, bfd_elf32_sh64lnbsd_vec): Likewise.
(bfd_elf32_sh64nbsd_vec, bfd_elf32_sh_vec): Likewise.
(bfd_elf32_shblin_vec, bfd_elf32_shl_vec): Likewise.
(bfd_elf32_shl_symbian_vec, bfd_elf32_shlin_vec): Likewise.
(bfd_elf32_shlnbsd_vec, bfd_elf32_shnbsd_vec): Likewise.
(bfd_elf32_shlvxworks_vec, bfd_elf32_shvxworks_vec): New stanzas.
* configure: Regenerate.
* Makefile.am: Regenerate dependencies.
* Makefile.in: Regenerate.
* elf-vxworks.c (elf_vxworks_gott_symbol_p): New function.
(elf_vxworks_add_symbol_hook): Use it.
(elf_vxworks_link_output_symbol_hook): Likewise. Use the hash
table entry to check for weak undefined symbols and to obtain
the original bfd.
(elf_vxworks_emit_relocs): Use target_index instead of this_idx.
* elf32-sh-relocs.h: New file, split from elf32-sh.c.
(R_SH_DIR32): Use SH_PARTIAL32 for the partial_inplace field,
SH_SRC_MASK32 for the src_mask field, and SH_ELF_RELOC for the
special_function field.
(R_SH_REL32): Use SH_PARTIAL32 and SH_SRC_MASK32 here too.
(R_SH_REL32, R_SH_TLS_GD_32, R_SH_TLS_LD_32): Likewise.
(R_SH_TLS_LDO_32, R_SH_TLS_IE_32, R_SH_TLS_LE_32): Likewise.
(R_SH_TLS_DTPMOD32, R_SH_TLS_DTPOFF32, R_SH_TLS_TPOFF32): Likewise.
(R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT): Likewise.
(R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Likewise.
(SH_PARTIAL32, SH_SRC_MASK32, SH_ELF_RELOC): Undefine at end of file.
* elf32-sh.c: Include elf32-vxworks.h.
(MINUS_ONE): Define.
(sh_elf_howto_table): Include elf32-sh-relocs.h with SH_PARTIAL32
set to TRUE, SH_SRC_MASK32 set to 0xffffffff, and SH_ELF_RELOC set
to sh_elf_reloc.
(sh_vxworks_howto_table): New variable. Include elf32-sh-relocs.h
with SH_PARTIAL32 set to FALSE, SH_SRC_MASK32 set to 0, and
SH_ELF_RELOC set to bfd_elf_generic_reloc.
(vxworks_object_p, get_howto_table): New functions.
(sh_elf_reloc_type_lookup): Fix typo. Use get_howto_table.
(sh_elf_info_to_howto): Use get_howto_table.
(sh_elf_relax_section): Honor the partial_inplace field of the
R_SH_DIR32 howto.
(sh_elf_relax_delete_bytes): Likewise.
(elf_sh_plt_info): New structure.
(PLT_ENTRY_SIZE): Replace both definitions with...
(ELF_PLT_ENTRY_SIZE): ...this new macro, with separate definitions for
INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_entry_be): Update sizes of both definitions accordingly.
(elf_sh_plt0_entry_le): Likewise.
(elf_sh_plt_entry_be, elf_sh_plt_entry_le): Likewise.
(elf_sh_pic_plt_entry_be, elf_sh_pic_plt_entry_le): Likewise.
(elf_sh_plts): New structure, with separate definitions for
INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_entry): Delete both definitions.
(elf_sh_plt_entry, elf_sh_pic_plt_entry): Likewise.
(elf_sh_sizeof_plt, elf_sh_plt_plt0_offset): Likewise.
(elf_sh_plt_temp_offset, elf_sh_plt_symbol_offset): Likewise.
(elf_sh_plt_reloc_offset): Likewise.
(movi_shori_putval): Delete in favor of...
(install_plt_field): ...this new function, with separate definitions
for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(get_plt_info): New function, with separate definitions
for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
(elf_sh_plt0_linker_offset, elf_sh_plt0_gotid_offset): Delete.
(VXWORKS_PLT_HEADER_SIZE, VXWORKS_PLT_ENTRY_SIZE): New macros.
(vxworks_sh_plt0_entry_be, vxworks_sh_plt0_entry_le): New constants.
(vxworks_sh_plt_entry_be, vxworks_sh_plt_entry_le): Likewise.
(vxworks_sh_pic_plt_entry_be, vxworks_sh_pic_plt_entry_le): Likewise.
(get_plt_index, get_plt_offset): New functions.
(elf_sh_link_hash_table): Add srelplt2, plt_info and vxworks_p fields.
(sh_elf_link_hash_table_create): Initialize them.
(sh_elf_create_dynamic_sections): Call
elf_vxworks_create_dynamic_sections for VxWorks.
(allocate_dynrelocs): Use htab->plt_info to get the size of PLT
entries. Allocate relocation entries in .rela.plt.unloaded if
generating a VxWorks executable.
(sh_elf_always_size_sections): New function.
(sh_elf_size_dynamic_sections): Extend .rela.plt handling to
.rela.plt.unloaded.
(sh_elf_relocate_section): Use get_howto_table. Honor
partial_inplace when calculating the addend for dynamic
relocations. Use get_plt_index.
(sh_elf_finish_dynamic_symbol): Use get_plt_index, install_plt_field
and htab->plt_info. Fill in the bra .plt offset for VxWorks
executables. Populate .rela.plt.unloaded. Do not make
_GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(sh_elf_finish_dynamic_sections): Use install_plt_field and
htab->plt_info. Handle cases where there is no special PLT header.
Populate the first relocation in .rela.plt.unloaded and fix up
the remaining entries.
(sh_elf_plt_sym_val): Use get_plt_info.
(elf_backend_always_size_sections): Define.
(TARGET_BIG_SYM, TARGET_BIG_NAME): Override for VxWorks.
(TARGET_LITTLE_SYM, TARGET_BIG_SYM): Likewise.
(elf32_bed, elf_backend_want_plt_sym): Likewise.
(elf_symbol_leading_char, elf_backend_want_got_underscore): Likewise.
(elf_backend_grok_prstatus, elf_backend_grok_psinfo): Likewise.
(elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing): Likewise.
(ELF_MAXPAGESIZE, ELF_COMMONPAGESIZE): Likewise.
* targets.c (bfd_elf32_shlvxworks_vec): Declare.
(bfd_elf32_shvxworks_vec): Likewise.
(_bfd_target_vector): Include bfd_elf32_shlvxworks_vec and
bfd_elf32_shvxworks_vec.
gas/
* config/tc-sh.c (apply_full_field_fix): New function.
(md_apply_fix): Use it instead of md_number_to_chars. Do not fill
in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.
ld/
2006-08-02 Richard Sandiford <richard@codesourcery.com>
Kazu Hirata <kazu@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
* Makefile.am (ALL_EMULATIONS): Add eshelf_vxworks.o and
eshlelf_vxworks.o.
(eshelf_vxworks.c, eshlelf_vxworks.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh-*-vxworks): Use shelf_vxworks and
shlelf_vxworks.
* emulparams/shelf_vxworks.sh: New file.
* emulparams/shlelf_vxworks.sh: Likewise.
* emulparams/vxworks.sh (FINI): Prefix _etext with ${SYMPREFIX}.
(OTHER_END_SYMBOLS): Likewise _ehdr.
(DATA_END_SYMBOLS): Likewise _edata.
* emultempl/vxworks.em (vxworks_after_open): Check whether output_bfd
is indeed an ELF file before dealing with --force-dynamic.
ld/testsuite/
* ld-sh/rd-sh.exp: Treat vxworks1-static.d specially.
* ld-sh/sh-vxworks.exp: New file.
* ld-sh/sh.exp: Extend sh-linux SIZEOF_HEADERS handling to
sh-*-vxworks.
* ld-sh/vxworks1-le.dd, ld-sh/vxworks1-lib-le.dd,
* ld-sh/vxworks1-lib.dd, ld-sh/vxworks1-lib.nd,
* ld-sh/vxworks1-lib.rd, ld-sh/vxworks1-lib.s,
* ld-sh/vxworks1-static.d, ld-sh/vxworks1.dd,
* ld-sh/vxworks1.ld, ld-sh/vxworks1.rd, ld-sh/vxworks1.s,
* ld-sh/vxworks2-static.sd, ld-sh/vxworks2.s,
* ld-sh/vxworks2.sd, ld-sh/vxworks3-le.dd,
* ld-sh/vxworks3-lib-le.dd, ld-sh/vxworks3-lib.dd,
* ld-sh/vxworks3-lib.s, ld-sh/vxworks3.dd, ld-sh/vxworks3.s,
* ld-sh/vxworks4.d, ld-sh/vxworks4a.s, ld-sh/vxworks4b.s,
* ld-sh/reloc1.s, ld-sh/reloc1.d: New tests.
2006-08-04 13:13:56 +00:00
|
|
|
|
2006-08-04 Richard Sandiford <richard@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh.c (apply_full_field_fix): New function.
|
|
|
|
|
|
(md_apply_fix): Use it instead of md_number_to_chars. Do not fill
|
|
|
|
|
|
in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
|
|
|
|
|
|
(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
|
|
|
|
|
|
* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.
|
|
|
|
|
|
|
2006-08-03 17:01:10 +00:00
|
|
|
|
2006-08-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2991
|
|
|
|
|
|
* config.in: Regenerate.
|
|
|
|
|
|
|
2006-08-03 15:59:00 +00:00
|
|
|
|
2006-08-03 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (parse_operands): Handle invalid register name
|
|
|
|
|
|
for OP_RIWR_RIWC.
|
|
|
|
|
|
|
2006-08-03 15:57:04 +00:00
|
|
|
|
2006-08-03 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
|
|
|
|
|
|
(parse_operands): Handle it.
|
|
|
|
|
|
(insns): Use it for tmcr and tmrc.
|
|
|
|
|
|
|
2006-08-02 16:25:14 +00:00
|
|
|
|
2006-08-02 Petr Salinger <Petr.Salinger@seznam.cz>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/2983
|
|
|
|
|
|
* config/tc-i386.c (md_parse_option): Treat any target starting
|
|
|
|
|
|
with elf64_x86_64 as a viable target for the -64 switch.
|
|
|
|
|
|
(i386_target_format): For 64-bit ELF flavoured output use
|
|
|
|
|
|
ELF_TARGET_FORMAT64.
|
|
|
|
|
|
* config/tc-i386.h (ELF_TARGET_FORMAT64): Define.
|
|
|
|
|
|
|
2006-08-02 14:26:07 +00:00
|
|
|
|
2006-08-02 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2991
|
|
|
|
|
|
* acinclude.m4 (BFD_BINARY_FOPEN): Import this function from
|
|
|
|
|
|
bfd/aclocal.m4.
|
|
|
|
|
|
* configure.in: Run BFD_BINARY_FOPEN.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* as.h: Look at USE_BINARY_FOPEN to decide which fopen-*.h header
|
|
|
|
|
|
file to include.
|
|
|
|
|
|
|
2006-08-01 17:54:28 +00:00
|
|
|
|
2006-08-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (md_assemble): Don't update
|
|
|
|
|
|
cpu_arch_isa_flags.
|
|
|
|
|
|
|
2006-08-01 07:58:22 +00:00
|
|
|
|
2006-08-01 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_section_align): Check ELF-ness at runtime.
|
|
|
|
|
|
|
2006-08-01 05:49:02 +00:00
|
|
|
|
2006-08-01 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro_build_lui): Fix comment formatting.
|
|
|
|
|
|
(md_apply_fix): Likewise. Unify handling of BFD_RELOC_RVA,
|
|
|
|
|
|
BFD_RELOC_32 and BFD_RELOC_16.
|
|
|
|
|
|
(s_align, s_cpload, s_cplocal, s_cprestore, s_mips_stab,
|
|
|
|
|
|
md_convert_frag, md_obj_end): Fix comment formatting.
|
|
|
|
|
|
|
2006-07-31 17:23:31 +00:00
|
|
|
|
2006-07-31 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_apply_fix, tc_gen_reloc): Remove special
|
|
|
|
|
|
handling for BFD_RELOC_MIPS16_JMP.
|
|
|
|
|
|
|
2006-07-24 16:30:55 +00:00
|
|
|
|
2006-07-24 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR/2756
|
|
|
|
|
|
* read.c (read_a_source_file): Ignore unknown text after line
|
|
|
|
|
|
comment character. Fix misleading comment.
|
|
|
|
|
|
|
2006-07-24 13:49:50 +00:00
|
|
|
|
2006-07-24 Ralk Wildenhues <Ralf.Wildenhues@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/all.texi, doc/as.texinfo, doc/c-arc.texi, doc/c-arm.texi,
|
|
|
|
|
|
doc/c-avr.texi, doc/c-bfin.texi, doc/c-i386.texi,
|
|
|
|
|
|
doc/c-i960.texi, doc/c-m32r.texi, doc/c-m68k.texi,
|
|
|
|
|
|
doc/c-mmix.texi, doc/c-pdp11.texi, doc/c-ppc.texi,
|
|
|
|
|
|
doc/c-tic54x.texi, doc/c-v850.texi, doc/c-xtensa.texi,
|
|
|
|
|
|
doc/c-z80.texi, doc/internals.texi: Fix some typos.
|
|
|
|
|
|
|
2006-07-21 09:46:15 +00:00
|
|
|
|
2006-07-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh.c (md_longopts): Add -EL and -EB for use by the
|
|
|
|
|
|
linker testsuite.
|
|
|
|
|
|
|
2006-07-20 16:51:38 +00:00
|
|
|
|
2006-07-20 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_parse_option): Don't infer optimisation
|
|
|
|
|
|
options from debug options.
|
|
|
|
|
|
|
2006-07-20 16:46:30 +00:00
|
|
|
|
2006-07-20 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
|
|
|
|
|
|
(tc_gen_reloc): Handle mips16 jumps to section symbol offsets.
|
|
|
|
|
|
|
2006-07-19 12:53:33 +00:00
|
|
|
|
2006-07-19 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (insns): Fix rbit Arm opcode.
|
|
|
|
|
|
|
2006-07-18 16:44:47 +00:00
|
|
|
|
2006-07-18 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
|
|
|
|
|
|
(md_convert_frag): Use correct reloc for add_pc. Use
|
|
|
|
|
|
BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
|
|
|
|
|
|
(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
|
|
|
|
|
|
(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
|
|
|
|
|
|
|
2006-07-17 12:49:50 +00:00
|
|
|
|
2006-07-17 Mat Hostetter <mat@lcs.mit.edu>
|
|
|
|
|
|
|
|
|
|
|
|
* symbols.c (report_op_error): Fix pasto. Don't use as_bad_where
|
|
|
|
|
|
when file and line unknown.
|
|
|
|
|
|
|
* read.c (s_struct): Use IS_ELF.
* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
s_mips_mask): Likewise.
2006-07-17 10:40:11 +00:00
|
|
|
|
2006-07-17 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (s_struct): Use IS_ELF.
|
|
|
|
|
|
* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
|
|
|
|
|
|
md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
|
|
|
|
|
|
tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
|
|
|
|
|
|
s_mips_mask): Likewise.
|
|
|
|
|
|
|
2006-07-16 10:19:19 +00:00
|
|
|
|
2006-07-16 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (s_struct): Handle ELF section changing.
|
|
|
|
|
|
* config/tc-mips.c (s_align): Leave enabling auto-align to the
|
|
|
|
|
|
generic code.
|
|
|
|
|
|
(s_change_sec): Try section changing only if we output ELF.
|
|
|
|
|
|
|
2006-07-15 16:32:48 +00:00
|
|
|
|
2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
|
|
|
|
|
|
CpuAmdFam10.
|
|
|
|
|
|
(smallest_imm_type): Remove Cpu086.
|
|
|
|
|
|
(i386_target_format): Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
|
|
|
|
|
|
Update CpuXXX.
|
|
|
|
|
|
|
2006-07-13 22:25:48 +00:00
|
|
|
|
2006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
|
|
|
|
|
|
Michael Meissner <michael.meissner@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
|
|
|
|
|
|
(CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add support for AmdFam10
|
|
|
|
|
|
architecture.
|
|
|
|
|
|
(i386_align_code): Ditto.
|
|
|
|
|
|
(md_assemble_code): Add support for insertq/extrq instructions,
|
|
|
|
|
|
swapping as needed for intel syntax.
|
|
|
|
|
|
(swap_imm_operands): New function to swap immediate operands.
|
|
|
|
|
|
(swap_operands): Deal with 4 operand instructions.
|
|
|
|
|
|
(build_modrm_byte): Add support for insertq instruction.
|
|
|
|
|
|
|
2006-07-13 18:13:36 +00:00
|
|
|
|
2006-07-13 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.h (Size64): Fix a typo in comment.
|
|
|
|
|
|
|
2006-07-12 09:02:00 +00:00
|
|
|
|
2006-07-12 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh.c (md_apply_fix): Do not allow the generic code in
|
2006-07-12 09:08:34 +00:00
|
|
|
|
fixup_segment() to repeat a range check on a value that has
|
2006-07-12 09:02:00 +00:00
|
|
|
|
already been checked here.
|
|
|
|
|
|
|
2006-07-07 23:17:55 +00:00
|
|
|
|
2006-07-07 James E Wilson <wilson@specifix.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_cpu_info_table): Add sb1a.
|
|
|
|
|
|
|
2006-07-06 10:34:02 +00:00
|
|
|
|
2006-07-06 Mohammed Adnène Trojette <adn@diwi.org>
|
|
|
|
|
|
Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/2877
|
|
|
|
|
|
* doc/as.texi: Fix spelling typo: branchs => branches.
|
|
|
|
|
|
* doc/c-m68hc11.texi: Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c: Likewise.
|
|
|
|
|
|
Support old spelling of command line switch for backwards
|
|
|
|
|
|
compatibility.
|
|
|
|
|
|
|
2006-07-04 17:22:11 +00:00
|
|
|
|
2006-07-04 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (s_is_linkonce): New function.
|
|
|
|
|
|
(mips16_mark_labels): Don't adjust mips16 symbol addresses for
|
|
|
|
|
|
weak, external, and linkonce symbols.
|
|
|
|
|
|
(pic_need_relax): Use s_is_linkonce.
|
|
|
|
|
|
|
2006-06-24 18:25:10 +00:00
|
|
|
|
2006-06-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Org): Remove space.
|
|
|
|
|
|
(P2align): Add "@var{abs-expr},".
|
|
|
|
|
|
|
gas/
2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch_tune_set): New.
(cpu_arch_isa): Likewise.
(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
nops with short or long nop sequences based on -march=/.arch
and -mtune=.
(set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
set cpu_arch_tune and cpu_arch_tune_flags.
(md_parse_option): For -march=, set cpu_arch_isa and set
cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
0. Set cpu_arch_tune_set to 1 for -mtune=.
(i386_target_format): Don't set cpu_arch_tune.
gas/testsuite/
2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686,
nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1,
x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom.
* gas/i386/nops-1.s: New file.
* gas/i386/nops-2.s: Likewise.
* gas/i386/nops-1-i386.d: Likewise.
* gas/i386/nops-1-i686.d: Likewise.
* gas/i386/nops-1-merom.d: Likewise.
* gas/i386/nops-1.d: Likewise.
* gas/i386/nops-2-i386.d: Likewise.
* gas/i386/nops-2-merom.d: Likewise.
* gas/i386/nops-2.d: Likewise.
* gas/i386/x86-64-nops-1.s: Likewise.
* gas/i386/x86-64-nops-1-k8.d: Likewise.
* gas/i386/x86-64-nops-1-merom.d: Likewise.
* gas/i386/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/x86-64-nops-1.d: Likewise.
* gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte
nop.
2006-06-23 21:47:36 +00:00
|
|
|
|
2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch_tune_set): New.
|
|
|
|
|
|
(cpu_arch_isa): Likewise.
|
|
|
|
|
|
(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
|
|
|
|
|
|
nops with short or long nop sequences based on -march=/.arch
|
|
|
|
|
|
and -mtune=.
|
|
|
|
|
|
(set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
|
|
|
|
|
|
set cpu_arch_tune and cpu_arch_tune_flags.
|
|
|
|
|
|
(md_parse_option): For -march=, set cpu_arch_isa and set
|
|
|
|
|
|
cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
|
|
|
|
|
|
0. Set cpu_arch_tune_set to 1 for -mtune=.
|
|
|
|
|
|
(i386_target_format): Don't set cpu_arch_tune.
|
|
|
|
|
|
|
2006-06-23 18:31:17 +00:00
|
|
|
|
2006-06-23 Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
|
|
|
|
|
|
generated .sbss.* and .gnu.linkonce.sb.*.
|
|
|
|
|
|
|
* config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
label_list.
* config/tc-mips.c (label_list): Define per-segment label_list.
(mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
mips_from_file_after_relocs, mips_define_label): Use per-segment
label_list.
2006-06-23 16:26:13 +00:00
|
|
|
|
2006-06-23 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
|
|
|
|
|
|
label_list.
|
|
|
|
|
|
* config/tc-mips.c (label_list): Define per-segment label_list.
|
|
|
|
|
|
(mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
|
|
|
|
|
|
append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
|
|
|
|
|
|
mips_from_file_after_relocs, mips_define_label): Use per-segment
|
|
|
|
|
|
label_list.
|
|
|
|
|
|
|
2006-06-22 14:09:40 +00:00
|
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|
|
2006-06-22 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
|
|
|
|
|
|
(append_insn): Use it.
|
|
|
|
|
|
(md_apply_fix): Whitespace formatting.
|
|
|
|
|
|
(md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
|
|
|
|
|
|
mips16_extended_frag): Remove register specifier.
|
|
|
|
|
|
(md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
|
|
|
|
|
|
constants.
|
|
|
|
|
|
|
2006-06-21 14:20:25 +00:00
|
|
|
|
2006-06-21 Mark Shinwell <shinwell@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
|
|
|
|
|
|
a directive saving VFP registers for ARMv6 or later.
|
|
|
|
|
|
(s_arm_unwind_save): Add parameter arch_v6 and call
|
|
|
|
|
|
s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
|
|
|
|
|
|
appropriate.
|
|
|
|
|
|
(md_pseudo_table): Add entry for new "vsave" directive.
|
|
|
|
|
|
* doc/c-arm.texi: Correct error in example for "save"
|
|
|
|
|
|
directive (fstmdf -> fstmdx). Also document "vsave" directive.
|
|
|
|
|
|
|
2006-06-21 15:24:40 +00:00
|
|
|
|
2006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
|
2006-06-19 16:58:29 +00:00
|
|
|
|
Anatoly Sokolov <aesok@post.ru>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
|
|
|
|
|
|
and atmega644p devices. Rename atmega164/atmega324 devices to
|
|
|
|
|
|
atmega164p/atmega324p.
|
|
|
|
|
|
* doc/c-avr.texi: Document new mcu and arch options.
|
|
|
|
|
|
|
2006-06-17 16:05:41 +00:00
|
|
|
|
2006-06-17 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (enum parse_operand_result): Move outside of
|
|
|
|
|
|
#ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
|
|
|
|
|
|
|
2006-06-16 15:46:11 +00:00
|
|
|
|
2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.h (processor_type): New.
|
|
|
|
|
|
(arch_entry): Add type.
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch_tune): New.
|
|
|
|
|
|
(cpu_arch_tune_flags): Likewise.
|
|
|
|
|
|
(cpu_arch_isa_flags): Likewise.
|
|
|
|
|
|
(cpu_arch): Updated.
|
|
|
|
|
|
(set_cpu_arch): Also update cpu_arch_isa_flags.
|
|
|
|
|
|
(md_assemble): Update cpu_arch_isa_flags.
|
|
|
|
|
|
(OPTION_MARCH): New.
|
|
|
|
|
|
(OPTION_MTUNE): Likewise.
|
|
|
|
|
|
(md_longopts): Add -march= and -mtune=.
|
|
|
|
|
|
(md_parse_option): Support -march= and -mtune=.
|
|
|
|
|
|
(md_show_usage): Add -march=CPU/-mtune=CPU.
|
|
|
|
|
|
(i386_target_format): Also update cpu_arch_isa_flags,
|
|
|
|
|
|
cpu_arch_tune and cpu_arch_tune_flags.
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo: Add -march=CPU/-mtune=CPU.
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
|
|
|
|
|
|
|
* include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}
to R_ARM_LDC_SB_G{0,1,2} respectively.
bfd/
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
gas/
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
ld/testsuite/
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
2006-06-15 11:03:02 +00:00
|
|
|
|
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (enum parse_operand_result): New.
|
|
|
|
|
|
(struct group_reloc_table_entry): New.
|
|
|
|
|
|
(enum group_reloc_type): New.
|
|
|
|
|
|
(group_reloc_table): New array.
|
|
|
|
|
|
(find_group_reloc_table_entry): New function.
|
|
|
|
|
|
(parse_shifter_operand_group_reloc): New function.
|
|
|
|
|
|
(parse_address_main): New function, incorporating code
|
|
|
|
|
|
from the old parse_address function. To be used via...
|
|
|
|
|
|
(parse_address): wrapper for parse_address_main; and
|
|
|
|
|
|
(parse_address_group_reloc): new function, likewise.
|
|
|
|
|
|
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
|
|
|
|
|
|
OP_ADDRGLDRS, OP_ADDRGLDC.
|
|
|
|
|
|
(parse_operands): Support for these new operand codes.
|
|
|
|
|
|
New macro po_misc_or_fail_no_backtrack.
|
|
|
|
|
|
(encode_arm_cp_address): Preserve group relocations.
|
|
|
|
|
|
(insns): Modify to use the above operand codes where group
|
|
|
|
|
|
relocations are permitted.
|
|
|
|
|
|
(md_apply_fix): Handle the group relocations
|
|
|
|
|
|
ALU_PC_G0_NC through LDC_SB_G2.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
(arm_force_relocation): Leave group relocations for the linker.
|
|
|
|
|
|
(arm_fix_adjustable): Likewise.
|
|
|
|
|
|
|
2006-06-15 10:51:28 +00:00
|
|
|
|
2006-06-15 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
|
|
|
|
|
|
(do_neon_ldr_str): Always defer to VFP encoding routines, which handle
|
|
|
|
|
|
relocs properly.
|
|
|
|
|
|
|
gas/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Don't add rex64 for
"xchg %rax,%rax".
gas/testsuite/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/opcode.s: Add "xchg %ax,%ax".
* gas/i386/opcode.d: Updated.
* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
* gas/i386/x86-64-opcode.d: Updated.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Update comment for 64bit NOP.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (NOP_Fixup): Removed.
(NOP_Fixup1): New.
(NOP_Fixup2): Likewise.
(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-12 18:55:44 +00:00
|
|
|
|
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (process_suffix): Don't add rex64 for
|
|
|
|
|
|
"xchg %rax,%rax".
|
|
|
|
|
|
|
2006-06-09 11:53:39 +00:00
|
|
|
|
2006-06-09 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ip): Maintain argument count.
|
|
|
|
|
|
|
2006-06-09 03:42:25 +00:00
|
|
|
|
2006-06-09 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-iq2000.c: Include sb.h.
|
|
|
|
|
|
|
2006-06-08 15:28:26 +00:00
|
|
|
|
2006-06-08 Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
|
|
|
|
|
|
aliases for better compatibility with SGI tools.
|
|
|
|
|
|
|
2006-06-08 05:09:37 +00:00
|
|
|
|
2006-06-08 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
|
|
|
|
|
|
* Makefile.am (GASLIBS): Expand @BFDLIB@.
|
|
|
|
|
|
(BFDVER_H): Delete.
|
|
|
|
|
|
(OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
|
|
|
|
|
|
(obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
|
|
|
|
|
|
(obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
|
|
|
|
|
|
Run "make dep-am".
|
|
|
|
|
|
* dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* doc/Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2006-06-07 15:38:01 +00:00
|
|
|
|
2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/Make-in (pdf, ps): New dummy targets.
|
|
|
|
|
|
|
* config/tc-arm.c (stdarg.h): include.
(arm_it): Add uncond_value field. Add isvec and issingle to operand
array.
(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
REG_TYPE_NSDQ (single, double or quad vector reg).
(reg_expected_msgs): Update.
(BAD_FPU): Add macro for unsupported FPU instruction error.
(parse_neon_type): Support 'd' as an alias for .f64.
(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
sets of registers.
(parse_vfp_reg_list): Don't update first arg on error.
(parse_neon_mov): Support extra syntax for VFP moves.
(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
(parse_operands): Support isvec, issingle operands fields, new parse
codes above.
(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
msr variants.
(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
(NEON_SHAPE_DEF): New macro. Define table of possible instruction
shapes.
(neon_shape): Redefine in terms of above.
(neon_shape_class): New enumeration, table of shape classes.
(neon_shape_el): New enumeration. One element of a shape.
(neon_shape_el_size): Register widths of above, where appropriate.
(neon_shape_info): New struct. Info for shape table.
(neon_shape_tab): New array.
(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
(neon_check_shape): Rewrite as...
(neon_select_shape): New function to classify instruction shapes,
driven by new table neon_shape_tab array.
(neon_quad): New function. Return 1 if shape should set Q flag in
instructions (or equivalent), 0 otherwise.
(type_chk_of_el_type): Support F64.
(el_type_of_type_chk): Likewise.
(neon_check_type): Add support for VFP type checking (VFP data
elements fill their containing registers).
(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
in thumb mode for VFP instructions.
(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
and encode the current instruction as if it were that opcode.
(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
arguments, call function in PFN.
(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
Redirect Neon-syntax VFP instructions to VFP instruction handlers.
(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
neon_quad.
(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
between VFP and Neon turns out to belong to Neon. Perform
architecture check and fill in condition field if appropriate.
(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
(do_neon_cvt): Add support for VFP variants of instructions.
(neon_cvt_flavour): Extend to cover VFP conversions.
(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
vmov variants.
(do_neon_ldr_str): Handle single-precision VFP load/store.
(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
NS_NULL not NS_IGNORE.
(opcode_tag): Add OT_csuffixF for operands which either take a
conditional suffix, or have 0xF in the condition field.
(md_assemble): Add support for OT_csuffixF.
(NCE): Replace macro with...
(NCE_tag, NCE, NCEF): New macros.
(nCE): Replace macro with...
(nCE_tag, nCE, nCEF): New macros.
(insns): Add support for VFP insns or VFP versions of insns msr,
mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
VFP/Neon insns together.
2006-06-07 14:32:28 +00:00
|
|
|
|
2006-06-07 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (stdarg.h): include.
|
|
|
|
|
|
(arm_it): Add uncond_value field. Add isvec and issingle to operand
|
|
|
|
|
|
array.
|
|
|
|
|
|
(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
|
|
|
|
|
|
REG_TYPE_NSDQ (single, double or quad vector reg).
|
|
|
|
|
|
(reg_expected_msgs): Update.
|
|
|
|
|
|
(BAD_FPU): Add macro for unsupported FPU instruction error.
|
|
|
|
|
|
(parse_neon_type): Support 'd' as an alias for .f64.
|
|
|
|
|
|
(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
|
|
|
|
|
|
sets of registers.
|
|
|
|
|
|
(parse_vfp_reg_list): Don't update first arg on error.
|
|
|
|
|
|
(parse_neon_mov): Support extra syntax for VFP moves.
|
|
|
|
|
|
(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
|
|
|
|
|
|
OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
|
|
|
|
|
|
(parse_operands): Support isvec, issingle operands fields, new parse
|
|
|
|
|
|
codes above.
|
|
|
|
|
|
(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
|
|
|
|
|
|
msr variants.
|
|
|
|
|
|
(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
|
|
|
|
|
|
(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
|
|
|
|
|
|
(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
|
|
|
|
|
|
(NEON_SHAPE_DEF): New macro. Define table of possible instruction
|
|
|
|
|
|
shapes.
|
|
|
|
|
|
(neon_shape): Redefine in terms of above.
|
|
|
|
|
|
(neon_shape_class): New enumeration, table of shape classes.
|
|
|
|
|
|
(neon_shape_el): New enumeration. One element of a shape.
|
|
|
|
|
|
(neon_shape_el_size): Register widths of above, where appropriate.
|
|
|
|
|
|
(neon_shape_info): New struct. Info for shape table.
|
|
|
|
|
|
(neon_shape_tab): New array.
|
|
|
|
|
|
(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
|
|
|
|
|
|
(neon_check_shape): Rewrite as...
|
|
|
|
|
|
(neon_select_shape): New function to classify instruction shapes,
|
|
|
|
|
|
driven by new table neon_shape_tab array.
|
|
|
|
|
|
(neon_quad): New function. Return 1 if shape should set Q flag in
|
|
|
|
|
|
instructions (or equivalent), 0 otherwise.
|
|
|
|
|
|
(type_chk_of_el_type): Support F64.
|
|
|
|
|
|
(el_type_of_type_chk): Likewise.
|
|
|
|
|
|
(neon_check_type): Add support for VFP type checking (VFP data
|
|
|
|
|
|
elements fill their containing registers).
|
|
|
|
|
|
(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
|
|
|
|
|
|
in thumb mode for VFP instructions.
|
|
|
|
|
|
(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
|
|
|
|
|
|
and encode the current instruction as if it were that opcode.
|
|
|
|
|
|
(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
|
|
|
|
|
|
arguments, call function in PFN.
|
|
|
|
|
|
(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
|
|
|
|
|
|
(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
|
|
|
|
|
|
(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
|
|
|
|
|
|
(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
|
|
|
|
|
|
(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
|
|
|
|
|
|
Redirect Neon-syntax VFP instructions to VFP instruction handlers.
|
|
|
|
|
|
(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
|
|
|
|
|
|
(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
|
|
|
|
|
|
(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
|
|
|
|
|
|
(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
|
|
|
|
|
|
(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
|
|
|
|
|
|
(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
|
|
|
|
|
|
(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
|
|
|
|
|
|
(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
|
|
|
|
|
|
(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
|
|
|
|
|
|
neon_quad.
|
|
|
|
|
|
(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
|
|
|
|
|
|
between VFP and Neon turns out to belong to Neon. Perform
|
|
|
|
|
|
architecture check and fill in condition field if appropriate.
|
|
|
|
|
|
(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
|
|
|
|
|
|
(do_neon_cvt): Add support for VFP variants of instructions.
|
|
|
|
|
|
(neon_cvt_flavour): Extend to cover VFP conversions.
|
|
|
|
|
|
(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
|
|
|
|
|
|
vmov variants.
|
|
|
|
|
|
(do_neon_ldr_str): Handle single-precision VFP load/store.
|
|
|
|
|
|
(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
|
|
|
|
|
|
NS_NULL not NS_IGNORE.
|
|
|
|
|
|
(opcode_tag): Add OT_csuffixF for operands which either take a
|
|
|
|
|
|
conditional suffix, or have 0xF in the condition field.
|
|
|
|
|
|
(md_assemble): Add support for OT_csuffixF.
|
|
|
|
|
|
(NCE): Replace macro with...
|
|
|
|
|
|
(NCE_tag, NCE, NCEF): New macros.
|
|
|
|
|
|
(nCE): Replace macro with...
|
|
|
|
|
|
(nCE_tag, nCE, nCEF): New macros.
|
|
|
|
|
|
(insns): Add support for VFP insns or VFP versions of insns msr,
|
|
|
|
|
|
mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
|
|
|
|
|
|
vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
|
|
|
|
|
|
vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
|
|
|
|
|
|
VFP/Neon insns together.
|
|
|
|
|
|
|
2006-06-07 11:27:58 +00:00
|
|
|
|
2006-06-07 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
Ladislav Michl <ladis@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
* app.c: Don't include headers already included by as.h.
|
|
|
|
|
|
* as.c: Likewise.
|
|
|
|
|
|
* atof-generic.c: Likewise.
|
|
|
|
|
|
* cgen.c: Likewise.
|
|
|
|
|
|
* dwarf2dbg.c: Likewise.
|
|
|
|
|
|
* expr.c: Likewise.
|
|
|
|
|
|
* input-file.c: Likewise.
|
|
|
|
|
|
* input-scrub.c: Likewise.
|
|
|
|
|
|
* macro.c: Likewise.
|
|
|
|
|
|
* output-file.c: Likewise.
|
|
|
|
|
|
* read.c: Likewise.
|
|
|
|
|
|
* sb.c: Likewise.
|
|
|
|
|
|
* config/bfin-lex.l: Likewise.
|
|
|
|
|
|
* config/obj-coff.h: Likewise.
|
|
|
|
|
|
* config/obj-elf.h: Likewise.
|
|
|
|
|
|
* config/obj-som.h: Likewise.
|
|
|
|
|
|
* config/tc-arc.c: Likewise.
|
|
|
|
|
|
* config/tc-arm.c: Likewise.
|
|
|
|
|
|
* config/tc-avr.c: Likewise.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-cris.c: Likewise.
|
|
|
|
|
|
* config/tc-d10v.c: Likewise.
|
|
|
|
|
|
* config/tc-d30v.c: Likewise.
|
|
|
|
|
|
* config/tc-dlx.h: Likewise.
|
|
|
|
|
|
* config/tc-fr30.c: Likewise.
|
|
|
|
|
|
* config/tc-frv.c: Likewise.
|
|
|
|
|
|
* config/tc-h8300.c: Likewise.
|
|
|
|
|
|
* config/tc-hppa.c: Likewise.
|
|
|
|
|
|
* config/tc-i370.c: Likewise.
|
|
|
|
|
|
* config/tc-i860.c: Likewise.
|
|
|
|
|
|
* config/tc-i960.c: Likewise.
|
|
|
|
|
|
* config/tc-ip2k.c: Likewise.
|
|
|
|
|
|
* config/tc-iq2000.c: Likewise.
|
|
|
|
|
|
* config/tc-m32c.c: Likewise.
|
|
|
|
|
|
* config/tc-m32r.c: Likewise.
|
|
|
|
|
|
* config/tc-maxq.c: Likewise.
|
|
|
|
|
|
* config/tc-mcore.c: Likewise.
|
|
|
|
|
|
* config/tc-mips.c: Likewise.
|
|
|
|
|
|
* config/tc-mmix.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.c: Likewise.
|
|
|
|
|
|
* config/tc-mt.c: Likewise.
|
|
|
|
|
|
* config/tc-ns32k.c: Likewise.
|
|
|
|
|
|
* config/tc-openrisc.c: Likewise.
|
|
|
|
|
|
* config/tc-ppc.c: Likewise.
|
|
|
|
|
|
* config/tc-s390.c: Likewise.
|
|
|
|
|
|
* config/tc-sh.c: Likewise.
|
|
|
|
|
|
* config/tc-sh64.c: Likewise.
|
|
|
|
|
|
* config/tc-sparc.c: Likewise.
|
|
|
|
|
|
* config/tc-tic30.c: Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c: Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c: Likewise.
|
|
|
|
|
|
* config/tc-v850.c: Likewise.
|
|
|
|
|
|
* config/tc-vax.c: Likewise.
|
|
|
|
|
|
* config/tc-xc16x.c: Likewise.
|
|
|
|
|
|
* config/tc-xstormy16.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c: Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
* config/tc-z8k.c: Likewise.
|
|
|
|
|
|
* macro.h: Don't include sb.h or ansidecl.h.
|
|
|
|
|
|
* sb.h: Don't include stdio.h or ansidecl.h.
|
|
|
|
|
|
* cond.c: Include sb.h.
|
|
|
|
|
|
* itbl-lex.l: Include as.h instead of other system headers.
|
|
|
|
|
|
* itbl-parse.y: Likewise.
|
|
|
|
|
|
* itbl-ops.c: Similarly.
|
|
|
|
|
|
* itbl-ops.h: Don't include as.h or ansidecl.h.
|
|
|
|
|
|
* config/bfin-defs.h: Don't include bfd.h or as.h.
|
|
|
|
|
|
* config/bfin-parse.y: Include as.h instead of other system headers.
|
|
|
|
|
|
|
2006-06-07 05:23:59 +00:00
|
|
|
|
2006-06-06 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
Anton Blanchard <anton@samba.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
|
|
|
|
|
|
(md_show_usage): Document it.
|
|
|
|
|
|
(ppc_setup_opcodes): Test power6 opcode flag bits.
|
|
|
|
|
|
* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
|
|
|
|
|
|
|
2006-06-06 10:49:48 +00:00
|
|
|
|
2006-06-06 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
|
|
|
|
|
|
(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
|
|
|
|
|
|
(macro_build): Update comment.
|
|
|
|
|
|
(mips_ip): Allow DSP64 instructions for MIPS64R2.
|
|
|
|
|
|
(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
|
|
|
|
|
|
CPU_HAS_MDMX.
|
|
|
|
|
|
(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
|
|
|
|
|
|
MIPS_CPU_ASE_MDMX flags for sb1.
|
|
|
|
|
|
|
2006-06-05 16:28:36 +00:00
|
|
|
|
2006-06-05 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
|
|
|
|
|
|
appropriate.
|
|
|
|
|
|
(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
|
|
|
|
|
|
(mips_ip): Make overflowed/underflowed constant arguments in DSP
|
|
|
|
|
|
and MT instructions a fatal error. Use INSERT_OPERAND where
|
|
|
|
|
|
appropriate. Improve warnings for break and wait code overflows.
|
|
|
|
|
|
Use symbolic constant of OP_MASK_COPZ.
|
|
|
|
|
|
(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
|
|
|
|
|
|
|
2006-06-05 14:04:05 +00:00
|
|
|
|
2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/Make-in (top_builddir): Define.
|
|
|
|
|
|
|
2006-06-02 23:08:12 +00:00
|
|
|
|
2006-06-02 Joseph S. Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/Makefile.am (TEXI2DVI): Define.
|
|
|
|
|
|
* doc/Makefile.in: Regenerate.
|
|
|
|
|
|
* doc/c-arc.texi: Fix typo.
|
|
|
|
|
|
|
2006-06-01 12:21:05 +00:00
|
|
|
|
2006-06-01 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-ieee.c: Delete.
|
|
|
|
|
|
* config/obj-ieee.h: Delete.
|
|
|
|
|
|
* Makefile.am (OBJ_FORMATS): Remove ieee.
|
|
|
|
|
|
(OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
|
|
|
|
|
|
(obj-ieee.o): Remove rule.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in (atof): Remove tahoe.
|
|
|
|
|
|
(OBJ_MAYBE_IEEE): Don't define.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* config.in: Regenerate.
|
|
|
|
|
|
* doc/Makefile.in: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2006-05-31 15:14:46 +00:00
|
|
|
|
2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
|
|
|
|
|
|
and LIBINTL_DEP everywhere.
|
|
|
|
|
|
(INTLLIBS): Remove.
|
|
|
|
|
|
(INCLUDES, DEP_INCLUDES): Use @INCINTL@.
|
|
|
|
|
|
* acinclude.m4: Include new gettext macros.
|
|
|
|
|
|
* configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
|
|
|
|
|
|
Remove local code for po/Makefile.
|
|
|
|
|
|
* Makefile.in, configure, doc/Makefile.in: Regenerated.
|
|
|
|
|
|
|
2006-05-30 11:01:59 +00:00
|
|
|
|
2006-05-30 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
|
2006-05-29 17:57:48 +00:00
|
|
|
|
2006-05-06 Denis Chertykov <denisc@overta.ru>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-avr.texi: New file.
|
|
|
|
|
|
* doc/Makefile.am (CPU_DOCS): Add c-avr.texi
|
|
|
|
|
|
* doc/all.texi: Set AVR
|
|
|
|
|
|
* doc/as.texinfo: Include c-avr.texi
|
|
|
|
|
|
|
2006-05-28 00:53:08 +00:00
|
|
|
|
2006-05-28 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y (check_macfunc): Loose the condition of
|
|
|
|
|
|
calling check_multiply_halfregs ().
|
|
|
|
|
|
|
2006-05-25 04:07:08 +00:00
|
|
|
|
2006-05-25 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y (asm_1): Better check and deal with
|
|
|
|
|
|
vector and scalar Multiply 16-Bit Operands instructions.
|
|
|
|
|
|
|
2006-05-24 11:05:42 +00:00
|
|
|
|
2006-05-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-hppa.c: Convert to ISO C90 format.
|
|
|
|
|
|
* config/tc-hppa.h: Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
2006-05-24 Carlos O'Donell <carlos@systemhalted.org>
|
|
|
|
|
|
Randolph Chung <randolph@tausq.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
|
|
|
|
|
|
is_tls_ieoff, is_tls_leoff): Define.
|
|
|
|
|
|
(fix_new_hppa): Handle TLS.
|
|
|
|
|
|
(cons_fix_new_hppa): Likewise.
|
|
|
|
|
|
(pa_ip): Likewise.
|
|
|
|
|
|
(md_apply_fix): Handle TLS relocs.
|
|
|
|
|
|
* config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
|
|
|
|
|
|
|
2006-05-24 07:36:12 +00:00
|
|
|
|
2006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 15:37:20 +00:00
|
|
|
|
2006-05-23 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
|
|
|
|
|
|
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
|
|
|
|
|
|
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
|
|
|
|
|
|
ISA_HAS_MXHC1): New macros.
|
|
|
|
|
|
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
|
|
|
|
|
|
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
|
|
|
|
|
|
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
|
|
|
|
|
|
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
|
|
|
|
|
|
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
|
|
|
|
|
|
(mips_after_parse_args): Change default handling of float register
|
|
|
|
|
|
size to account for 32bit code with 64bit FP. Better sanity checking
|
|
|
|
|
|
of ISA/ASE/ABI option combinations.
|
|
|
|
|
|
(s_mipsset): Support switching of GPR and FPR sizes via
|
|
|
|
|
|
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
|
|
|
|
|
|
options.
|
|
|
|
|
|
(mips_elf_final_processing): We should record the use of 64bit FP
|
|
|
|
|
|
registers in 32bit code but we don't, because ELF header flags are
|
|
|
|
|
|
a scarce ressource.
|
|
|
|
|
|
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
|
|
|
|
|
|
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
|
|
|
|
|
|
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
|
|
|
|
|
|
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
|
|
|
|
|
|
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
|
|
|
|
|
|
missing -march options. Document .set arch=CPU. Move .set smartmips
|
|
|
|
|
|
to ASE page. Use @code for .set FOO examples.
|
|
|
|
|
|
|
2006-05-23 06:01:12 +00:00
|
|
|
|
2006-05-23 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-bfin.c (bfin_start_line_hook): Bump line counters
|
|
|
|
|
|
if needed.
|
|
|
|
|
|
|
2006-05-23 04:23:41 +00:00
|
|
|
|
2006-05-23 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-defs.h (bfin_equals): Remove declaration.
|
|
|
|
|
|
* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
|
|
|
|
|
|
* config/tc-bfin.c (bfin_name_is_register): Remove.
|
|
|
|
|
|
(bfin_equals): Remove.
|
|
|
|
|
|
* config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
|
|
|
|
|
|
(bfin_name_is_register): Remove declaration.
|
|
|
|
|
|
|
2006-05-19 13:03:06 +00:00
|
|
|
|
2006-05-19 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
|
|
|
|
|
|
(mips_oddfpreg_ok): New function.
|
|
|
|
|
|
(mips_ip): Use it.
|
|
|
|
|
|
|
* config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
(regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
reg_names_o32, reg_names_n32n64): Define register classes.
(reg_lookup): New function, use register classes.
(md_begin): Reserve register names in the symbol table. Simplify
OBJ_ELF defines.
(mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
Use reg_lookup.
(mips16_ip): Use reg_lookup.
(tc_get_register): Likewise.
(tc_mips_regname_to_dw2regnum): New function.
-------------------------------------------------------------------
2006-05-19 12:34:09 +00:00
|
|
|
|
2006-05-19 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
|
|
|
|
|
|
* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
|
|
|
|
|
|
ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
|
|
|
|
|
|
(regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
|
|
|
|
|
|
RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
|
|
|
|
|
|
RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
|
|
|
|
|
|
FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
|
|
|
|
|
|
N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
|
|
|
|
|
|
SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
|
|
|
|
|
|
MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
|
|
|
|
|
|
reg_names_o32, reg_names_n32n64): Define register classes.
|
|
|
|
|
|
(reg_lookup): New function, use register classes.
|
|
|
|
|
|
(md_begin): Reserve register names in the symbol table. Simplify
|
|
|
|
|
|
OBJ_ELF defines.
|
|
|
|
|
|
(mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
|
|
|
|
|
|
Use reg_lookup.
|
|
|
|
|
|
(mips16_ip): Use reg_lookup.
|
|
|
|
|
|
(tc_get_register): Likewise.
|
|
|
|
|
|
(tc_mips_regname_to_dw2regnum): New function.
|
|
|
|
|
|
|
2006-05-19 11:26:11 +00:00
|
|
|
|
2006-05-19 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
|
|
|
|
|
|
Un-constify string argument.
|
|
|
|
|
|
* config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
|
2006-05-19 10:18:02 +00:00
|
|
|
|
2006-05-19 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
|
|
|
|
|
|
cfloat/m68881 to correct architecture before using it.
|
|
|
|
|
|
|
2006-05-16 08:23:43 +00:00
|
|
|
|
2006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
|
|
|
|
|
|
constant values.
|
|
|
|
|
|
|
2006-05-15 19:57:35 +00:00
|
|
|
|
2006-05-15 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_adjust_symtab): Use
|
|
|
|
|
|
bfd_is_arm_special_symbol_name.
|
|
|
|
|
|
|
2006-05-15 17:03:15 +00:00
|
|
|
|
2006-05-15 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
|
|
|
|
|
|
xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
|
|
|
|
|
|
xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
|
|
|
|
|
|
Handle errors from calls to xtensa_opcode_is_* functions.
|
|
|
|
|
|
|
2006-05-14 15:35:22 +00:00
|
|
|
|
2006-05-14 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro_build): Test for currently active
|
|
|
|
|
|
mips16 option.
|
|
|
|
|
|
(mips16_ip): Reject invalid opcodes.
|
|
|
|
|
|
|
2006-05-11 16:11:29 +00:00
|
|
|
|
2006-05-11 Carlos O'Donell <carlos@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo: Rename "Index" to "AS Index",
|
|
|
|
|
|
and "ABORT" to "ABORT (COFF)".
|
|
|
|
|
|
|
2006-05-11 15:17:34 +00:00
|
|
|
|
2006-05-11 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (parse_half): New function.
|
|
|
|
|
|
(operand_parse_code): Remove OP_Iffff. Add OP_HALF.
|
|
|
|
|
|
(parse_operands): Ditto.
|
|
|
|
|
|
(do_mov16): Reject invalid relocations.
|
|
|
|
|
|
(do_t_mov16): Ditto. Use Thumb reloc numbers.
|
|
|
|
|
|
(insns): Replace Iffff with HALF.
|
|
|
|
|
|
(md_apply_fix): Add MOVW and MOVT relocs.
|
|
|
|
|
|
(tc_gen_reloc): Ditto.
|
|
|
|
|
|
* doc/c-arm.texi: Document relocation operators
|
|
|
|
|
|
|
2006-05-11 15:05:17 +00:00
|
|
|
|
2006-05-11 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
|
|
|
|
|
|
|
2006-05-11 14:30:58 +00:00
|
|
|
|
2006-05-11 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Don't check the range of j or
|
|
|
|
|
|
jal addresses.
|
|
|
|
|
|
|
2006-05-11 08:48:58 +00:00
|
|
|
|
2006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_pcrel_from_section): Force a bias for
|
|
|
|
|
|
relocs against external symbols for WinCE targets.
|
|
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
|
2006-05-09 14:16:50 +00:00
|
|
|
|
2006-05-09 David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Only warn about an out-of-range
|
|
|
|
|
|
j or jal address.
|
|
|
|
|
|
|
2006-05-09 11:47:48 +00:00
|
|
|
|
2006-05-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
|
|
|
|
|
|
against symbols which are not going to be placed into the symbol
|
|
|
|
|
|
table.
|
|
|
|
|
|
|
2006-05-09 04:54:32 +00:00
|
|
|
|
2006-05-09 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* expr.c (operand): Remove `if (0 && ..)' statement and
|
|
|
|
|
|
subsequently unused target_op label. Collapse `if (1 || ..)'
|
|
|
|
|
|
statement.
|
|
|
|
|
|
* app.c (do_scrub_chars): Remove unused case 0, as it is handled
|
|
|
|
|
|
separately above the switch.
|
|
|
|
|
|
|
2006-05-08 17:08:34 +00:00
|
|
|
|
2006-05-08 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2623
|
|
|
|
|
|
* config/tc-msp430.c (line_separator_character): Define as |.
|
|
|
|
|
|
|
2006-05-08 15:57:05 +00:00
|
|
|
|
2006-05-08 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
Nigel Stephens <nigel@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
|
|
|
|
|
|
(mips_opts): Likewise.
|
|
|
|
|
|
(file_ase_smartmips): New variable.
|
|
|
|
|
|
(ISA_HAS_ROR): SmartMIPS implements rotate instructions.
|
|
|
|
|
|
(macro_build): Handle SmartMIPS instructions.
|
|
|
|
|
|
(mips_ip): Likewise.
|
|
|
|
|
|
(md_longopts): Add argument handling for smartmips.
|
|
|
|
|
|
(md_parse_options, mips_after_parse_args): Likewise.
|
|
|
|
|
|
(s_mipsset): Add .set smartmips support.
|
|
|
|
|
|
(md_show_usage): Document -msmartmips/-mno-smartmips.
|
|
|
|
|
|
* doc/as.texinfo: Document -msmartmips/-mno-smartmips and
|
|
|
|
|
|
.set smartmips.
|
|
|
|
|
|
* doc/c-mips.texi: Likewise.
|
|
|
|
|
|
|
2006-05-07 23:03:48 +00:00
|
|
|
|
2006-05-08 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (relax_segment): Add pass count arg. Don't error on
|
|
|
|
|
|
negative org/space on first two passes.
|
|
|
|
|
|
(relax_seg_info): New struct.
|
|
|
|
|
|
(relax_seg, write_object_file): Adjust.
|
|
|
|
|
|
* write.h (relax_segment): Update prototype.
|
|
|
|
|
|
|
2006-05-05 18:54:44 +00:00
|
|
|
|
2006-05-05 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
|
|
|
|
|
|
checking.
|
|
|
|
|
|
(do_neon_mov): Enable several VMOV variants for VFP. Add suitable
|
|
|
|
|
|
architecture version checks.
|
|
|
|
|
|
(insns): Allow overlapping instructions to be used in VFP mode.
|
|
|
|
|
|
|
2006-05-05 18:24:45 +00:00
|
|
|
|
2006-05-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2598
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section): Allow user
|
|
|
|
|
|
specified SHF_ALPHA_GPREL.
|
|
|
|
|
|
|
2006-05-05 17:46:47 +00:00
|
|
|
|
2006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
|
|
|
|
|
|
for PMEM related expressions.
|
|
|
|
|
|
|
2006-05-05 16:55:28 +00:00
|
|
|
|
2006-05-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2582
|
|
|
|
|
|
* dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
|
|
|
|
|
|
insertion of a directory separator character into a string at a
|
|
|
|
|
|
given offset. Uses heuristics to decide when to use a backslash
|
|
|
|
|
|
character rather than a forward-slash character.
|
|
|
|
|
|
(dwarf2_directive_loc): Use the macro.
|
|
|
|
|
|
(out_debug_info): Likewise.
|
|
|
|
|
|
|
2006-05-05 15:41:23 +00:00
|
|
|
|
2006-05-05 Thiemo Seufer <ths@mips.com>
|
|
|
|
|
|
David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro_build): Add case 'k' to handle cache
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
(macro): Add new case M_CACHE_AB.
|
|
|
|
|
|
|
2006-05-04 15:41:00 +00:00
|
|
|
|
2006-05-04 Kazu Hirata <kazu@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
|
|
|
|
|
|
(opcode_lookup): Issue a warning for opcode with
|
|
|
|
|
|
OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
|
|
|
|
|
|
identical to OT_cinfix3.
|
|
|
|
|
|
(TxC3w, TC3w, tC3w): New.
|
|
|
|
|
|
(insns): Use tC3w and TC3w for comparison instructions with
|
|
|
|
|
|
's' suffix.
|
|
|
|
|
|
|
2006-05-03 23:52:15 +00:00
|
|
|
|
2006-05-04 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* subsegs.h (struct frchain): Delete frch_seg.
|
|
|
|
|
|
(frchain_root): Delete.
|
|
|
|
|
|
(seg_info): Define as macro.
|
|
|
|
|
|
* subsegs.c (frchain_root): Delete.
|
|
|
|
|
|
(abs_seg_info, und_seg_info, absolute_frchain): Delete.
|
|
|
|
|
|
(subsegs_begin, subseg_change): Adjust for above.
|
|
|
|
|
|
(subseg_set_rest): Likewise. Add new frchain structs to seginfo
|
|
|
|
|
|
rather than to one big list.
|
|
|
|
|
|
(subseg_get): Don't special case abs, und sections.
|
|
|
|
|
|
(subseg_new, subseg_force_new): Don't set frchainP here.
|
|
|
|
|
|
(seg_info): Delete.
|
|
|
|
|
|
(subsegs_print_statistics): Adjust frag chain control list traversal.
|
|
|
|
|
|
* debug.c (dmp_frags): Likewise.
|
|
|
|
|
|
* dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
|
|
|
|
|
|
at frchain_root. Make use of known frchain ordering.
|
|
|
|
|
|
(last_frag_for_seg): Likewise.
|
|
|
|
|
|
(get_frag_fix): Likewise. Add seg param.
|
|
|
|
|
|
(process_entries, out_debug_aranges): Adjust get_frag_fix calls.
|
|
|
|
|
|
* write.c (chain_frchains_together_1): Adjust for struct frchain.
|
|
|
|
|
|
(SUB_SEGMENT_ALIGN): Likewise.
|
|
|
|
|
|
(subsegs_finish): Adjust frchain list traversal.
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
|
|
|
|
|
|
(xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
|
|
|
|
|
|
(xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
|
|
|
|
|
|
(xtensa_fix_b_j_loop_end_frags): Likewise.
|
|
|
|
|
|
(xtensa_fix_close_loop_end_frags): Likewise.
|
|
|
|
|
|
(xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
|
|
|
|
|
|
(retrieve_segment_info): Delete frch_seg initialisation.
|
|
|
|
|
|
|
2006-05-03 14:26:41 +00:00
|
|
|
|
2006-05-03 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
|
|
|
|
|
|
* config/obj-elf.h (obj_sec_set_private_data): Delete.
|
|
|
|
|
|
* config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
|
|
|
|
|
|
* config/tc-mn10300.c (tc_gen_reloc): Likewise.
|
|
|
|
|
|
|
2006-05-02 14:42:30 +00:00
|
|
|
|
2006-05-02 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
|
|
|
|
|
|
here.
|
|
|
|
|
|
(md_apply_fix3): Multiply offset by 4 here for
|
|
|
|
|
|
BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
|
|
|
|
|
|
|
2006-05-02 14:24:03 +00:00
|
|
|
|
2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_invalid_buf): Change size for
|
|
|
|
|
|
unsigned char.
|
|
|
|
|
|
* config/tc-tic30.c (output_invalid_buf): Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_invalid): Cast none-ascii char to
|
|
|
|
|
|
unsigned char.
|
|
|
|
|
|
* config/tc-tic30.c (output_invalid): Likewise.
|
|
|
|
|
|
|
2006-05-02 14:20:46 +00:00
|
|
|
|
2006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
|
|
|
|
|
|
(TEXI2POD): Use AM_MAKEINFOFLAGS.
|
|
|
|
|
|
(asconfig.texi): Don't set top_srcdir.
|
|
|
|
|
|
* doc/as.texinfo: Don't use top_srcdir.
|
|
|
|
|
|
* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
|
|
|
|
|
|
|
2006-05-02 14:24:03 +00:00
|
|
|
|
2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_invalid_buf): Change size to 16.
|
|
|
|
|
|
* config/tc-tic30.c (output_invalid_buf): Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (output_invalid): Use snprintf instead of
|
|
|
|
|
|
sprintf.
|
|
|
|
|
|
* config/tc-ia64.c (declare_register_set): Likewise.
|
|
|
|
|
|
(emit_one_bundle): Likewise.
|
|
|
|
|
|
(check_dependencies): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (output_invalid): Likewise.
|
|
|
|
|
|
|
2006-05-02 13:09:18 +00:00
|
|
|
|
2006-05-02 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_optimize_expr): New function.
|
|
|
|
|
|
* config/tc-arm.h (md_optimize_expr): Define
|
|
|
|
|
|
(arm_optimize_expr): Add prototype.
|
|
|
|
|
|
(TC_FORCE_RELOCATION_SUB_SAME): Define.
|
|
|
|
|
|
|
2006-05-02 03:39:04 +00:00
|
|
|
|
2006-05-02 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
2006-05-02 04:21:39 +00:00
|
|
|
|
* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
|
|
|
|
|
|
field unsigned.
|
|
|
|
|
|
|
2006-05-02 03:39:04 +00:00
|
|
|
|
* sb.h (sb_list_vector): Move to sb.c.
|
|
|
|
|
|
* sb.c (free_list): Use type of sb_list_vector directly.
|
|
|
|
|
|
(sb_build): Fix off-by-one error in assertion about `size'.
|
|
|
|
|
|
|
2006-05-01 09:21:46 +00:00
|
|
|
|
2006-05-01 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* listing.c (listing_listing): Remove useless loop.
|
|
|
|
|
|
* macro.c (macro_expand): Remove is_positional local variable.
|
|
|
|
|
|
* read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
|
|
|
|
|
|
and simplify surrounding expressions, where possible.
|
|
|
|
|
|
(assign_symbol): Likewise.
|
|
|
|
|
|
(s_weakref): Likewise.
|
|
|
|
|
|
* symbols.c (colon): Likewise.
|
|
|
|
|
|
|
2006-05-01 05:41:40 +00:00
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2006-05-01 James Lemke <jwlemke@wasabisystems.com>
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* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
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2006-04-30 18:34:39 +00:00
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2006-04-30 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
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(mips_immed): New table that records various handling of udi
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instruction patterns.
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(mips_ip): Adds udi handling.
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2006-04-28 04:07:33 +00:00
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2006-04-28 Alan Modra <amodra@bigpond.net.au>
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* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
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of list rather than beginning.
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2006-04-26 16:03:02 +00:00
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2006-04-26 Julian Brown <julian@codesourcery.com>
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* gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
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(is_quarter_float): Rename from above. Simplify slightly.
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(parse_qfloat_immediate): Parse a "quarter precision" floating-point
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number.
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(parse_neon_mov): Parse floating-point constants.
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(neon_qfloat_bits): Fix encoding.
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(neon_cmode_for_move_imm): Tweak to use floating-point encoding in
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preference to integer encoding when using the F32 type.
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* config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
zero-initialising structures containing it will lead to invalid types).
(arm_it): Add vectype to each operand.
(NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
defined field.
(neon_typed_alias): New structure. Extra information for typed
register aliases.
(reg_entry): Add neon type info field.
(arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
Break out alternative syntax for coprocessor registers, etc. into...
(arm_reg_alt_syntax): New function. Alternate syntax handling broken
out from arm_reg_parse.
(parse_neon_type): Move. Return SUCCESS/FAIL.
(first_error): New function. Call to ensure first error which occurs is
reported.
(parse_neon_operand_type): Parse exactly one type.
(NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
(parse_typed_reg_or_scalar): New function. Handle core of both
arm_typed_reg_parse and parse_scalar.
(arm_typed_reg_parse): Parse a register with an optional type.
(NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
result.
(parse_scalar): Parse a Neon scalar with optional type.
(parse_reg_list): Use first_error.
(parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
(neon_alias_types_same): New function. Return true if two (alias) types
are the same.
(parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
of elements.
(insert_reg_alias): Return new reg_entry not void.
(insert_neon_reg_alias): New function. Insert type/index information as
well as register for alias.
(create_neon_reg_alias): New function. Parse .dn/.qn directives and
make typed register aliases accordingly.
(s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
of line.
(s_unreq): Delete type information if present.
(s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
(s_arm_unwind_save_mmxwcg): Likewise.
(s_arm_unwind_movsp): Likewise.
(s_arm_unwind_setfp): Likewise.
(parse_shift): Likewise.
(parse_shifter_operand): Likewise.
(parse_address): Likewise.
(parse_tb): Likewise.
(tc_arm_regname_to_dw2regnum): Likewise.
(md_pseudo_table): Add dn, qn.
(parse_neon_mov): Handle typed operands.
(parse_operands): Likewise.
(neon_type_mask): Add N_SIZ.
(N_ALLMODS): New macro.
(neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
(el_type_of_type_chk): Add some safeguards.
(modify_types_allowed): Fix logic bug.
(neon_check_type): Handle operands with types.
(neon_three_same): Remove redundant optional arg handling.
(do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
(do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
(do_neon_step): Adjust accordingly.
(neon_cmode_for_logic_imm): Use first_error.
(do_neon_bitfield): Call neon_check_type.
(neon_dyadic): Rename to...
(neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
to allow modification of type of the destination.
(do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
(do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
(do_neon_compare): Make destination be an untyped bitfield.
(neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
(neon_mul_mac): Return early in case of errors.
(neon_move_immediate): Use first_error.
(neon_mac_reg_scalar_long): Fix type to include scalar.
(do_neon_dup): Likewise.
(do_neon_mov): Likewise (in several places).
(do_neon_tbl_tbx): Fix type.
(do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
(do_neon_ld_dup): Exit early in case of errors and/or use
first_error.
(opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
Handle .dn/.qn directives.
(REGDEF): Add zero for reg_entry neon field.
2006-04-26 15:55:45 +00:00
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2006-04-26 Julian Brown <julian@codesourcery.com>
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* config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
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zero-initialising structures containing it will lead to invalid types).
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(arm_it): Add vectype to each operand.
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(NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
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defined field.
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(neon_typed_alias): New structure. Extra information for typed
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register aliases.
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(reg_entry): Add neon type info field.
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(arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
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Break out alternative syntax for coprocessor registers, etc. into...
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(arm_reg_alt_syntax): New function. Alternate syntax handling broken
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out from arm_reg_parse.
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(parse_neon_type): Move. Return SUCCESS/FAIL.
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(first_error): New function. Call to ensure first error which occurs is
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reported.
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(parse_neon_operand_type): Parse exactly one type.
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(NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
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(parse_typed_reg_or_scalar): New function. Handle core of both
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arm_typed_reg_parse and parse_scalar.
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(arm_typed_reg_parse): Parse a register with an optional type.
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(NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
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result.
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(parse_scalar): Parse a Neon scalar with optional type.
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(parse_reg_list): Use first_error.
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(parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
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(neon_alias_types_same): New function. Return true if two (alias) types
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are the same.
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(parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
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of elements.
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(insert_reg_alias): Return new reg_entry not void.
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(insert_neon_reg_alias): New function. Insert type/index information as
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well as register for alias.
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(create_neon_reg_alias): New function. Parse .dn/.qn directives and
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make typed register aliases accordingly.
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(s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
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of line.
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(s_unreq): Delete type information if present.
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(s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
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(s_arm_unwind_save_mmxwcg): Likewise.
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(s_arm_unwind_movsp): Likewise.
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(s_arm_unwind_setfp): Likewise.
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(parse_shift): Likewise.
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(parse_shifter_operand): Likewise.
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(parse_address): Likewise.
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(parse_tb): Likewise.
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(tc_arm_regname_to_dw2regnum): Likewise.
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(md_pseudo_table): Add dn, qn.
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(parse_neon_mov): Handle typed operands.
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(parse_operands): Likewise.
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(neon_type_mask): Add N_SIZ.
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(N_ALLMODS): New macro.
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(neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
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(el_type_of_type_chk): Add some safeguards.
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(modify_types_allowed): Fix logic bug.
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(neon_check_type): Handle operands with types.
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(neon_three_same): Remove redundant optional arg handling.
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(do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
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(do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
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(do_neon_step): Adjust accordingly.
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(neon_cmode_for_logic_imm): Use first_error.
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(do_neon_bitfield): Call neon_check_type.
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(neon_dyadic): Rename to...
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(neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
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to allow modification of type of the destination.
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(do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
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(do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
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(do_neon_compare): Make destination be an untyped bitfield.
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(neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
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(neon_mul_mac): Return early in case of errors.
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(neon_move_immediate): Use first_error.
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(neon_mac_reg_scalar_long): Fix type to include scalar.
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(do_neon_dup): Likewise.
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(do_neon_mov): Likewise (in several places).
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(do_neon_tbl_tbx): Fix type.
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(do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
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(do_neon_ld_dup): Exit early in case of errors and/or use
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first_error.
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(opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
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Handle .dn/.qn directives.
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(REGDEF): Add zero for reg_entry neon field.
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* config/tc-arm.c (limits.h): Include.
(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
(fpu_vfp_v3_or_neon_ext): Declare constants.
(neon_el_type): New enumeration of types for Neon vector elements.
(neon_type_el): New struct. Define type and size of a vector element.
(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
instruction.
(neon_type): Define struct. The type of an instruction.
(arm_it): Add 'vectype' for the current instruction.
(isscalar, immisalign, regisimm, isquad): New predicates for operands.
(vfp_sp_reg_pos): Rename to...
(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
tags.
(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
(Neon D or Q register).
(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
register.
(GE_OPT_PREFIX_BIG): Define constant, for use in...
(my_get_expression): Allow above constant as argument to accept
64-bit constants with optional prefix.
(arm_reg_parse): Add extra argument to return the specific type of
register in when either a D or Q register (REG_TYPE_NDQ) is
requested. Can be NULL.
(parse_scalar): New function. Parse Neon scalar (vector reg and index).
(parse_reg_list): Update for new arm_reg_parse args.
(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
(parse_neon_el_struct_list): New function. Parse element/structure
register lists for VLD<n>/VST<n> instructions.
(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
(s_arm_unwind_save_mmxwr): Likewise.
(s_arm_unwind_save_mmxwcg): Likewise.
(s_arm_unwind_movsp): Likewise.
(s_arm_unwind_setfp): Likewise.
(parse_big_immediate): New function. Parse an immediate, which may be
64 bits wide. Put results in inst.operands[i].
(parse_shift): Update for new arm_reg_parse args.
(parse_address): Likewise. Add parsing of alignment specifiers.
(parse_neon_mov): Parse the operands of a VMOV instruction.
(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
(parse_operands): Handle new codes above.
(encode_arm_vfp_sp_reg): Rename to...
(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
selected VFP version only supports D0-D15.
(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
encode_arm_vfp_reg name, and allow 32 D regs.
(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
regs.
(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
constant-load and conversion insns introduced with VFPv3.
(neon_tab_entry): New struct.
(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
those which are the targets of pseudo-instructions.
(neon_opc): Enumerate opcodes, use as indices into...
(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
(NEON_ENC_DUP): Define meaningful helper macros to look up values in
neon_enc_tab.
(neon_shape): Enumerate shapes (permitted register widths, etc.) for
Neon instructions.
(neon_type_mask): New. Compact type representation for type checking.
(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
permitted type combinations.
(N_IGNORE_TYPE): New macro.
(neon_check_shape): New function. Check an instruction shape for
multiple alternatives. Return the specific shape for the current
instruction.
(neon_modify_type_size): New function. Modify a vector type and size,
depending on the bit mask in argument 1.
(neon_type_promote): New function. Convert a given "key" type (of an
operand) into the correct type for a different operand, based on a bit
mask.
(type_chk_of_el_type): New function. Convert a type and size into the
compact representation used for type checking.
(el_type_of_type_ckh): New function. Reverse of above (only when a
single bit is set in the bit mask).
(modify_types_allowed): New function. Alter a mask of allowed types
based on a bit mask of modifications.
(neon_check_type): New function. Check the type of the current
instruction against the variable argument list. The "key" type of the
instruction is returned.
(neon_dp_fixup): New function. Fill in and modify instruction bits for
a Neon data-processing instruction depending on whether we're in ARM
mode or Thumb-2 mode.
(neon_logbits): New function.
(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
(neon_move_immediate, do_neon_mvn, neon_mixed_length)
(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
helpers.
(parse_neon_type): New function. Parse Neon type specifier.
(opcode_lookup): Allow parsing of Neon type specifiers.
(REGNUM2, REGSETH, REGSET2): New macros.
(reg_names): Add new VFPv3 and Neon registers.
(NUF, nUF, NCE, nCE): New macros for opcode table.
(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
fto[us][lh][sd].
(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
(arm_option_cpu_value): Add vfp3 and neon.
(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
VFPv1 attribute.
2006-04-26 15:42:54 +00:00
|
|
|
|
2006-04-26 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (limits.h): Include.
|
|
|
|
|
|
(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
|
|
|
|
|
|
(fpu_vfp_v3_or_neon_ext): Declare constants.
|
|
|
|
|
|
(neon_el_type): New enumeration of types for Neon vector elements.
|
|
|
|
|
|
(neon_type_el): New struct. Define type and size of a vector element.
|
|
|
|
|
|
(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
(neon_type): Define struct. The type of an instruction.
|
|
|
|
|
|
(arm_it): Add 'vectype' for the current instruction.
|
|
|
|
|
|
(isscalar, immisalign, regisimm, isquad): New predicates for operands.
|
|
|
|
|
|
(vfp_sp_reg_pos): Rename to...
|
|
|
|
|
|
(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
|
|
|
|
|
|
tags.
|
|
|
|
|
|
(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
|
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|
|
|
|
(Neon D or Q register).
|
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|
|
|
|
(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
|
|
|
|
|
|
register.
|
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|
|
(GE_OPT_PREFIX_BIG): Define constant, for use in...
|
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|
|
(my_get_expression): Allow above constant as argument to accept
|
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|
|
64-bit constants with optional prefix.
|
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|
|
(arm_reg_parse): Add extra argument to return the specific type of
|
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|
|
register in when either a D or Q register (REG_TYPE_NDQ) is
|
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|
|
requested. Can be NULL.
|
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|
|
(parse_scalar): New function. Parse Neon scalar (vector reg and index).
|
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|
|
(parse_reg_list): Update for new arm_reg_parse args.
|
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|
|
(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
|
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|
|
|
(parse_neon_el_struct_list): New function. Parse element/structure
|
|
|
|
|
|
register lists for VLD<n>/VST<n> instructions.
|
|
|
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|
|
(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
|
|
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|
(s_arm_unwind_save_mmxwr): Likewise.
|
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|
(s_arm_unwind_save_mmxwcg): Likewise.
|
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|
|
(s_arm_unwind_movsp): Likewise.
|
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|
|
|
(s_arm_unwind_setfp): Likewise.
|
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|
|
|
(parse_big_immediate): New function. Parse an immediate, which may be
|
|
|
|
|
|
64 bits wide. Put results in inst.operands[i].
|
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|
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|
|
(parse_shift): Update for new arm_reg_parse args.
|
|
|
|
|
|
(parse_address): Likewise. Add parsing of alignment specifiers.
|
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|
|
|
|
(parse_neon_mov): Parse the operands of a VMOV instruction.
|
|
|
|
|
|
(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
|
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|
|
|
|
OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
|
|
|
|
|
|
OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
|
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|
|
|
|
OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
|
|
|
|
|
|
(parse_operands): Handle new codes above.
|
|
|
|
|
|
(encode_arm_vfp_sp_reg): Rename to...
|
|
|
|
|
|
(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
|
|
|
|
|
|
selected VFP version only supports D0-D15.
|
|
|
|
|
|
(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
|
|
|
|
|
|
(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
|
|
|
|
|
|
(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
|
|
|
|
|
|
(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
|
|
|
|
|
|
encode_arm_vfp_reg name, and allow 32 D regs.
|
|
|
|
|
|
(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
|
|
|
|
|
|
(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
|
|
|
|
|
|
regs.
|
|
|
|
|
|
(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
|
|
|
|
|
|
(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
|
|
|
|
|
|
constant-load and conversion insns introduced with VFPv3.
|
|
|
|
|
|
(neon_tab_entry): New struct.
|
|
|
|
|
|
(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
|
|
|
|
|
|
those which are the targets of pseudo-instructions.
|
|
|
|
|
|
(neon_opc): Enumerate opcodes, use as indices into...
|
|
|
|
|
|
(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
|
|
|
|
|
|
(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
|
|
|
|
|
|
(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
|
|
|
|
|
|
(NEON_ENC_DUP): Define meaningful helper macros to look up values in
|
|
|
|
|
|
neon_enc_tab.
|
|
|
|
|
|
(neon_shape): Enumerate shapes (permitted register widths, etc.) for
|
|
|
|
|
|
Neon instructions.
|
|
|
|
|
|
(neon_type_mask): New. Compact type representation for type checking.
|
|
|
|
|
|
(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
|
|
|
|
|
|
permitted type combinations.
|
|
|
|
|
|
(N_IGNORE_TYPE): New macro.
|
|
|
|
|
|
(neon_check_shape): New function. Check an instruction shape for
|
|
|
|
|
|
multiple alternatives. Return the specific shape for the current
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
(neon_modify_type_size): New function. Modify a vector type and size,
|
|
|
|
|
|
depending on the bit mask in argument 1.
|
|
|
|
|
|
(neon_type_promote): New function. Convert a given "key" type (of an
|
|
|
|
|
|
operand) into the correct type for a different operand, based on a bit
|
|
|
|
|
|
mask.
|
|
|
|
|
|
(type_chk_of_el_type): New function. Convert a type and size into the
|
|
|
|
|
|
compact representation used for type checking.
|
|
|
|
|
|
(el_type_of_type_ckh): New function. Reverse of above (only when a
|
|
|
|
|
|
single bit is set in the bit mask).
|
|
|
|
|
|
(modify_types_allowed): New function. Alter a mask of allowed types
|
|
|
|
|
|
based on a bit mask of modifications.
|
|
|
|
|
|
(neon_check_type): New function. Check the type of the current
|
|
|
|
|
|
instruction against the variable argument list. The "key" type of the
|
|
|
|
|
|
instruction is returned.
|
|
|
|
|
|
(neon_dp_fixup): New function. Fill in and modify instruction bits for
|
|
|
|
|
|
a Neon data-processing instruction depending on whether we're in ARM
|
|
|
|
|
|
mode or Thumb-2 mode.
|
|
|
|
|
|
(neon_logbits): New function.
|
|
|
|
|
|
(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
|
|
|
|
|
|
(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
|
|
|
|
|
|
(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
|
|
|
|
|
|
(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
|
|
|
|
|
|
(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
|
|
|
|
|
|
(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
|
|
|
|
|
|
(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
|
|
|
|
|
|
(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
|
|
|
|
|
|
(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
|
|
|
|
|
|
(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
|
|
|
|
|
|
(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
|
|
|
|
|
|
(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
|
|
|
|
|
|
(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
|
|
|
|
|
|
(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
|
|
|
|
|
|
(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
|
|
|
|
|
|
(neon_move_immediate, do_neon_mvn, neon_mixed_length)
|
|
|
|
|
|
(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
|
|
|
|
|
|
(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
|
|
|
|
|
|
(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
|
|
|
|
|
|
(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
|
|
|
|
|
|
(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
|
|
|
|
|
|
(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
|
|
|
|
|
|
(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
|
|
|
|
|
|
(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
|
|
|
|
|
|
(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
|
|
|
|
|
|
helpers.
|
|
|
|
|
|
(parse_neon_type): New function. Parse Neon type specifier.
|
|
|
|
|
|
(opcode_lookup): Allow parsing of Neon type specifiers.
|
|
|
|
|
|
(REGNUM2, REGSETH, REGSET2): New macros.
|
|
|
|
|
|
(reg_names): Add new VFPv3 and Neon registers.
|
|
|
|
|
|
(NUF, nUF, NCE, nCE): New macros for opcode table.
|
|
|
|
|
|
(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
|
|
|
|
|
|
fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
|
|
|
|
|
|
fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
|
|
|
|
|
|
Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
|
|
|
|
|
|
vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
|
|
|
|
|
|
vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
|
|
|
|
|
|
vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
|
|
|
|
|
|
vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
|
|
|
|
|
|
vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
|
|
|
|
|
|
vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
|
|
|
|
|
|
vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
|
|
|
|
|
|
vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
|
|
|
|
|
|
vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
|
|
|
|
|
|
vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
|
|
|
|
|
|
fto[us][lh][sd].
|
|
|
|
|
|
(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
|
|
|
|
|
|
(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
|
|
|
|
|
|
(arm_option_cpu_value): Add vfp3 and neon.
|
|
|
|
|
|
(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
|
|
|
|
|
|
VFPv1 attribute.
|
|
|
|
|
|
|
2006-04-25 17:11:10 +00:00
|
|
|
|
2006-04-25 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
|
|
|
|
|
|
syntax instead of hardcoded opcodes with ".w18" suffixes.
|
|
|
|
|
|
(wide_branch_opcode): New.
|
|
|
|
|
|
(build_transition): Use it to check for wide branch opcodes with
|
|
|
|
|
|
either ".w18" or ".w15" suffixes.
|
|
|
|
|
|
|
2006-04-25 16:32:56 +00:00
|
|
|
|
2006-04-25 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_create_literal_symbol,
|
|
|
|
|
|
xg_assemble_literal, xg_assemble_literal_space): Do not set the
|
|
|
|
|
|
frag's is_literal flag.
|
|
|
|
|
|
|
2006-04-25 15:41:16 +00:00
|
|
|
|
2006-04-25 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
|
|
|
|
|
|
|
* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
2006-04-23 22:12:43 +00:00
|
|
|
|
2006-04-23 Kazu Hirata <kazu@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
|
|
|
|
|
|
config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
|
|
|
|
|
|
config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
|
|
|
|
|
|
config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
|
|
|
|
|
|
config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
|
|
|
|
|
|
|
2006-04-20 12:39:51 +00:00
|
|
|
|
2005-04-20 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
|
|
|
|
|
|
all targets.
|
|
|
|
|
|
(md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
|
|
|
|
|
|
|
2006-04-19 12:10:46 +00:00
|
|
|
|
2006-04-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
|
|
|
|
|
|
(CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
|
|
|
|
|
|
Make some cpus unsupported on ELF. Run "make dep-am".
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
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|
|
2006-04-19 02:06:15 +00:00
|
|
|
|
2006-04-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (--enable-targets): Indent help message.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2006-04-18 17:52:37 +00:00
|
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|
2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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|
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|
|
PR gas/2533
|
|
|
|
|
|
* config/tc-i386.c (i386_immediate): Check illegal immediate
|
|
|
|
|
|
register operand.
|
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|
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|
|
|
2006-04-18 09:55:27 +00:00
|
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|
2006-04-18 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
2006-04-18 10:11:09 +00:00
|
|
|
|
* config/tc-i386.c: Formatting.
|
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|
|
(output_disp, output_imm): ISO C90 params.
|
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|
2006-04-18 09:58:26 +00:00
|
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|
|
* frags.c (frag_offset_fixed_p): Constify args.
|
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|
|
|
|
* frags.h (frag_offset_fixed_p): Ditto.
|
|
|
|
|
|
|
2006-04-18 09:55:27 +00:00
|
|
|
|
* config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
|
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|
|
|
(COFF_MAGIC): Delete.
|
2006-04-18 09:50:08 +00:00
|
|
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|
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|
* config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
|
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|
2006-04-16 18:25:11 +00:00
|
|
|
|
2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
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|
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|
|
* po/POTFILES.in: Regenerated.
|
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|
2006-04-16 18:15:55 +00:00
|
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|
2006-04-16 Mark Mitchell <mark@codesourcery.com>
|
|
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|
|
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|
|
* doc/as.texinfo: Mention that some .type syntaxes are not
|
|
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|
|
|
supported on all architectures.
|
|
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|
2006-04-15 00:04:15 +00:00
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|
2006-04-14 Sterling Augustine <sterling@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
|
|
|
|
|
|
instructions when such transformations have been disabled.
|
|
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|
|
|
2006-04-10 19:00:31 +00:00
|
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|
|
2006-04-10 Sterling Augustine <sterling@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
|
|
|
|
|
|
symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
|
|
|
|
|
|
(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
|
|
|
|
|
|
decoding the loop instructions. Remove current_offset variable.
|
|
|
|
|
|
(xtensa_fix_short_loop_frags): Likewise.
|
|
|
|
|
|
(min_bytes_to_other_loop_end): Remove current_offset argument.
|
|
|
|
|
|
|
2006-04-09 18:08:08 +00:00
|
|
|
|
2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
|
|
|
|
|
|
|
2006-04-18 09:50:08 +00:00
|
|
|
|
* config/tc-z80.c (z80_optimize_expr): Removed.
|
2006-04-09 18:08:08 +00:00
|
|
|
|
* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
|
|
|
|
|
|
|
Add support for attiny261, attiny461, attiny861, attiny25, attiny45,
attiny85, attiny24, attiny44, attiny84, at90pwm2, at90pwm3, atmega164,
atmega324, atmega644, atmega329, atmega3290, atmega649, atmega6490,
atmega406, atmega640, atmega1280, atmega1281, at90can32, at90can64,
at90usb646, at90usb647, at90usb1286 and at90usb1287.
Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
2006-04-07 15:18:08 +00:00
|
|
|
|
2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
|
|
|
|
|
|
attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
|
|
|
|
|
|
attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
|
|
|
|
|
|
atmega644, atmega329, atmega3290, atmega649, atmega6490,
|
|
|
|
|
|
atmega406, atmega640, atmega1280, atmega1281, at90can32,
|
|
|
|
|
|
at90can64, at90usb646, at90usb647, at90usb1286 and
|
|
|
|
|
|
at90usb1287.
|
|
|
|
|
|
Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
|
|
|
|
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|
|
2006-04-07 15:11:19 +00:00
|
|
|
|
2006-04-07 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
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|
|
* config/tc-arm.c (parse_operands): Set default error message.
|
|
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|
|
2006-04-07 15:09:40 +00:00
|
|
|
|
2006-04-07 Paul Brook <paul@codesourcery.com>
|
|
|
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|
|
|
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|
|
* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
|
|
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|
2006-04-07 15:08:04 +00:00
|
|
|
|
2006-04-07 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
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|
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|
|
* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
|
|
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|
|
2006-04-07 15:03:45 +00:00
|
|
|
|
2006-04-07 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
|
|
|
|
|
|
(move_or_literal_pool): Handle Thumb-2 instructions.
|
|
|
|
|
|
(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
|
|
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|
|
|
|
2006-04-07 06:40:57 +00:00
|
|
|
|
2006-04-07 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
PR 2512.
|
|
|
|
|
|
* config/tc-i386.c (match_template): Move 64-bit operand tests
|
|
|
|
|
|
inside loop.
|
|
|
|
|
|
|
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* Makefile.tpl: Add install-html target.
* Makefile.def: Add install-html target.
* Makefile.in: Regenerate.
* configure.in: Add --with-datarootdir, --with-docdir,
and --with-htmldir options.
* configure: Regenerate.
bfd/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* po/Make-in: Add install-html target.
* Makefile.am: Rename docdir to bfddocdir. Add datarootdir, docdir
htmldir. Add install-html and install-html-recursive targets.
* Makefile.in: Regenerate.
* configure.in: AC_SUBST for datarootdir, docdir and htmldir.
* configure: Regenerate.
bfd/doc/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* Makefile.am: Add install-html and install-html-am targets.
Define datarootdir, docdir and htmldir.
* Makefile.in: Regenerate.
binutils/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* po/Make-in: Add install-html target.
* Makefile.am: Add install-html and install-html-recursive targets.
* Makefile.in: Regenerate.
* configure.in: AC_SUBST datarootdir, docdir and htmldir.
* configure: Regenerate.
* doc/Makefile.am: Add install-html and install-html-am targets.
* doc/Makefile.in: Regenerate.
etc/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* Makefile.in: Add install-html target. Add htmldir,
docdir and datarootdir.
* configure.texi: Document install-html target.
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
* configure: Regenerate.
gas/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* po/Make-in: Add install-html target.
* Makefile.am: Add install-html and install-html-recursive targets.
* Makefile.in: Regenerate.
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
* configure: Regenerate.
* doc/Makefile.am: Add install-html and install-html-am targets.
* doc/Makefile.in: Regenerate.
gprof/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* po/Make-in: Add install-html target.
* Makefile.am: Add install-html, install-html-am and
install-html-recursive targets.
* Makefile.in: Regenerate.
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
* configure: Regenerate.
intl/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* intl/Makefile.in: Add html info and dvi and install-html to .PHONY
Add install-html target.
ld/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* Makefile.am: Add install-html, install-html-am, and
install-html-recursive targets.
* Makefile.in: Regenerate.
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
* configure: Regenerate.
* po/Make-in: Add install-html target.
opcodes/
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
* Makefile.am: Add install-html target.
* Makefile.in: Regenerate.
2006-04-06 21:49:35 +00:00
|
|
|
|
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/Make-in: Add install-html target.
|
|
|
|
|
|
* Makefile.am: Add install-html and install-html-recursive targets.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* doc/Makefile.am: Add install-html and install-html-am targets.
|
|
|
|
|
|
* doc/Makefile.in: Regenerate.
|
|
|
|
|
|
|
2006-04-06 04:38:33 +00:00
|
|
|
|
2006-04-06 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* frags.c (frag_offset_fixed_p): Reinitialise offset before
|
|
|
|
|
|
second scan.
|
|
|
|
|
|
|
bfd/
* config.bfd (sparc-*-vxworks*): New stanza.
* configure.in (bfd_elf32_sparc_vxworks_vec): New stanza.
(bfd_elf32_sparc_vec, bfd_elf64_sparc_vec): Add elf-vxworks.lo.
* configure: Regenerate.
* elf32-sparc.c: Include elf-vxworks.h.
(elf32_sparc_vxworks_link_hash_table_create: New.
(elf32_sparc_vxworks_final_write_processing): New.
(TARGET_BIG_SYM): Override for VxWorks.
(TARGET_BIG_NAME, ELF_MINPAGESIZE): Likewise.
(bfd_elf32_bfd_link_hash_table_create): Likewise.
(elf_backend_want_got_plt, elf_backend_plt_readonly): Likewise.
(elf_backend_got_header_size, elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing, elf32_bed): Likewise.
* elfxx-sparc.c: Include libiberty.h and elf-vxworks.h.
(sparc_vxworks_exec_plt0_entry, sparc_vxworks_exec_plt_entry): New.
(sparc_vxworks_shared_plt0_entry, sparc_vxworks_shared_plt_entry): New.
(_bfd_sparc_elf_link_hash_table_create): Don't initialize
build_plt_entry here.
(create_got_section): Initialize sgotplt for VxWorks.
(_bfd_sparc_elf_create_dynamic_sections): Initialize build_plt_entry,
plt_header_size and plt_entry_size, with new VxWorks-specific settings.
Call elf_vxworks_create_dynamic_sections for VxWorks.
(allocate_dynrelocs): Use plt_header_size and plt_entry_size.
Allocate room for .got.plt and .rela.plt.unloaded entries on VxWorks.
(_bfd_sparc_elf_size_dynamic_sections): Don't allocate a nop in .plt
for VxWorks. Check for the .got.plt section.
(sparc_vxworks_build_plt_entry): New function.
(_bfd_sparc_elf_finish_dynamic_symbol): Add handling of VxWorks PLTs.
Don't make _GLOBAL_OFFSET_TABLE_ and _PROCEDURE_LINKAGE_TABLE_
absolute on VxWorks.
(sparc32_finish_dyn): Add special handling for DT_RELASZ
and DT_PLTGOT on VxWorks.
(sparc_vxworks_finish_exec_plt): New.
(sparc_vxworks_finish_shared_plt): New.
(_bfd_sparc_elf_finish_dynamic_sections): Call them.
Use plt_header_size and plt_entry_size.
* elfxx-sparc.h (_bfd_sparc_elf_link_hash_table): Add is_vxworks,
srelplt2, sgotplt, plt_header_size and plt_entry_size fields.
* Makefile.am (elfxx-sparc.lo): Depend on elf-vxworks.h.
(elf32-sparc.lo): Likewise.
* Makefile.in: Regenerate.
* targets.c (bfd_elf32_sparc_vxworks_vec): Declare.
(_bfd_target_vector): Add a pointer to it.
gas/
* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
(GOTT_BASE, GOTT_INDEX): New.
(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
GOTT_INDEX when generating VxWorks PIC.
* configure.tgt (sparc*-*-vxworks*): Remove this special case;
use the generic *-*-vxworks* stanza instead.
gas/testsuite/
* gas/sparc/vxworks-pic.s, gas/sparc/vxworks-pic.d: New test.
* gas/sparc/sparc.exp: Run it. Remove sparc*-*-vxworks* XFAILs.
ld/
* configure.tgt (sparc*-*-vxworks*): New stanza.
* emulparams/elf32_sparc_vxworks.sh: New file.
* Makefile.am (ALL_EMULATIONS): Add eelf32_sparc_vxworks.o.
(eelf32_sparc_vxworks.c): New rule.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-sparc/vxworks1.dd, ld-sparc/vxworks1.ld, ld-sparc/vxworks1-lib.dd,
* ld-sparc/vxworks1-lib.nd, ld-sparc/vxworks1-lib.rd,
* ld-sparc/vxworks1-lib.s, ld-sparc/vxworks1.rd, ld-sparc/vxworks1.s,
* ld-sparc/vxworks1-static.d, ld-sparc/vxworks2.s,
* ld-sparc/vxworks2.sd, ld-sparc/vxworks2-static.sd: New tests.
* ld-sparc/sparc.exp: Run them.
2006-04-05 12:41:59 +00:00
|
|
|
|
2006-04-05 Richard Sandiford <richard@codesourcery.com>
|
|
|
|
|
|
Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
|
|
|
|
|
|
(GOTT_BASE, GOTT_INDEX): New.
|
|
|
|
|
|
(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
|
|
|
|
|
|
GOTT_INDEX when generating VxWorks PIC.
|
|
|
|
|
|
* configure.tgt (sparc*-*-vxworks*): Remove this special case;
|
|
|
|
|
|
use the generic *-*-vxworks* stanza instead.
|
|
|
|
|
|
|
2006-04-04 08:04:57 +00:00
|
|
|
|
2006-04-04 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
PR 997
|
|
|
|
|
|
* frags.c (frag_offset_fixed_p): New function.
|
|
|
|
|
|
* frags.h (frag_offset_fixed_p): Declare.
|
|
|
|
|
|
* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
|
|
|
|
|
|
(resolve_expression): Likewise.
|
|
|
|
|
|
|
2006-04-03 19:11:05 +00:00
|
|
|
|
2006-04-03 Sterling Augustine <sterling@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
|
|
|
|
|
|
of the same length but different numbers of slots.
|
|
|
|
|
|
|
2006-03-30 13:35:17 +00:00
|
|
|
|
2006-03-30 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Fix help string for --enable-targets option.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
gas:
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
m68020_control_regs, m68040_control_regs, m68060_control_regs,
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
mcf5282_ctrl, mcfv4e_ctrl): ... these.
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
(struct m68k_cpu): Change chip field to control_regs.
(current_chip): Remove.
(control_regs): New.
(m68k_archs, m68k_extensions): Adjust.
(m68k_cpus): Reorder to be in cpu number order. Adjust.
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
(find_cf_chip): Reimplement for new organization of cpu table.
(select_control_regs): Remove.
(mri_chip): Adjust.
(struct save_opts): Save control regs, not chip.
(s_save, s_restore): Adjust.
(m68k_lookup_cpu): Give deprecated warning when necessary.
(m68k_init_arch): Adjust.
(md_show_usage): Adjust for new cpu table organization.
include/opcodes:
* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
2006-03-28 07:19:16 +00:00
|
|
|
|
2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
2006-03-28 07:21:49 +00:00
|
|
|
|
* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
|
|
|
|
|
|
(m68k_ip): ... here. Use for all chips. Protect against buffer
|
|
|
|
|
|
overrun and avoid excessive copying.
|
|
|
|
|
|
|
gas:
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
m68020_control_regs, m68040_control_regs, m68060_control_regs,
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
mcf5282_ctrl, mcfv4e_ctrl): ... these.
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
(struct m68k_cpu): Change chip field to control_regs.
(current_chip): Remove.
(control_regs): New.
(m68k_archs, m68k_extensions): Adjust.
(m68k_cpus): Reorder to be in cpu number order. Adjust.
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
(find_cf_chip): Reimplement for new organization of cpu table.
(select_control_regs): Remove.
(mri_chip): Adjust.
(struct save_opts): Save control regs, not chip.
(s_save, s_restore): Adjust.
(m68k_lookup_cpu): Give deprecated warning when necessary.
(m68k_init_arch): Adjust.
(md_show_usage): Adjust for new cpu table organization.
include/opcodes:
* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
2006-03-28 07:19:16 +00:00
|
|
|
|
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
|
|
|
|
|
|
m68020_control_regs, m68040_control_regs, m68060_control_regs,
|
|
|
|
|
|
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
|
|
|
|
|
|
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
|
|
|
|
|
|
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
|
|
|
|
|
|
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
|
|
|
|
|
|
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
|
|
|
|
|
|
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
|
|
|
|
|
|
mcf5282_ctrl, mcfv4e_ctrl): ... these.
|
|
|
|
|
|
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
|
|
|
|
|
|
(struct m68k_cpu): Change chip field to control_regs.
|
|
|
|
|
|
(current_chip): Remove.
|
|
|
|
|
|
(control_regs): New.
|
|
|
|
|
|
(m68k_archs, m68k_extensions): Adjust.
|
|
|
|
|
|
(m68k_cpus): Reorder to be in cpu number order. Adjust.
|
|
|
|
|
|
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
|
|
|
|
|
|
(find_cf_chip): Reimplement for new organization of cpu table.
|
|
|
|
|
|
(select_control_regs): Remove.
|
|
|
|
|
|
(mri_chip): Adjust.
|
|
|
|
|
|
(struct save_opts): Save control regs, not chip.
|
|
|
|
|
|
(s_save, s_restore): Adjust.
|
|
|
|
|
|
(m68k_lookup_cpu): Give deprecated warning when necessary.
|
|
|
|
|
|
(m68k_init_arch): Adjust.
|
|
|
|
|
|
(md_show_usage): Adjust for new cpu table organization.
|
|
|
|
|
|
|
2006-03-26 01:12:07 +00:00
|
|
|
|
2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
|
|
|
|
|
|
* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
|
|
|
|
|
|
* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
|
|
|
|
|
|
"elf/bfin.h".
|
|
|
|
|
|
(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
|
|
|
|
|
|
(any_gotrel): New rule.
|
|
|
|
|
|
(got): Use it, and create Expr_Node_GOT_Reloc nodes.
|
|
|
|
|
|
* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
|
|
|
|
|
|
"elf/bfin.h".
|
|
|
|
|
|
(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
|
|
|
|
|
|
(bfin_pic_ptr): New function.
|
|
|
|
|
|
(md_pseudo_table): Add it for ".picptr".
|
|
|
|
|
|
(OPTION_FDPIC): New macro.
|
|
|
|
|
|
(md_longopts): Add -mfdpic.
|
|
|
|
|
|
(md_parse_option): Handle it.
|
|
|
|
|
|
(md_begin): Set BFD flags.
|
|
|
|
|
|
(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
|
|
|
|
|
|
(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
|
|
|
|
|
|
us for GOT relocs.
|
|
|
|
|
|
* Makefile.am (bfin-parse.o): Update dependencies.
|
|
|
|
|
|
(DEPTC_bfin_elf): Likewise.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2006-03-25 10:24:27 +00:00
|
|
|
|
2006-03-25 Richard Sandiford <richard@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
|
|
|
|
|
|
mcfemac instead of mcfmac.
|
|
|
|
|
|
|
2006-04-26 09:24:07 +00:00
|
|
|
|
2006-03-23 Michael Matz <matz@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (type_names): Correct placement of 'static'.
|
|
|
|
|
|
(reloc): Map some more relocs to their 64 bit counterpart when
|
|
|
|
|
|
size is 8.
|
|
|
|
|
|
(output_insn): Work around breakage if DEBUG386 is defined.
|
|
|
|
|
|
(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
|
|
|
|
|
|
needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
|
|
|
|
|
|
BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
|
|
|
|
|
|
different from i386.
|
|
|
|
|
|
(output_imm): Ditto.
|
|
|
|
|
|
(lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
|
|
|
|
|
|
Imm64.
|
|
|
|
|
|
(md_convert_frag): Jumps can now be larger than 2GB away, error
|
|
|
|
|
|
out in that case.
|
|
|
|
|
|
(tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
|
|
|
|
|
|
and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
|
|
|
|
|
|
|
Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Phil Edwards <phil@codesourcery.com>
Zack Weinberg <zack@codesourcery.com>
Mark Mitchell <mark@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
bfd/
* bfd-in2.h: Regenerate.
* config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas.
* configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(bfd_elf32_bigmips_vec): Add elf-vxworks.lo.
(bfd_elf32_littlemips_vec): Likewise.
(bfd_elf32_nbigmips_vec): Likewise.
(bfd_elf32_nlittlemips_vec): Likewise.
(bfd_elf32_ntradbigmips_vec): Likewise.
(bfd_elf32_ntradlittlemips_vec): Likewise.
(bfd_elf32_tradbigmips_vec): Likewise.
(bfd_elf32_tradlittlemips_vec): Likewise.
(bfd_elf64_bigmips_vec): Likewise.
(bfd_elf64_littlemips_vec): Likewise.
(bfd_elf64_tradbigmips_vec): Likewise.
(bfd_elf64_tradlittlemips_vec): Likewise.
* elf32-mips.c: Include elf-vxworks.h.
(mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto
instead of calling mips_elf32_rtype_to_howto directly.
(mips_vxworks_copy_howto_rela): New reloc howto.
(mips_vxworks_jump_slot_howto_rela): Likewise.
(mips_vxworks_bfd_reloc_type_lookup): New function.
(mips_vxworks_rtype_to_howto): Likewise.
(mips_vxworks_final_write_processing): Likewise.
(TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks.
(TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise.
(elf_backend_want_got_plt): Likewise.
(elf_backend_want_plt_sym): Likewise.
(elf_backend_got_symbol_offset): Likewise.
(elf_backend_want_dynbss): Likewise.
(elf_backend_may_use_rel_p): Likewise.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_got_header_size: Likewise.
(elf_backend_plt_readonly): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Likewise.
(elf_backend_mips_rtype_to_howto): Likewise.
(elf_backend_adjust_dynamic_symbol): Likewise.
(elf_backend_finish_dynamic_symbol): Likewise.
(bfd_elf32_bfd_link_hash_table_create): Likewise.
(elf_backend_add_symbol_hook): Likewise.
(elf_backend_link_output_symbol_hook): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_final_write_processing: Likewise.
(elf_backend_additional_program_headers): Likewise.
(elf_backend_modify_segment_map): Likewise.
(elf_backend_symbol_processing): Likewise.
* elfxx-mips.c: Include elf-vxworks.h.
(mips_elf_link_hash_entry): Add is_relocation_target and
is_branch_target fields.
(mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt,
srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields.
(MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros.
(MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument.
Return 3 for VxWorks.
(ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a
mips_elf_link_hash_table. Return 0 for VxWorks.
(MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a
mips_elf_link_hash_table. Update the call to ELF_MIPS_GP_OFFSET.
(mips_vxworks_exec_plt0_entry): New variable.
(mips_vxworks_exec_plt_entry): Likewise.
(mips_vxworks_shared_plt0_entry): Likewise.
(mips_vxworks_shared_plt_entry): Likewise.
(mips_elf_link_hash_newfunc): Initialize the new hash_entry fields.
(mips_elf_rel_dyn_section): Change the bfd argument to a
mips_elf_link_hash_table. Use MIPS_ELF_REL_DYN_NAME to get
the name of the section.
(mips_elf_initialize_tls_slots): Update the call to
mips_elf_rel_dyn_section.
(mips_elf_gotplt_index): New function.
(mips_elf_local_got_index): Add an input_section argument.
Update the call to mips_elf_create_local_got_entry.
(mips_elf_got_page): Likewise.
(mips_elf_got16_entry): Likewise.
(mips_elf_create_local_got_entry): Add bfd_link_info and input_section
arguments. Create dynamic relocations for each entry on VxWorks.
(mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE.
(mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE
and MIPS_RESERVED_GOTNO.
(mips_elf_create_got_section): Update the uses of
MIPS_ELF_GOT_MAX_SIZE. Create .got.plt on VxWorks.
(is_gott_symbol): New function.
(mips_elf_calculate_relocation): Use a dynobj local variable.
Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and
mips_elf_got_page_entry. Set G to the .got.plt entry when calculating
VxWorks R_MIPS_CALL* relocations. Calculate and use G for all GOT
relocations on VxWorks. Add dynamic relocations for references
to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Don't
create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64
in VxWorks executables.
(mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument.
Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry.
Don't allocate a null entry on VxWorks.
(mips_elf_create_dynamic_relocation): Update the call to
mips_elf_rel_dyn_section. Use absolute rather than relative
relocations for VxWorks, and make them RELA rather than REL.
(_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic
read-only on VxWorks. Update the call to mips_elf_rel_dyn_section.
Create the .plt, .rela.plt, .dynbss and .rela.bss sections on
VxWorks. Likewise create the _PROCEDURE_LINKAGE_TABLE symbol.
Call elf_vxworks_create_dynamic_sections for VxWorks and
initialize the plt_header_size and plt_entry_size fields.
(_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be
used in VxWorks executables. Don't allocate dynamic relocations
for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables.
Set is_relocation_target for each symbol referenced by a relocation.
Allocate .rela.dyn entries for relocations against the special
VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Create GOT
entries for all VxWorks R_MIPS_GOT16 relocations. Don't allocate
a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*,
R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations. Update the calls
to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations.
Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26
relocations. Don't set no_fn_stub on VxWorks.
(_bfd_mips_elf_adjust_dynamic_symbol): Update the call to
mips_elf_allocate_dynamic_relocations.
(_bfd_mips_vxworks_adjust_dynamic_symbol): New function.
(_bfd_mips_elf_always_size_sections): Do not allocate GOT page
entries for VxWorks, and do not create multiple GOTs.
(_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME.
Handle .got specially for VxWorks. Update the uses of
MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations.
Check for sgotplt and splt. Allocate the .rel(a).dyn contents last,
once its final size is known. Set DF_TEXTREL for VxWorks. Add
DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL
tags on VxWorks. Do not add the MIPS-specific tags for VxWorks.
(_bfd_mips_vxworks_finish_dynamic_symbol): New function.
(mips_vxworks_finish_exec_plt): Likewise.
(mips_vxworks_finish_shared_plt): Likewise.
(_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call
to mips_elf_rel_dyn_section. Use a VxWorks-specific value of
DT_PLTGOT. Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL,
DT_PLTRELSZ and DT_JMPREL. Update the uses of MIPS_RESERVED_GOTNO
and mips_elf_rel_dyn_section. Use a different GOT header for
VxWorks. Don't sort .rela.dyn on VxWorks. Finish the PLT on VxWorks.
(_bfd_mips_elf_link_hash_table_create): Initialize the new
mips_elf_link_hash_table fields.
(_bfd_mips_vxworks_link_hash_table_create): New function.
(_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_
on VxWorks. Update the call to ELF_MIPS_GP_OFFSET.
* elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_vxworks_link_hash_table_create): Likewise.
* libbfd.h: Regenerate.
* Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h.
(elf32-mips.lo): Likewise.
* Makefile.in: Regenerate.
* reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare.
* targets.c (bfd_elf32_bigmips_vxworks_vec): Declare.
(bfd_elf32_littlemips_vxworks_vec): Likewise.
(_bfd_target_vector): Add entries for them.
gas/
* config/tc-mips.c (mips_target_format): Handle vxworks targets.
(md_begin): Complain about -G being used for PIC. Don't change
the text, data and bss alignments on VxWorks.
(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
generating VxWorks PIC.
(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
(macro): Likewise, but do not treat la $25 specially for
VxWorks PIC, and do not handle jal.
(OPTION_MVXWORKS_PIC): New macro.
(md_longopts): Add -mvxworks-pic.
(md_parse_option): Don't complain about using PIC and -G together here.
Handle OPTION_MVXWORKS_PIC.
(md_estimate_size_before_relax): Always use the first relaxation
sequence on VxWorks.
* config/tc-mips.h (VXWORKS_PIC): New.
gas/testsuite/
* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
* gas/mips/vxworks1-xgot.d: New tests.
* gas/mips/mips.exp: Run them. Do not run other tests on VxWorks.
include/elf/
* mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs.
ld/
* configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use
separate VxWorks emulations.
* emulparams/elf32ebmipvxworks.sh: New file.
* emulparams/elf32elmipvxworks.sh: New file.
* Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and
eelf32elmipvxworks.o.
(eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd,
* ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd,
* ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s,
* ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd,
* ld-mips/vxworks2-static.sd: New tests.
* ld-mips/mips-elf.exp: Run them.
2006-03-22 09:28:15 +00:00
|
|
|
|
2006-03-22 Richard Sandiford <richard@codesourcery.com>
|
|
|
|
|
|
Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
Phil Edwards <phil@codesourcery.com>
|
|
|
|
|
|
Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
Mark Mitchell <mark@codesourcery.com>
|
|
|
|
|
|
Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_target_format): Handle vxworks targets.
|
|
|
|
|
|
(md_begin): Complain about -G being used for PIC. Don't change
|
|
|
|
|
|
the text, data and bss alignments on VxWorks.
|
|
|
|
|
|
(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
|
|
|
|
|
|
generating VxWorks PIC.
|
|
|
|
|
|
(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
|
|
|
|
|
|
(macro): Likewise, but do not treat la $25 specially for
|
|
|
|
|
|
VxWorks PIC, and do not handle jal.
|
|
|
|
|
|
(OPTION_MVXWORKS_PIC): New macro.
|
|
|
|
|
|
(md_longopts): Add -mvxworks-pic.
|
|
|
|
|
|
(md_parse_option): Don't complain about using PIC and -G together here.
|
|
|
|
|
|
Handle OPTION_MVXWORKS_PIC.
|
|
|
|
|
|
(md_estimate_size_before_relax): Always use the first relaxation
|
|
|
|
|
|
sequence on VxWorks.
|
|
|
|
|
|
* config/tc-mips.h (VXWORKS_PIC): New.
|
|
|
|
|
|
|
2006-03-21 22:52:06 +00:00
|
|
|
|
2006-03-21 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
|
|
|
|
|
|
|
2006-03-21 20:34:38 +00:00
|
|
|
|
2006-03-21 Sterling Augustine <sterling@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
|
|
|
|
|
|
(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
|
|
|
|
|
|
(get_loop_align_size): New.
|
|
|
|
|
|
(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
|
|
|
|
|
|
(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
|
|
|
|
|
|
(get_text_align_power): Rewrite to handle inputs in the range 2-8.
|
|
|
|
|
|
(get_noop_aligned_address): Use get_loop_align_size.
|
|
|
|
|
|
(get_aligned_diff): Likewise.
|
|
|
|
|
|
|
2006-03-21 14:35:27 +00:00
|
|
|
|
2006-03-21 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
|
|
|
|
|
|
|
2006-03-20 Paul Brook <paul@codesourcery.com>
gas/
* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
(do_t_branch): Encode branches inside IT blocks as unconditional.
(do_t_cps): New function.
(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
(opcode_lookup): Allow conditional suffixes on all instructions in
Thumb mode.
(md_assemble): Advance condexec state before checking for errors.
(insns): Use do_t_cps.
gas/testsuite/
* gas/arm/thumb2_bcond.d: New test.
* gas/arm/thumb2_bcond.s: New test.
* gas/arm/thumb2_it_bad.d: New test.
* gas/arm/thumb2_it_bad.l: New test.
* gas/arm/thumb2_it_bad.s: New test.
2006-03-20 15:38:02 +00:00
|
|
|
|
2006-03-20 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
|
|
|
|
|
|
(do_t_branch): Encode branches inside IT blocks as unconditional.
|
|
|
|
|
|
(do_t_cps): New function.
|
|
|
|
|
|
(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
|
|
|
|
|
|
do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
|
|
|
|
|
|
(opcode_lookup): Allow conditional suffixes on all instructions in
|
|
|
|
|
|
Thumb mode.
|
|
|
|
|
|
(md_assemble): Advance condexec state before checking for errors.
|
|
|
|
|
|
(insns): Use do_t_cps.
|
|
|
|
|
|
|
2006-03-20 15:14:49 +00:00
|
|
|
|
2006-03-20 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
|
|
|
|
|
|
outputting the insn.
|
|
|
|
|
|
|
2006-03-18 11:23:38 +00:00
|
|
|
|
2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-vax.c: Update copyright year.
|
|
|
|
|
|
* config/tc-vax.h: Likewise.
|
|
|
|
|
|
|
2006-03-18 11:06:47 +00:00
|
|
|
|
2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-vax.c (md_chars_to_number): Used only locally, so
|
|
|
|
|
|
make it static.
|
|
|
|
|
|
* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
|
|
|
|
|
|
|
2006-03-17 14:03:36 +00:00
|
|
|
|
2006-03-17 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (insns): Add ldm and stm.
|
|
|
|
|
|
|
2006-03-17 00:45:13 +00:00
|
|
|
|
2006-03-17 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2446
|
|
|
|
|
|
* doc/as.texinfo (Ident): Document this directive more thoroughly.
|
|
|
|
|
|
|
2006-03-16 15:08:48 +00:00
|
|
|
|
2006-03-16 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (insns): Add "svc".
|
|
|
|
|
|
|
2006-03-13 21:46:53 +00:00
|
|
|
|
2006-03-13 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
|
|
|
|
|
|
flag and avoid double underscore prefixes.
|
|
|
|
|
|
|
2006-03-10 17:20:30 +00:00
|
|
|
|
2006-03-10 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_begin): Handle EABIv5.
|
|
|
|
|
|
(arm_eabis): Add EF_ARM_EABI_VER5.
|
|
|
|
|
|
* doc/c-arm.texi: Document -meabi=5.
|
|
|
|
|
|
|
2006-03-10 10:57:18 +00:00
|
|
|
|
2006-03-10 Ben Elliston <bje@au.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* app.c (do_scrub_chars): Simplify string handling.
|
|
|
|
|
|
|
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
2006-03-07 08:39:21 +00:00
|
|
|
|
2006-03-07 Richard Sandiford <richard@codesourcery.com>
|
|
|
|
|
|
Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
Ricardo Anguiano <anguiano@codesourcery.com>
|
|
|
|
|
|
Phil Edwards <phil@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
|
|
|
|
|
|
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
|
|
|
|
|
|
R_ARM_ABS12 reloc.
|
|
|
|
|
|
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
|
|
|
|
|
|
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
|
|
|
|
|
|
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
|
|
|
|
|
|
|
2006-03-06 18:02:06 +00:00
|
|
|
|
2006-03-06 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
|
|
|
|
|
|
even when using the text-section-literals option.
|
|
|
|
|
|
|
2006-03-06 13:42:05 +00:00
|
|
|
|
2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
|
|
|
|
|
|
and cf.
|
|
|
|
|
|
(m68k_ip): <case 'J'> Check we have some control regs.
|
|
|
|
|
|
(md_parse_option): Allow raw arch switch.
|
|
|
|
|
|
(m68k_init_arch): Better detection of arch/cpu mismatch. Detect
|
|
|
|
|
|
whether 68881 or cfloat was meant by -mfloat.
|
|
|
|
|
|
(md_show_usage): Adjust extension display.
|
|
|
|
|
|
(m68k_elf_final_processing): Adjust.
|
|
|
|
|
|
|
2006-03-03 15:25:31 +00:00
|
|
|
|
2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c (avr_mod_hash_value): New function.
|
|
|
|
|
|
(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
|
|
|
|
|
|
BFD_RELOC_MS8_LDI for hlo8() and hhi8()
|
|
|
|
|
|
(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
|
|
|
|
|
|
instead of int avr_ldi_expression: use avr_mod_hash_value instead
|
|
|
|
|
|
of (int).
|
|
|
|
|
|
(tc_gen_reloc): Handle substractions of symbols, if possible do
|
|
|
|
|
|
fixups, abort otherwise.
|
|
|
|
|
|
* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
|
|
|
|
|
|
tc_fix_adjustable): Define.
|
|
|
|
|
|
|
2006-03-03 01:10:42 +00:00
|
|
|
|
2006-03-02 James E Wilson <wilson@specifix.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
|
|
|
|
|
|
change the template, then clear md.slot[curr].end_of_insn_group.
|
|
|
|
|
|
|
2006-02-28 07:57:09 +00:00
|
|
|
|
2006-02-28 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
|
|
|
|
|
|
|
2006-02-28 07:55:36 +00:00
|
|
|
|
2006-02-28 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR/1070
|
|
|
|
|
|
* macro.c (getstring): Don't treat parentheses special anymore.
|
|
|
|
|
|
(get_any_string): Don't consider '(' and ')' as quoting anymore.
|
|
|
|
|
|
Special-case '(', ')', '[', and ']' when dealing with non-quoting
|
|
|
|
|
|
characters.
|
|
|
|
|
|
|
2006-02-28 00:38:19 +00:00
|
|
|
|
2006-02-28 Mat <mat@csail.mit.edu>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
|
|
|
|
|
|
|
2006-02-27 23:07:06 +00:00
|
|
|
|
2006-02-27 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
|
|
|
|
|
|
field.
|
|
|
|
|
|
(CFI_signal_frame): Define.
|
|
|
|
|
|
(cfi_pseudo_table): Add .cfi_signal_frame.
|
|
|
|
|
|
(dot_cfi): Handle CFI_signal_frame.
|
|
|
|
|
|
(output_cie): Handle cie->signal_frame.
|
|
|
|
|
|
(select_cie_for_fde): Don't share CIE if signal_frame flag is
|
|
|
|
|
|
different. Copy signal_frame from FDE to newly created CIE.
|
|
|
|
|
|
* doc/as.texinfo: Document .cfi_signal_frame.
|
|
|
|
|
|
|
2006-02-27 16:26:26 +00:00
|
|
|
|
2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/Makefile.am: Add html target.
|
|
|
|
|
|
* doc/Makefile.in: Regenerate.
|
|
|
|
|
|
* po/Make-in: Add html target.
|
|
|
|
|
|
|
2006-02-27 15:35:37 +00:00
|
|
|
|
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
2006-02-27 23:21:41 +00:00
|
|
|
|
* config/tc-i386.c (output_insn): Support Intel Merom New
|
2006-02-27 15:35:37 +00:00
|
|
|
|
Instructions.
|
|
|
|
|
|
|
2006-02-27 23:21:41 +00:00
|
|
|
|
* config/tc-i386.h (CpuMNI): New.
|
2006-02-27 15:35:37 +00:00
|
|
|
|
(CpuUnknownFlags): Add CpuMNI.
|
|
|
|
|
|
|
2006-02-25 01:34:09 +00:00
|
|
|
|
2006-02-24 David S. Miller <davem@sunset.davemloft.net>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
|
|
|
|
|
|
(hpriv_reg_table): New table for hyperprivileged registers.
|
|
|
|
|
|
(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
|
|
|
|
|
|
register encoding.
|
|
|
|
|
|
|
[include/elf]
* m32c.h: Add relax relocs.
[cpu]
* m32c.cpu (RL_TYPE): New attribute, with macros.
(Lab-8-24): Add RELAX.
(unary-insn-defn-g, binary-arith-imm-dst-defn,
binary-arith-imm4-dst-defn): Add 1ADDR attribute.
(binary-arith-src-dst-defn): Add 2ADDR attribute.
(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
attribute.
(jsri16, jsri32): Add 1ADDR attribute.
(jsr32.w, jsr32.a): Add JUMP attribute.
[opcodes]
* m32c-desc.c: Regenerate with linker relaxation attributes.
* m32c-desc.h: Likewise.
* m32c-dis.c: Likewise.
* m32c-opc.c: Likewise.
[gas]
* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
(tc_gen_reloc): Don't define.
* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
(OPTION_LINKRELAX): New.
(md_longopts): Add it.
(m32c_relax): New.
(md_parse_options): Set it.
(md_assemble): Emit relaxation relocs as needed.
(md_convert_frag): Emit relaxation relocs as needed.
(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
(m32c_apply_fix): New.
(tc_gen_reloc): New.
(m32c_force_relocation): Force out jump relocs when relaxing.
(m32c_fix_adjustable): Return false if relaxing.
[bfd]
* elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs.
(m32c_elf_relocate_section): Don't relocate them.
(compare_reloc): New.
(relax_reloc): Remove.
(m32c_offset_for_reloc): New.
(m16c_addr_encodings): New.
(m16c_jmpaddr_encodings): New.
(m32c_addr_encodings): New.
(m32c_elf_relax_section): Relax jumps and address displacements.
(m32c_elf_relax_delete_bytes): Adjust for internal syms. Fix up
short jumps.
* reloc.c: Add m32c relax relocs.
* libbfd.h: Regenerate.
2006-02-24 22:10:36 +00:00
|
|
|
|
2006-02-24 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
|
|
|
|
|
|
(tc_gen_reloc): Don't define.
|
|
|
|
|
|
* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
|
|
|
|
|
|
(OPTION_LINKRELAX): New.
|
|
|
|
|
|
(md_longopts): Add it.
|
|
|
|
|
|
(m32c_relax): New.
|
|
|
|
|
|
(md_parse_options): Set it.
|
|
|
|
|
|
(md_assemble): Emit relaxation relocs as needed.
|
|
|
|
|
|
(md_convert_frag): Emit relaxation relocs as needed.
|
|
|
|
|
|
(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
|
|
|
|
|
|
(m32c_apply_fix): New.
|
|
|
|
|
|
(tc_gen_reloc): New.
|
|
|
|
|
|
(m32c_force_relocation): Force out jump relocs when relaxing.
|
|
|
|
|
|
(m32c_fix_adjustable): Return false if relaxing.
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 15:36:36 +00:00
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
|
|
|
|
|
|
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
|
|
|
|
|
|
(struct asm_barrier_opt): Define.
|
|
|
|
|
|
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
|
|
|
|
|
|
(parse_psr): Accept V7M psr names.
|
|
|
|
|
|
(parse_barrier): New function.
|
|
|
|
|
|
(enum operand_parse_code): Add OP_oBARRIER.
|
|
|
|
|
|
(parse_operands): Implement OP_oBARRIER.
|
|
|
|
|
|
(do_barrier): New function.
|
|
|
|
|
|
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
|
|
|
|
|
|
(do_t_cpsi): Add V7M restrictions.
|
|
|
|
|
|
(do_t_mrs, do_t_msr): Validate V7M variants.
|
|
|
|
|
|
(md_assemble): Check for NULL variants.
|
|
|
|
|
|
(v7m_psrs, barrier_opt_names): New tables.
|
|
|
|
|
|
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
|
|
|
|
|
|
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
|
|
|
|
|
|
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
|
|
|
|
|
|
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
|
|
|
|
|
|
(struct cpu_arch_ver_table): Define.
|
|
|
|
|
|
(cpu_arch_ver): New.
|
|
|
|
|
|
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
|
|
|
|
|
|
Tag_CPU_arch_profile.
|
|
|
|
|
|
* doc/c-arm.texi: Document new cpu and arch options.
|
|
|
|
|
|
|
2006-02-23 21:36:18 +00:00
|
|
|
|
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
|
|
|
|
|
|
|
2006-02-23 14:49:32 +00:00
|
|
|
|
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c: Update copyright years.
|
|
|
|
|
|
|
2006-02-23 00:17:24 +00:00
|
|
|
|
2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (specify_resource): Add the rule 17 from
|
|
|
|
|
|
SDM 2.2.
|
|
|
|
|
|
|
2006-02-22 15:03:30 +00:00
|
|
|
|
2005-02-22 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_pld): Remove incorrect write to
|
|
|
|
|
|
inst.instruction.
|
|
|
|
|
|
(encode_thumb32_addr_mode): Use correct operand.
|
|
|
|
|
|
|
2006-02-21 15:13:54 +00:00
|
|
|
|
2006-02-21 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
|
|
|
|
|
|
|
2006-02-17 14:36:28 +00:00
|
|
|
|
2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
|
|
|
|
|
|
Anil Paranjape <anilp1@kpitcummins.com>
|
|
|
|
|
|
Shilin Shakti <shilins@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add xc16x related entry.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in: Added xc16x related entry.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* config/tc-xc16x.h: New file
|
|
|
|
|
|
* config/tc-xc16x.c: New file
|
|
|
|
|
|
* doc/c-xc16x.texi: New file for xc16x
|
|
|
|
|
|
* doc/all.texi: Entry for xc16x
|
|
|
|
|
|
* doc/Makefile.texi: Added c-xc16x.texi
|
|
|
|
|
|
* NEWS: Announce the support for the new target.
|
|
|
|
|
|
|
2006-02-16 08:05:02 +00:00
|
|
|
|
2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: set emulation for mips-*-netbsd*
|
|
|
|
|
|
|
2006-02-14 08:59:10 +00:00
|
|
|
|
2006-02-14 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config.in: Rebuilt.
|
|
|
|
|
|
|
2006-02-14 00:58:05 +00:00
|
|
|
|
2006-02-13 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
|
|
|
|
|
|
from 1, not 0, in error messages.
|
|
|
|
|
|
(md_assemble): Simplify special-case check for ENTRY instructions.
|
|
|
|
|
|
(tinsn_has_invalid_symbolic_operands): Do not include opcode and
|
|
|
|
|
|
operand in error message.
|
|
|
|
|
|
|
2006-02-13 15:08:43 +00:00
|
|
|
|
2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (arm-*-linux-gnueabi*): Change to
|
|
|
|
|
|
arm-*-linux-*eabi*.
|
|
|
|
|
|
|
2006-02-10 12:10:21 +00:00
|
|
|
|
2006-02-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2006-02-10 12:21:43 +00:00
|
|
|
|
* config/tc-crx.c (check_range): Ensure that the sign bit of a
|
|
|
|
|
|
32-bit value is propagated into the upper bits of a 64-bit long.
|
|
|
|
|
|
|
2006-02-10 12:10:21 +00:00
|
|
|
|
* config/tc-arc.c (init_opcode_tables): Fix cast.
|
|
|
|
|
|
(arc_extoper, md_operand): Likewise.
|
|
|
|
|
|
|
2006-02-10 01:02:12 +00:00
|
|
|
|
2006-02-09 David Heine <dlheine@tensilica.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
|
|
|
|
|
|
each relaxation step.
|
|
|
|
|
|
|
2006-02-09 18:43:50 +00:00
|
|
|
|
2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (CHECK_DECLS): Add vsnprintf.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
|
|
|
|
|
|
include/declare here, but...
|
|
|
|
|
|
* as.h: Move code detecting VARARGS idiom to the top.
|
|
|
|
|
|
(errno.h, stdarg.h, varargs.h, va_list): ...here.
|
|
|
|
|
|
(vsnprintf): Declare if not already declared.
|
|
|
|
|
|
|
2006-02-09 00:07:41 +00:00
|
|
|
|
2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* as.c (close_output_file): New.
|
|
|
|
|
|
(main): Register close_output_file with xatexit before
|
|
|
|
|
|
dump_statistics. Don't call output_file_close.
|
|
|
|
|
|
|
* bfd/archures.c (bfd_mach_mcf5200, bfd_mach_mcf5206e,
bfd_mach_mcf5307, bfd_mach_mcf5407, bfd_mach_mcf528x,
bfd_mach_mcfv4e, bfd_mach_mcf521x, bfd_mach_mcf5249,
bfd_mach_mcf547x, bfd_mach_mcf548x): Remove.
(bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_div,
bfd_mach_mcf_isa_a_div_mac, bfd_mach_mcf_isa_a_div_emac,
bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac,
bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_aplus_usp,
bfd_mach_mcf_isa_aplus_usp_mac, bfd_mach_mcf_isa_aplus_usp_emac,
bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac,
bfd_mach_mcf_isa_b_usp_float, bfd_mach_mcf_isa_b_usp_float_mac,
bfd_mach_mcf_isa_b_usp_float_emac): New.
(bfd_default_scan): Update coldfire mapping.
* bfd/bfd-in.h (bfd_m68k_mach_to_features,
bfd_m68k_features_to_mach): Declare.
* bfd/bfd-in2.h: Rebuilt.
* bfd/cpu-m68k.c (arch_info_struct): Add new coldfire machines,
adjust legacy names.
(m68k_arch_features): New.
(bfd_m68k_mach_to_features,
bfd_m68k_features_to_mach): Define.
* bfd/elf32-m68k.c (elf32_m68k_object_p): New.
(elf32_m68k_merge_private_bfd_data): Merge the CF EF flags.
(elf32_m68k_print_private_bfd_data): Print the CF EF flags.
(elf_backend_object_p): Define.
* bfd/ieee.c (ieee_write_processor): Update coldfire machines.
* bfd/libbfd.h: Rebuilt.
* gas/config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
mcf5329_control_regs): New.
(not_current_architecture, selected_arch, selected_cpu): New.
(m68k_archs, m68k_extensions): New.
(archs): Renamed to ...
(m68k_cpus): ... here. Adjust.
(n_arches): Remove.
(md_pseudo_table): Add arch and cpu directives.
(find_cf_chip, m68k_ip): Adjust table scanning.
(no_68851, no_68881): Remove.
(md_assemble): Lazily initialize.
(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
(md_init_after_args): Move functionality to m68k_init_arch.
(mri_chip): Adjust table scanning.
(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
options with saner parsing.
(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
m68k_init_arch): New.
(s_m68k_cpu, s_m68k_arch): New.
(md_show_usage): Adjust.
(m68k_elf_final_processing): Set CF EF flags.
* gas/config/tc-m68k.h (m68k_init_after_args): Remove.
(tc_init_after_args): Remove.
* gas/doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
(M68k-Directives): Document .arch and .cpu directives.
* gas/testsuite/gas/m68k/all.exp: Add arch-cpu-1 test.
* gas/testsuite/gas/m68k/arch-cpu-1.[sd]: New.
* include/elf/m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ...
(EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here.
(EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS,
EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC,
EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New.
* include/opcode/m68k.h (m68008, m68ec030, m68882): Remove.
(m68k_mask): New.
(cpu_m68k, cpu_cf): New.
(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
* opcodes/m68k-dis.c (print_insn_m68k): Use
bfd_m68k_mach_to_features.
* binutils/readelf.c (get_machine_flags): Add logic for EF_M68K flags.
2006-02-07 19:01:10 +00:00
|
|
|
|
2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
|
|
|
|
|
|
mcf5329_control_regs): New.
|
|
|
|
|
|
(not_current_architecture, selected_arch, selected_cpu): New.
|
|
|
|
|
|
(m68k_archs, m68k_extensions): New.
|
|
|
|
|
|
(archs): Renamed to ...
|
|
|
|
|
|
(m68k_cpus): ... here. Adjust.
|
|
|
|
|
|
(n_arches): Remove.
|
|
|
|
|
|
(md_pseudo_table): Add arch and cpu directives.
|
|
|
|
|
|
(find_cf_chip, m68k_ip): Adjust table scanning.
|
|
|
|
|
|
(no_68851, no_68881): Remove.
|
|
|
|
|
|
(md_assemble): Lazily initialize.
|
|
|
|
|
|
(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
|
|
|
|
|
|
(md_init_after_args): Move functionality to m68k_init_arch.
|
|
|
|
|
|
(mri_chip): Adjust table scanning.
|
|
|
|
|
|
(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
|
|
|
|
|
|
options with saner parsing.
|
|
|
|
|
|
(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
|
|
|
|
|
|
m68k_init_arch): New.
|
|
|
|
|
|
(s_m68k_cpu, s_m68k_arch): New.
|
|
|
|
|
|
(md_show_usage): Adjust.
|
|
|
|
|
|
(m68k_elf_final_processing): Set CF EF flags.
|
|
|
|
|
|
* config/tc-m68k.h (m68k_init_after_args): Remove.
|
|
|
|
|
|
(tc_init_after_args): Remove.
|
|
|
|
|
|
* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
|
|
|
|
|
|
(M68k-Directives): Document .arch and .cpu directives.
|
|
|
|
|
|
|
2006-02-05 11:57:35 +00:00
|
|
|
|
2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
|
|
|
|
|
|
synonyms for equ and defl.
|
|
|
|
|
|
(z80_cons_fix_new): New function.
|
|
|
|
|
|
(emit_byte): Disallow relative jumps to absolute locations.
|
|
|
|
|
|
(emit_data): Only handle defb, prototype changed, because defb is
|
|
|
|
|
|
now handled as pseudo-op rather than an instruction.
|
|
|
|
|
|
(instab): Entries for defb,defw,db,dw moved from here...
|
|
|
|
|
|
(md_pseudo_table): ... to here, use generic cons() for defw,dw.
|
|
|
|
|
|
Add entries for def24,def32,d24,d32.
|
|
|
|
|
|
(md_assemble): Improved error handling.
|
|
|
|
|
|
(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
|
|
|
|
|
|
* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
|
|
|
|
|
|
(z80_cons_fix_new): Declare.
|
|
|
|
|
|
* doc/c-z80.texi (defb, db): Mention warning on overflow.
|
|
|
|
|
|
(def24,d24,def32,d32): New pseudo-ops.
|
|
|
|
|
|
|
2006-02-02 20:19:56 +00:00
|
|
|
|
2006-02-02 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
|
|
|
|
|
|
|
2005-02-02 Paul Brook <paul@codesourcery.com>
gas/
* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
T2_OPCODE_RSB): Define.
(thumb32_negate_data_op): New function.
(md_apply_fix): Use it.
gas/testsuite/
* gas/arm/thumb2_invert.d: New test.
* gas/arm/thumb2_invert.s: New test.
2006-02-02 13:34:17 +00:00
|
|
|
|
2005-02-02 Paul Brook <paul@codesourcery.com>
|
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|
|
|
|
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|
|
* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
|
|
|
|
|
|
T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
|
|
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|
|
|
T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
|
|
|
|
|
|
T2_OPCODE_RSB): Define.
|
|
|
|
|
|
(thumb32_negate_data_op): New function.
|
|
|
|
|
|
(md_apply_fix): Use it.
|
|
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|
|
2006-01-31 19:36:57 +00:00
|
|
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|
2006-01-31 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
|
|
|
|
|
|
fields.
|
|
|
|
|
|
* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
|
|
|
|
|
|
* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
|
|
|
|
|
|
subtracted symbols.
|
|
|
|
|
|
(relaxation_requirements): Add pfinish_frag argument and use it to
|
|
|
|
|
|
replace setting tinsn->record_fix fields.
|
|
|
|
|
|
(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
|
|
|
|
|
|
and vinsn_to_insnbuf. Remove references to record_fix and
|
|
|
|
|
|
slot_sub_symbols fields.
|
|
|
|
|
|
(xtensa_mark_narrow_branches): Delete unused code.
|
|
|
|
|
|
(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
|
|
|
|
|
|
a symbol.
|
|
|
|
|
|
(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
|
|
|
|
|
|
record_fix fields.
|
|
|
|
|
|
(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
|
|
|
|
|
|
(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
|
|
|
|
|
|
of the record_fix field. Simplify error messages for unexpected
|
|
|
|
|
|
symbolic operands.
|
|
|
|
|
|
(set_expr_symbol_offset_diff): Delete.
|
|
|
|
|
|
|
2006-01-31 16:19:41 +00:00
|
|
|
|
2006-01-31 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
|
|
|
|
|
|
|
2006-01-31 Paul Brook <paul@codesourcery.com>
Richard Earnshaw <rearnsha@arm.com>
* gas/config/tc-arm.c: Use arm_feature_set.
(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
New variables.
(insns): Use them.
(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
feature flags.
(arm_legacy_option_table, arm_option_cpu_value_table): New types.
(arm_opts): Move old cpu/arch options from here...
(arm_legacy_opts): ... to here.
(md_parse_option): Search arm_legacy_opts.
(arm_cpus, arm_archs, arm_extensions, arm_fpus)
(arm_float_abis, arm_eabis): Make const.
* include/opcode/arm.h: Use ARM_CPU_FEATURE.
(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
(arm_feature_set): Change to a structure.
(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
ARM_FEATURE): New macros.
2006-01-31 14:11:13 +00:00
|
|
|
|
2006-01-31 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c: Use arm_feature_set.
|
|
|
|
|
|
(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
|
|
|
|
|
|
arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
|
|
|
|
|
|
fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
|
|
|
|
|
|
New variables.
|
|
|
|
|
|
(insns): Use them.
|
|
|
|
|
|
(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
|
|
|
|
|
|
md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
|
|
|
|
|
|
arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
|
|
|
|
|
|
s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
|
|
|
|
|
|
feature flags.
|
|
|
|
|
|
(arm_legacy_option_table, arm_option_cpu_value_table): New types.
|
|
|
|
|
|
(arm_opts): Move old cpu/arch options from here...
|
|
|
|
|
|
(arm_legacy_opts): ... to here.
|
|
|
|
|
|
(md_parse_option): Search arm_legacy_opts.
|
|
|
|
|
|
(arm_cpus, arm_archs, arm_extensions, arm_fpus)
|
|
|
|
|
|
(arm_float_abis, arm_eabis): Make const.
|
|
|
|
|
|
|
2006-01-26 05:21:43 +00:00
|
|
|
|
2006-01-25 Bob Wilson <bob.wilson@acm.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
|
|
|
|
|
|
|
2006-01-20 17:22:50 +00:00
|
|
|
|
2006-01-21 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
|
|
|
|
|
|
in load immediate intruction.
|
|
|
|
|
|
|
2006-01-20 16:57:09 +00:00
|
|
|
|
2006-01-21 Jie Zhang <jie.zhang@analog.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y (value_match): Use correct conversion
|
|
|
|
|
|
specifications in template string for __FILE__ and __LINE__.
|
|
|
|
|
|
(binary): Ditto.
|
|
|
|
|
|
(unary): Ditto.
|
|
|
|
|
|
|
include/elf/ChangeLog:
Introduce TLS descriptors for i386 and x86_64.
* common.h (DT_TLSDESC_GOT, DT_TLSDESC_PLT): New.
* i386.h (R_386_TLS_GOTDESC, R_386_TLS_DESC_CALL, R_386_TLS_DESC):
New.
* x86-64.h (R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL,
R_X86_64_TLSDESC): New.
bfd/ChangeLog:
Introduce TLS descriptors for i386 and x86_64.
* reloc.c (BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC,
BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_GOTPC32_TLSDESC,
BFD_RELOC_X86_64_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL): New.
* libbfd.h, bfd-in2.h: Rebuilt.
* elf32-i386.c (elf_howto_table): New relocations.
(R_386_tls): Adjust.
(elf_i386_reloc_type_lookup): Map new relocations.
(GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros.
(GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros.
(struct elf_i386_link_hash_entry): Add tlsdesc_got field.
(struct elf_i386_obj_tdata): Add local_tlsdesc_gotent field.
(elf_i386_local_tlsdesc_gotent): New macro.
(struct elf_i386_link_hash_table): Add sgotplt_jump_table_size.
(elf_i386_compute_jump_table_size): New macro.
(link_hash_newfunc): Initialize tlsdesc_got.
(elf_i386_link_hash_table_create): Set sgotplt_jump_table_size.
(elf_i386_tls_transition): Handle R_386_TLS_GOTDESC and
R_386_TLS_DESC_CALL.
(elf_i386_check_relocs): Likewise. Allocate space for
local_tlsdesc_gotent.
(elf_i386_gc_sweep_hook): Handle R_386_TLS_GOTDESC and
R_386_TLS_DESC_CALL.
(allocate_dynrelocs): Count function PLT relocations. Reserve
space for TLS descriptors and relocations.
(elf_i386_size_dynamic_sections): Reserve space for TLS
descriptors and relocations. Set up sgotplt_jump_table_size.
Don't zero reloc_count in srelplt.
(elf_i386_always_size_sections): New. Set up _TLS_MODULE_BASE_.
(elf_i386_relocate_section): Handle R_386_TLS_GOTDESC and
R_386_TLS_DESC_CALL.
(elf_i386_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P.
(elf_backend_always_size_sections): Define.
* elf64-x86-64.c (x86_64_elf_howto): Add R_X86_64_GOTPC32_TLSDESC,
R_X86_64_TLSDESC, R_X86_64_TLSDESC_CALL.
(R_X86_64_standard): Adjust.
(x86_64_reloc_map): Map new relocs.
(elf64_x86_64_rtype_to_howto): New, split out of...
(elf64_x86_64_info_to_howto): ... this function, and...
(elf64_x86_64_reloc_type_lookup): ... use it to map elf_reloc_val.
(GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros.
(GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros.
(struct elf64_x86_64_link_hash_entry): Add tlsdesc_got field.
(struct elf64_x86_64_obj_tdata): Add local_tlsdesc_gotent field.
(elf64_x86_64_local_tlsdesc_gotent): New macro.
(struct elf64_x86_64_link_hash_table): Add tlsdesc_plt,
tlsdesc_got and sgotplt_jump_table_size fields.
(elf64_x86_64_compute_jump_table_size): New macro.
(link_hash_newfunc): Initialize tlsdesc_got.
(elf64_x86_64_link_hash_table_create): Initialize new fields.
(elf64_x86_64_tls_transition): Handle R_X86_64_GOTPC32_TLSDESC and
R_X86_64_TLSDESC_CALL.
(elf64_x86_64_check_relocs): Likewise. Allocate space for
local_tlsdesc_gotent.
(elf64_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPC32_TLSDESC and
R_X86_64_TLSDESC_CALL.
(allocate_dynrelocs): Count function PLT relocations. Reserve
space for TLS descriptors and relocations.
(elf64_x86_64_size_dynamic_sections): Reserve space for TLS
descriptors and relocations. Set up sgotplt_jump_table_size,
tlsdesc_plt and tlsdesc_got. Make room for them. Don't zero
reloc_count in srelplt. Add dynamic entries for DT_TLSDESC_PLT
and DT_TLSDESC_GOT.
(elf64_x86_64_always_size_sections): New. Set up
_TLS_MODULE_BASE_.
(elf64_x86_64_relocate_section): Handle R_386_TLS_GOTDESC and
R_386_TLS_DESC_CALL.
(elf64_x86_64_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P.
(elf64_x86_64_finish_dynamic_sections): Set DT_TLSDESC_PLT and
DT_TLSDESC_GOT. Set up TLS descriptor lazy resolver PLT entry.
(elf_backend_always_size_sections): Define.
binutils/ChangeLog:
Introduce TLS descriptors for i386 and x86_64.
* readelf.c (get_dynamic_type): Handle DT_TLSDESC_GOT and
DT_TLSDESC_PLT.
gas/ChangeLog:
Introduce TLS descriptors for i386 and x86_64.
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
displacement bits.
(build_modrm_byte): Set up zero modrm for TLS desc calls.
(lex_got): Handle @tlsdesc and @tlscall.
(md_apply_fix, tc_gen_reloc): Handle the new relocations.
ld/testsuite/ChangeLog:
Introduce TLS descriptors for i386 and x86_64.
* ld-i386/i386.exp: Run on x86_64-*-linux* and amd64-*-linux*.
Add new tests.
* ld-i386/pcrel16.d: Add -melf_i386.
* ld-i386/pcrel8.d: Likewise.
* ld-i386/tlsbindesc.dd: New.
* ld-i386/tlsbindesc.rd: New.
* ld-i386/tlsbindesc.s: New.
* ld-i386/tlsbindesc.sd: New.
* ld-i386/tlsbindesc.td: New.
* ld-i386/tlsdesc.dd: New.
* ld-i386/tlsdesc.rd: New.
* ld-i386/tlsdesc.s: New.
* ld-i386/tlsdesc.sd: New.
* ld-i386/tlsdesc.td: New.
* ld-i386/tlsgdesc.dd: New.
* ld-i386/tlsgdesc.rd: New.
* ld-i386/tlsgdesc.s: New.
* ld-x86-64/x86-64.exp: Run new tests.
* ld-x86-64/tlsbindesc.dd: New.
* ld-x86-64/tlsbindesc.rd: New.
* ld-x86-64/tlsbindesc.s: New.
* ld-x86-64/tlsbindesc.sd: New.
* ld-x86-64/tlsbindesc.td: New.
* ld-x86-64/tlsdesc.dd: New.
* ld-x86-64/tlsdesc.pd: New.
* ld-x86-64/tlsdesc.rd: New.
* ld-x86-64/tlsdesc.s: New.
* ld-x86-64/tlsdesc.sd: New.
* ld-x86-64/tlsdesc.td: New.
* ld-x86-64/tlsgdesc.dd: New.
* ld-x86-64/tlsgdesc.rd: New.
* ld-x86-64/tlsgdesc.s: New.
2006-01-18 21:07:51 +00:00
|
|
|
|
2006-01-18 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Introduce TLS descriptors for i386 and x86_64.
|
|
|
|
|
|
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
|
|
|
|
|
|
BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
|
|
|
|
|
|
BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
|
|
|
|
|
|
(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
|
|
|
|
|
|
BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
|
|
|
|
|
|
displacement bits.
|
|
|
|
|
|
(build_modrm_byte): Set up zero modrm for TLS desc calls.
|
|
|
|
|
|
(lex_got): Handle @tlsdesc and @tlscall.
|
|
|
|
|
|
(md_apply_fix, tc_gen_reloc): Handle the new relocations.
|
|
|
|
|
|
|
2006-01-11 17:39:50 +00:00
|
|
|
|
2006-01-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Fixes for building on 64-bit hosts:
|
|
|
|
|
|
* config/tc-avr.c (mod_index): New union to allow conversion
|
|
|
|
|
|
between pointers and integers.
|
|
|
|
|
|
(md_begin, avr_ldi_expression): Use it.
|
|
|
|
|
|
* config/tc-i370.c (md_assemble): Add cast for argument to print
|
|
|
|
|
|
statement.
|
|
|
|
|
|
* config/tc-tic54x.c (subsym_substitute): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c (md_assemble): Use a union to convert the
|
|
|
|
|
|
opindex field of fr_cgen structure into a pointer so that it can
|
|
|
|
|
|
be stored in a frag.
|
|
|
|
|
|
* config/tc-mn10300.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
|
|
|
|
|
|
types.
|
|
|
|
|
|
* config/tc-v850.c: Replace uses of (int) casts with correct
|
|
|
|
|
|
types.
|
|
|
|
|
|
|
2006-01-09 17:14:40 +00:00
|
|
|
|
2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2117
|
|
|
|
|
|
* symbols.c (snapshot_symbol): Don't change a defined symbol.
|
|
|
|
|
|
|
2006-01-03 05:56:15 +00:00
|
|
|
|
2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/2101
|
|
|
|
|
|
* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
|
|
|
|
|
|
a local-label reference.
|
|
|
|
|
|
|
2006-01-16 23:15:07 +00:00
|
|
|
|
For older changes see ChangeLog-2005
|
2002-01-07 12:12:47 +00:00
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|