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libretro/mame2003-plus-libretro:Current
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compare: libretro/mame2003-plus-libretro:master
libretro/mame2003-plus-libretro:master libretro/mame2003-plus-libretro:arcadez2003-patch-11 libretro/mame2003-plus-libretro:arcadez2003-patch-10 libretro/mame2003-plus-libretro:arcadez2003-patch-9 libretro/mame2003-plus-libretro:arcadez2003-patch-8 libretro/mame2003-plus-libretro:markwkidd-patch-1 libretro/mame2003-plus-libretro:arcadez2003-patch-7 libretro/mame2003-plus-libretro:arcadez2003-patch-6 libretro/mame2003-plus-libretro:arcadez2003-patch-5 libretro/mame2003-plus-libretro:arcadez2003-patch-4 libretro/mame2003-plus-libretro:cpu-clock-scale-setting-change libretro/mame2003-plus-libretro:arcadez2003-patch-3 libretro/mame2003-plus-libretro:arcadez2003-patch-2 libretro/mame2003-plus-libretro:arcadez2003-patch-1 libretro/mame2003-plus-libretro:Call2
libretro/mame2003-plus-libretro:Current
94 Commits
arcadez2003-patch-8 ... master
Author SHA1 Message Date
mahoneyt944 dff0ba6365 segas32 use opaque blending by default - dbzvrvs backgrounds working. (#2211) 
* Update segas32.c

* Update segas32.c

* Update .gitlab-ci.yml

* Update segas32.c

* Update segas32.h

* Update segas32.c

* Update segas32.c

* Update .gitlab-ci.yml
 2026-11-07 07:35:08 -05:00
arcadez2003 1035485897 Merge pull request #2210 from libretro/arcadez2003-patch-11 
3on3dunk
 2026-11-06 21:07:03 +00:00
arcadez2003 a0e0e75905 Merge pull request #2209 from libretro/arcadez2003-patch-10 
3on3 Dunk Madness video code
 2026-11-06 21:06:47 +00:00
arcadez2003 a45b70e19e Merge pull request #2208 from libretro/arcadez2003-patch-9 
Attempt to support 3on3 Dunk Madness
 2026-11-06 21:06:32 +00:00
arcadez2003 ea291bf560 3on3dunk 2026-11-06 21:02:07 +00:00
arcadez2003 0dd483f4c0 3on3 Dunk Madness video code 2026-11-06 20:59:50 +00:00
arcadez2003 7f35678403 Attempt to support 3on3 Dunk Madness 
Ported from AdvanceMAME
 2026-11-06 20:58:34 +00:00
zanacandClaude Opus 5.5 888122871c namcos22: Time Crisis light gun as MAME, with crosshair (#2207) 
- the gun ports use MAME's position ranges (X 68-694, Y 43-284), what
  the game reads, instead of 8-bit values scaled in the handler;
- the screen edges read as off screen, as MAME: before, an off-screen
  position (1 or 254) reached the game as a shot at the edge;
- the crosshair (core option) is drawn where the game sees the shot,
  as MAME's PORT_CROSSHAIR(X/Y, 1.0, 0.0, 0).


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-06 03:33:05 -05:00
arcadez2003 d41198a39d Mention Akka Arrh can now be played using this core 2026-11-05 21:56:10 +00:00
zanacandClaude Opus 5.5 34988bc120 Namco System 22 / Super System 22 from current MAME (#2206) 
Replaces the old namcos22 driver (no DSPs, every game not working) with a
C89 backport of the current MAME driver:

- new Namco C71 core (TMS320C25 with internal ROM) for the master and
  slave DSPs: MAME's tms320c2x instructions, a page table memory system;
- Super System 22 (68EC020, M37710 MCU with C352 and MB87078 volume) and
  System 22 (68020, C74 MCU with internal BIOS);
- the video: display list simulation, z-sorted polygons and sprites,
  text layer, fog, fades, alpha, spot RAM, gamma; MAME's rasterizer
  rules, single threaded, with 1/z every 8 pixels and fast paths;
- the "Threaded Video" option (was "ST-V Threaded Video") draws the
  frame in bands on 2 to 4 threads (3D scene, text layer, mix, gamma),
  same picture;
- M37710: timer A event counters count up or down (output pin or up/down
  register, as MAME), for the Prop Cycle pedal and the Armadillo Racing
  trackball;
- C352: optional routing of the four outputs to the stereo stream (rear
  speakers, cabinet speakers), as current MAME maps them to stereo; off
  unless a driver asks for it, System 11/12 unchanged;
- game I/O as MAME: driving games and Cyber Commando on System 22,
  Alpine Racer steplock motor, Alpine Surfer ROM banking, Armadillo
  Racing trackball, default EEPROMs.

System 22 sets (namcoc74 BIOS): ridgerac, ridgeraca, ridgeracb,
ridgeracc, ridgeracj, ridgera2, ridgera2j, ridgera2ja, ridgera28,
cybrcomm, raverace, raveracej, raveraceja, acedrive, victlap, victlapa,
victlapj.

Super System 22 sets: alpinerd, alpinerc, alpinerjc, airco22b, cybrcycc,
cybrcyccj, dirtdash, dirtdasha, dirtdashb, dirtdashj, timecris,
timecrisa, timecrisj, propcycl, propcyclj, alpines, tokyowar, tokyowarj,
aquajet, alpinr2b, alpinr2a, adillor, adillorj.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-05 13:08:58 -05:00
zanacandClaude Opus 5.5 af0f783b1e Cyclone mode: DrZ80(snd) also takes the unflagged sound Z80; default list cleanup (#2157) (#2205) 
DrZ80(snd) and Cyclone+DrZ80(snd) only replaced the Z80s flagged
CPU_AUDIO_CPU, and many sound Z80s are not flagged (CPS2, Taito,
Toaplan, the Mega Drive based boards...): those games kept the C Z80
with no sign in the log.

Now, on a board with no flagged CPU whose first CPU is not a Z80, its
first Z80 is taken as the sound CPU too, except where DrZ80 can't run
it: a Z80 with a daisy chain (DrZ80 has none), the CPS1 QSound Z80
(Kabuki-encrypted opcodes) and the Tatsumi sound Z80 (Round Up 5
hangs). The log says which Z80s are replaced and which are kept.

frontend_list.h: removed the entries that could do nothing, with the
same result for every game: 82 names not in the core, 531 games with
neither a 68000 nor a Z80, and a second zzyzzyx2 entry never reached.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-05 03:36:34 -05:00
arcadez2003 b8afd2ddde Sigh this time surely 2026-11-04 22:48:46 +00:00
arcadez2003 00e1f93fc6 Fix build 2026-11-04 22:42:20 +00:00
arcadez2003 ae8299f57c Rename akkaarrh to akkaarrh.c 2026-11-04 22:32:18 +00:00
arcadez2003 11b6dd20a8 FFS try that again 2026-11-04 22:14:36 +00:00
arcadez2003 b6b9bae087 akkaarrh 2026-11-04 20:51:10 +00:00
arcadez2003 9f568e318b Declare akkaarrh 2026-11-04 20:46:46 +00:00
arcadez2003 5a0269a6fd New Driver Atari's Akka Arrh prototype 
With thanks to AdvanceMAME
 2026-11-04 20:44:15 +00:00
zanacandClaude Opus 5.5 91f2f15e15 ST-V: Cotton Boomerang English translation (cottonbme) (#2204) 
Bootleg clone set of cottonbm in English: the stage result lines, the
character select panels, the full names of the characters in the
attract mode, and the translation credit under the title logo. The game always
runs in its Japanese (translated) mode, so the whole translation shows
with every BIOS region. The four changed chips are built from cottonbm
with github.com/zanac/cottonbm, which writes a complete cottonbme.zip.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-04 01:38:45 -05:00
zanacandClaude Opus 5.5 b974d670cc Golden Axe: the FD1094 sets goldnaxb, goldnaxc and goldnaxj working (#2203) 
goldnaxb (317-0110), goldnaxc (317-0122) and goldnaxj (317-0121) are the
Golden Axe sets with the FD1094 encrypted 68000 (MAME goldnaxe1,
goldnaxeu, goldnaxej). They were marked not working.

- The decryption keys are added to the sets and the code is decrypted
  with the FD1094 module already used by Cotton (C 68000 core).
- They get their own memory maps: the ones of goldnaxa (171-5797 board)
  and goldnaxe (171-5704 board) without the handlers that stand in for
  the 8751 in the work RAM; these sets have no 8751, they read the I/O
  and send the sound commands themselves.
- The 315-5195 memory mapper, as far as these games use it: register 3 is
  the sound command, and every frame the program moves the sprite RAM to
  one of 8 bases (0x200000-0x900000), so the sprite RAM follows the base
  in register 0x19. The mapper registers are in the save states.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 20:16:15 -05:00
zanacandClaude Opus 5.5 ab52620ee4 ST-V and Model 2: save states, run-ahead and netplay; SCSP slot allocation (#2202) 
Save states on ST-V were broken on master: a loaded state, a run-ahead
rewind or a netplay resync did not continue the emulation the same way.
Model 2 was almost right (hpyagu98 differed after a rewind).

Core:
- SH-2: each CPU registers its own state (both used to register the
  boot buffer), and the rest of the CPU is saved: delay slot, divider,
  interrupt queue and lines, on-chip registers, FRT, DMA timers.
- Memory banks are registered after the driver init, where the drivers
  point them (ST-V work RAM was saved from the wrong buffer).
- cpu_spinuntil_time / cpu_yielduntil_time trigger counters are saved.
- The crosshair idle timer is saved (the crosshair hid at another frame
  after a load or a rewind).

ST-V:
- SMPC, SCU registers and interrupts, SCU DSP, I/O, sound CPU control,
  CD block scalars, VDP1 clipping, CRTC line counter are saved.
- The RTC starts from the host date and time at boot and then follows the
  emulated time (it read the host clock at every query, so two runs from
  the same state could read different times).

SH-2 recompiler: the polling loop skip counted a whole chain of blocks
that came back to the loop start as one loop iteration, skipping the
writes and calls in between. It now only skips when the block ran one
turn of the loop. Results with a warm or a cold block cache are now the
same.

Model 2: the polygon count of the last display list is saved.

SCSP (issue #2194, regression of #2198): a key off on a slot that had
already stopped (a one-shot sample past its end) left its envelope at the
level it stopped at, because a stopped slot no longer updates it. The
monitor register (0x408) then showed the slot as still sounding, the
sound drivers took it for busy and, after a while, put every new note on
the one slot left. Cotton Boomerang lost all but the drums at the first
boss, Winter Heat's voices cut each other from the first attract demo on.
Such a slot now ends its release at once.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 12:04:40 -05:00
zanacandClaude Opus 5.5 7ed1af5370 Model 2: faster 3D, 2D layers, SCSP DSP, i960 and SHARC (#2201) 
Renderer:
- texture sheets also kept one byte per texel, the texel fetch reads them
  straight (inlined, an opaque and a translucent span)
- the pixel of each texel worked out once for the colours of a polygon
- translucent texel pairs packed from a table; a translucent pixel sure to
  be discarded skips the next mipmap level
- 3D pixels kept as the 15-bit colour of the bitmap
- the tile layers drawn straight into the bitmap: the polygons are only
  drawn over the tile pixels behind them, no copy passes

System 24 tiles (rgb version, Model 1 and 2): eight pixels at a time, a
group all of the layer's priority without a test each, the last pixels of
the line as groups too.

SCSP DSP: the steps that only multiply and accumulate on a short path,
decoded when MPRO changes; the delay RAM float packing from a table.

i960: opcodes read straight from the memory block of the last fetch
(memory_get_read_range), execute_op inlined.

SHARC: no DMA call while channels 6 and 7 are idle.

AArch64 (QEMU, instructions per frame): fvipers -26%, doa -28%, daytona
-31%, vf2 -25%. Frames and audio are the same on the Model 2 sets, the
ST-V sets and in save states.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-03 02:19:01 -05:00
arcadez2003 35fee378f5 Merge pull request #2200 from zanac/stv-perf 
ST-V: faster VDP2 and VDP1 drawing, SH-2 polling loops skipped, FTCSR as in MAME
 2026-11-02 23:27:07 +00:00
VanniandClaude Opus 5.5 40dab5fe44 ST-V: faster VDP2 and VDP1 drawing, SH-2 polling loops skipped, FTCSR as in MAME 
VDP2 tiles:
- vdp2_drawgfx_alpha drew every pixel through vdp2_window_process; with a
  window it now draws the runs of each line the windows show, from the line
  cache of vdp2_drawgfx_transpen (same pixels), and with no window it
  copies without checks. Both work out the window key once per tile and
  check the cached line inline.
- Each decoded element keeps two masks of its rows (a pixel other than
  pen 0; no pen 0). With transparency vdp2_drawgfx_transpen skips tiles
  and rows of pen 0 only and copies whole the rows without it.

VDP1 sprites: without color calculation draw_sprites walks the window runs
of the line instead of calling vdp2_window_process for every pixel.

SH-2:
- Only a read that includes FRC resyncs it (MAME frc_r); TIER and FTCSR
  reads (MAME ftcsr_r) do not.
- The recompiler skips the iterations of polling loops that only read, as
  it already did for the SGL idle loop: a block that starts with a short
  loop back to itself which leaves every register as it found it and read
  only RAM or TIER/FTCSR repeats the same iteration until the end of the
  timeslice, so those iterations are counted at once.

Makefile (unix): -fvisibility=hidden, only retro_* leaves the library.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-11-02 22:34:25 +01:00
arcadez2003 cc4bfcdf71 Merge pull request #2198 from zanac/stv-sound-2194 
SCSP sound for ST-V and Model 2: voices, timers and interrupts from current MAME, Batman Forever RAX board
 2026-11-02 19:30:41 +00:00
VanniandClaude Opus 5.5 93b073496c ST-V sound: SCSP voices from current MAME, Batman Forever RAX board 
SCSP (also used by Model 2):
- The slot engine from current MAME: key off goes to the release, the
  envelope tables and the dB curve of the decay, pitch, interpolation,
  the four loop modes, FM from the ring buffer, noise (SSCTL), SBCTL,
  LPSLNK, STWINH/SDIR; 8-bit samples read in big-endian byte order.
- The monitor register 0x408 returns CA, SGC and EG of the slot set in
  MSLC: the sound drivers look there for a free slot, and Winter Heat
  played every voice on slot 0, each one cutting the previous.
- Real timers for timers A, B and C, as in MAME: counting them with the
  generated samples delayed every interrupt until the next stream update.
- Interrupts as in MAME: each source raises its own level until it is
  acknowledged in SCIRE, and an acknowledged expired timer is pending
  again with no new interrupt. Reading MIBUF drops the MIDI interrupt:
  left raised, the sound CPU took it again on an empty FIFO and read
  stale bytes as MIDI data, which broke music commands in Model 2
  (Fighting Vipers, Dead or Alive, Manx TT).
- The DMA used the common registers 0x412 words past them, inside the
  slots: now as in MAME.
- The common registers are 0x400-0x42f only (0x500 is not a mirror),
  the ring buffer at 0x600 can be read and written, the LFO saw wave and
  rate as in MAME.
- ST-V: a 16-bit access of the SH-2 touches only its half of the SCSP
  registers.

Batman Forever: the Acclaim RAX sound board (ADSP-2181), moved from zn.c
to sndhrdw/acclaim_rax.c and shared by NBA Jam Extreme and Batman
Forever, which writes its commands to 0x04800000 as in MAME.

docs/sega-model2.md: the MIDI interrupt of the sound link.

Fixes #2194.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-11-02 18:47:50 +01:00
GoodLuckTrying (Wolfric) 4930bf5be7 Ghosts'n Goblins: Princess Prin Prin Edition Hacks (#2196) 
* Add files via upload

* Add files via upload
 2026-11-02 07:41:43 -05:00
zanacandClaude Opus 5.5 6d162f313c ST-V: critcrsh hammer on the right input ports, lightgun crosshair (#2197) 
critcrsh / tatacot: the hammer was read from input ports 10 and 11,
which don't exist (the lightgun ports are 7 and 8), so the game always
saw it in the top left corner. The lightgun ports default to the
centre, since in this core the lightgun moves from the default value,
and the crosshair is drawn as in MAME. Fixes #2195.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-02 07:41:07 -05:00
mahoneyt944 e455f1783a Add files via upload 2026-11-01 07:01:14 -05:00
zanacandClaude Opus 5.5 9275a6a775 ST-V: trackball for the medal games, max geometry from the screen size (#2193) 
- techbowl, patocar, skychal, supgoal: trackball on the 315-5649 port G
  counters, as in MAME (mode register bit 7, counter select and byte in
  port G, auto-increment on read, reset when bit 7 is clear). New input
  stvtrack with trackball X/Y. Fixes #2189.
- libretro video: the max geometry and the conversion buffer use the
  larger of the default visible area and the screen size for raster
  games, so ST-V frames up to 704x480 fit. Fixes #2190.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-01 06:50:07 -05:00
zanacandClaude Opus 5.5 4d5e7f3e17 Sega ST-V: faster video (VDP1 clear, VDP2 windows, tiles, sprites, rotation copy); no freeze on reset (#2192) 
Video, same results:
- vdp1_clear_framebuffer: rows filled as one or two runs, eight bytes at
  a time, instead of a masked index per pixel.
- VDP2 windows: the coordinates of each line cached for the whole screen
  update (one entry per line), and the runs of pixels each line shows for
  the current layer cached too; the tiles of a window layer are drawn in
  those runs instead of testing the windows on each pixel.
- Transparent tiles: four pixels tested at once, a transparent group is
  skipped.
- Sprites: in a run of zero frame buffer pixels, four skipped at once.
- vdp2_copy_roz_bitmap: the layer settings read once per line.

Reset (#2188): the machine's timers are freed at each reset, but
machine_init only allocated the SCU DMA, hopper and SMPC INTBACK timers
when its pointers were NULL, so after a reset it adjusted freed timers
and the timer list looped forever. They are allocated at each
machine_init, as the other drivers do.

Fixes #2188


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-11-01 02:04:12 -05:00
zanacandClaude Opus 5.5 b168882c39 SH-2 recompiler: compare for CMP/EQ on AArch64 (ST-V black screens) (#2187) 
jit_cmp() asked the flags of the compare with SLJIT_SET(cond & ~1). For
SLJIT_EQUAL that is SLJIT_SET(0), no flag at all: the x86 back ends
compare anyway, the AArch64 one does not, so CMP/EQ Rm,Rn and CMP/EQ
#imm,R0 set T from stale flags. The ST-V BIOS then took wrong branches
and games stayed on a black screen or ran with broken graphics with the
SH-2 Dynarec option on. The zero flag is now asked with SLJIT_SET_Z, as
the SH-3 recompiler already does.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-31 15:46:16 -04:00
zanacandClaude 4125e63480 CV1000: faster SH-3 bus timing and screen copy, same results (#2186) 
The cache and bus timing of every SH-3 data access (and of the
instruction fetch sampled with it) was most of the time spent on ARM.
Same output, cycle for cycle:

- fast RAM regions found through a 64 KB page table
- the time of the last bus access kept in 32 bits, relative to the
  start of the timeslice (exact up to 2^30 cycles, "far" beyond, where
  the timing only compares with small counts); the 64-bit value is
  still the one saved in the states
- the tag of the most recently used way of each cache block kept next
  to it, rebuilt eagerly instead of checked on every access
- the cycle count kept in locals across the fetch and data penalties
- the timing fields at the start of the CPU state
- the screen copy in at most two runs per line, with SSE2/NEON


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-31 14:22:28 -04:00
zanacandClaude Opus 5.5 90149e76d2 Sega ST-V: cotton2e and puyosune, English translation bootlegs (#2185) 
- cotton2e: Cotton 2 with the story scenes, ending and staff roll,
  continue screen hints, prologue and character profiles in English,
  from the English fan translation of the Saturn port. All eight ROMs
  differ from cotton2; https://github.com/zanac/Cotton2 builds them.
- puyosune: Puyo Puyo Sun with the win quotes, story scenes, endings,
  menus and in-game lettering in English, from the Puyo Nexus English
  translation of the Windows version. Three ROMs differ from puyosun;
  https://github.com/zanac/sega_st-v_puyosune builds them.

znpwfve (All Japan Pro-Wrestling, English) is already in master.


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-31 03:13:49 -04:00
zanacandClaude Opus 5.5 273f904d7d Sega ST-V: driver, VDP1/VDP2 video and SCU from current MAME, optional SH-2 recompiler and threaded video (#2124) 
- Driver, SCU (DMA, interrupts, timers, DSP), SMPC, MINIT/SINIT, EEPROM
  and the protection chips as current MAME; the current MAME sets.
- VDP1/VDP2 video as current MAME's (one stvvid.c), with exact speedups:
  partial redraw of the rotation plane cache, rotation copy, sprite
  passes, window evaluation once per line.
- SH-2 recompiler on the bundled sljit (x86, x86-64, ARM32, ARM64; the
  "SH-2 Dynarec" core option, off by default): blocks with chaining,
  page tables for direct memory access, memory handlers called from the
  blocks; the SGL idle loop is skipped exactly; context switch by
  pointer. Same output as the interpreter on all the sets.
- "ST-V Threaded Video" core option (off by default): the screen drawn
  in strips by 2-4 threads (libretro-common rthreads, where thread-local
  storage is native), same output.

Two more sets of Zen Nippon Pro-Wrestling Featuring Virtua, both on the
Taiwan BIOS (the core selects it):
- znpwfvt: All Japan Pro-Wrestling Featuring Virtua (Taiwan), as in
  current MAME.
- znpwfve: English translation (bootleg) on the Taiwan program, with the
  graphics the English mode left in Japanese redrawn; the ROMs are built
  from the original ones by https://github.com/zanac/znpwfvt


Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX

Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-30 21:57:04 -04:00
mahoneyt944 df60f6466d F1en fix attract sound - JD (#2184) 2026-10-30 12:28:35 -04:00
zanaczanacClaude Opus 5.5
 		b47967f1f2 Sega System E MC-8123, Super Hang-On, Enduro Racer backports; Zero Team save states (#2183) 
System E (segasyse.c, segasyse_vidhrdw.c, mc8123.c, sn76496.c):
- MC-8123 key based decryption from current MAME: Opa Opa (317-0042)
  and Fantasy Zone II (317-0057) now run (MAME set names and keys)
- 315-5124 VDP as in MAME: per VDP status, line counter and frame
  interrupts (only VDP #1 drives /INT), output levels, per-line CRAM and
  scroll latching, front layer backdrop, mode 4 sprites
- Sega PSG clock (10.738635 MHz / 3) and noise
- trackball state saved (Riddle of Pythagoras, Megumi Rescue)

Super Hang-On (outrun.c): backport of MAME segaorun for shangon,
shangon1, shangon2, shangon3, shangon3d, shangonle (FD1089B, memory
mapper, interrupt timing, ADC, YM2151 + SegaPCM).

Enduro Racer (sharrier.c): backport of MAME segahang: FD1089B, both
8255 PPIs (mode 2 sound handshake), ADC0804, sub CPU mirrors, YM2151 and
YM2203 sound boards, Space Harrier sprites and road. Sets enduror,
endurora, endurorb, enduror1, endurobl, endurob2, endurord, enduror1d.
The Hang-On conversions shangonrb and shangonrb2 (old shangonb) use the
same code with the Hang-On main board map.

Sound:
- SegaPCM: register layout as in MAME (current address at 0x84,
  loop at 0x04), 7-bit volumes, 8-voice discrete mode, save states;
  Super Hang-On PCM pitch fixed
- Seibu sound: latches, IRQ vectors and bank saved (Zero Team save
  states, run ahead and netplay now work)


Claude-Session: https://claude.ai/code/session_014P4GcczkZTrzVfrRW8odFY

Co-authored-by: zanac <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-30 03:39:56 -04:00
zanacandClaude a1fb5c7993 Sega System C/C2 as in current MAME: segac2.c only C/C2, the Mega Drive part in machine/megadriv.c, 25 new sets (#2181) 
- machine/megadriv.c / includes/megadriv.h: the Mega Drive part shared by
  the Mega-Tech, Mega Play, bootleg, Y-BOX and Sun Mixing boards (the VDP
  interrupts, also used by System C/C2, the sound Z80 and its bus, the I/O,
  the machine drivers), moved out of segac2.c; the Mega-Tech / Mega Play
  BIOS VDP ports go to megatech.c, its interrupt to megaplay.c; dead code
  removed (the unused cart maps, inputs and I/O init)
- segac2.c: only System C/C2, with the sets, ROMs, titles, inputs and DIP
  switches of current MAME (57 sets instead of 32; puyopuyo/puyopuya/puyopuyb are now
  puyoj/puyoja/puyobl, columns2 and stkclmns (Japan) are now column2j and
  stkclmnsj, with the World sets as parents)
- the protection chip as the EPM5032 logic of each game of current MAME
  (identical to the old tables where they were real; Ribbit!, Poto Poto and
  Puyo Puyo 2 had fake tables and workarounds)
- the alternate palette mode of Ribbit! and Twin Squash (control bit 2),
  through palette lookups in the VDP, instead of watching Ribbit! ROM reads
- the 68000 at XL2/6 (8.95 MHz) and the refresh at 59.92 Hz as in current
  MAME (it was XL2/7 and 60 Hz); V-INT and H-INT held until the 68000
  acknowledges them, as on the board
- YM2612/YM3438 (shared): the busy flag for 192 clocks after a data write,
  and a timer started long after its last overflow runs a whole period, as
  in current MAME
- Mega Play: the BIOS VDP V-INT about 12 lines after the Mega Drive VBLANK,
  as in current MAME (Tecmo World Cup could stay on a black screen)
- Mega Play / System E: the BIOS VDP tile lines read byte by byte (wrong
  colours on big-endian hosts)
- the address mirrors, the battery-backed work RAM (0xff filled), the coin
  meters on the I/O chip, the Waku Waku Marine / Anpanman wheel
- save states: the alternate palette mode and the Bloxeed YM3438 kludge
- metadata/mame2003-plus.xml, CHANGELOG.md


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-30 03:39:39 -04:00
zanacandClaude d7117cdcdc Save states: exact load for Ms. Pac-Man, SNK, Bubble Bobble, OPL, SCSP and Sega Model 2 (#2182) 
- mspacman: the mapped ROM (decoded set or boot ROM)
- snk.c: the sound command/busy register, the sprite blink parity, the
  tile cache marked dirty after a load
- fmopl.c: the whole YM3812/YM3526/Y8950 state (channels, operators,
  envelopes, LFO, noise, timers, status, Delta-T ADPCM); replaces the
  register replay of #2045 (3812intf.c back to its earlier version)
- scsp.c: chip registers, slots, LFOs, DSP, timers, MIDI FIFOs, DMA
- model2: which CPU waits on the i960/copro FIFOs, the SCSP IRQ line
- bublbobl: ROM bank, display enable, sound NMI, MCU port latches
- m6800.c: the 6801/6803/63701 internal registers (ports, timer, TCSR,
  RAM control, WAI state)
- mb86233.c: the stall flag


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-30 02:47:53 -04:00
arcadez2003 0ad96d5104 Merge pull request #2180 from zanac/z80-busyloop 
Z80: the delay-loop shortcut counts the DEC cycles
 2026-10-29 22:11:06 +00:00
Claude f80f7223f4 Z80: the delay-loop shortcut counts the DEC cycles of each skipped iteration 
The TIME_LOOP_HACKS shortcut skips the iterations of a
DEC rr / LD A,r / OR r / JR NZ (or JP NZ) delay loop by burning their
cycles in one go. Each skipped iteration runs four opcodes (R is
advanced by 4), but only LD, OR and the jump were counted: the DEC was
left out, so every iteration took 6 cycles too few (20 instead of 26
with JR) and such delays ran about 23% short.

Count the DEC as well, for the BC, DE and HL loops with JR and JP.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-29 18:16:53 +01:00
SquirbieSquirbieClaude Opus 5.5
 		ff5f1bd024 mame-memory: leave read-only banks of 1 MiB or more out of the save state (#2178) 
register_banks() registers the RAM behind every bank that appears in a
memory map. Banks that only ever show up in read maps are ROM (the ST-V
cartridge bank, 48 MB, or the CAGE sound-board ROM banks, 2 + 16 MB),
but they were still copied into every save state, so states were
20-53 MB for those boards, and netplay, rewind and run-ahead keep many
states at once.

Remember whether each bank appears in a write map and skip a bank of
0x100000 bytes or more that never does. RAM banks and smaller banks are
unchanged, so the state layout of other drivers stays the same. An INFO
log line reports each skipped bank.

Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-29 06:08:50 -04:00
SquirbieSquirbieClaude Opus 5.5
 		dfc61f1689 H6280: register CPU state; battlera/actfancr: save HuC6270 VDC and driver state (#2177) 
The H6280 core registered nothing with the save-state system, and the
HuC6270 video chip of the battlera board (VRAM, registers, palette,
scanline/IRQ bookkeeping) and the driver's port select / ADPCM toggle
were not registered either. After a state load the CPU kept running
from its own PC, registers, MMR bank map and timer, and the screen was
drawn from the old VRAM, so netplay guests saw a blank or diverging
screen and rewind / run-ahead diverged.

- h6280.c: register PPC/PC/SP/ZP/EA, A/X/Y/P, the 8 MMR registers, the
  IRQ mask, timer status/ack/value/load, extra cycles and the IRQ lines
  (plus NZ with LAZY_FLAGS) per CPU in h6280_init(), as m6809_init() does.
- battlera_vidhrdw.c: register VRAM, the 20 VDC registers, the VDC
  pointers and flags, last_line (was a function-local static) and the
  palette RAM; a postload handler marks everything dirty and rebuilds
  the palette.
- battlera.c: register control_port_select, msm5205next and the ADPCM
  toggle (was a function-local static) from a new DRIVER_INIT.

Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-29 06:06:22 -04:00
zanacandClaude c6a2aa4700 Genie / Y-BOX and Sun Mixing boards in their own drivers (megadriv_ybox.c, megadriv_sunmix.c), as in current MAME (#2179) 
Phase 2.4/5 of the Sega VDP / segac2.c clean-up: Puckman Pockimon and the
other Y-BOX games, and Super Bubble Bobble (Sun Mixing), move from
drivers/segac2.c to drivers/megadriv_ybox.c and drivers/megadriv_sunmix.c,
as in current MAME.

- Sets as in current MAME: puckpkmn is the Genie 2000 set of MAME, the old
  puckpkmn set is now its clone puckpkmnb; new jingling and topshoot.
  xmvsfmb (not working in MAME) is not added: no ROMs.
- The Y-BOX games run on the Mega Drive machine, as MAME's md_ntsc (they
  ran on the System C board): 68000, Z80, the YM3438 on the Z80 bus, I/O
  (no pads), the RAM mirrors, and the VDP interrupts and HBLANK status as
  on the real hardware (genesis_enable_iack). Songjiangyanyi Final waits
  on HBLANK to write the scroll of each line: it hung on a grey screen,
  it now works (imperfect graphics, as in MAME).
- Songjiangyanyi / Shuihu Feng Yun Zhuan protection as in MAME: two read
  back latches selected by A2 (it was a list of fixed addresses), the
  0x70001c value per game, the ROM address remapping at 0x600000 of
  Shuihu Feng Yun Zhuan (an address XOR while a value is latched: the
  data reads through a handler, the opcodes through an opbase handler).
- Jingling Jiazu / Puckman Pockimon: the ID at 0x4b2476 and 0x70001c.
- Top Shooter: the shared RAM inputs of the MCU (not emulated, as in MAME).
- Save states: the protection and remapping state.
- Metadata: mame2003-plus.xml, CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-29 06:00:09 -04:00
zanacandClaude 6266128ce8 Save states: the missing YM2203/YM2610/YM2612, MultiPCM and 6809 state (RunAhead, netplay) (#2176) 
Loading a state, and so every RunAhead or netplay rollback, put back an
incomplete sound chip or CPU, and the game went on differently from the
run that never loaded: the audio of the Mega Drive based boards, Neo Geo
and the YM2203 games diverged, and on the 6809 games the game itself.

OPN chips (sound/fm.c):
- The reset sets the L/R pan of all the channels (0xb4-0xb6) and clears
  0x30-0xb2 without storing them in REGS; the postload rewrites REGS, so
  a channel the game never panned itself was muted after a load (the DAC
  of the Bare Knuckle games). The reset values are now in REGS (YM2203,
  YM2608, YM2610, YM2612), and the YM2612 DAC select too.
- The postloads of the YM2608 and YM2610 skipped 0xb6 (pan, AMS, PMS of
  the 3rd channel of each bank), as the YM2612 one did before.
- The chip recomputes its phase steps and envelope rates only when a
  register asks for it, so they can lag behind the registers (e.g. after
  a 3 slot mode change). They are now saved as they are, with the key
  codes and the LFO step, instead of being remade from the registers. The
  YM2612 and YM2610 extra state is one shared block (OPN_EXT), now also
  used by the YM2203, which had none.
- The YM2612 DAC value is saved as it is: before the first write it is 0,
  which is not what the register gives (aladmdb).
- YM2610: the extra FM and SSG state was opt-in (only zn.c asked for it);
  it is now always saved (Neo Geo). The opt-in FM timers stay as they were.

SSG (sound/ay8910.c): the periods of the SSG of a YM chip are saved as they
were made; the register rewrite of the postload remade them with the
current clock. The YM2203 now saves the SSG extra state too.

MultiPCM (sound/multipcm.c): the sample pointer of a voice was remade from
the registers at load, without the bank and with the sample number of now,
not of the key on; it is saved as its offset in the ROM. The release
counter is saved too (Star Wars Arcade).

6809 family: the M6809 did not save the accumulators (D), the HD6309 D and
W; the M6809, HD6309 and Konami did not save the cycles of an interrupt
taken outside the execute loop.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 23:13:45 -04:00
zanacandClaude 9649c81834 Sega Mega Drive bootlegs in their own driver (drivers/megadriv_acbl.c), as in current MAME (#2175) 
Phase 2.3/5 of the Sega VDP / segac2.c clean-up: the coin-op bootlegs of
Mega Drive games move from drivers/segac2.c to drivers/megadriv_acbl.c,
with the board variants of current MAME, and the nine new sets we have
the ROMs for are added. The Mega Drive part stays shared with the other
Mega Drive based boards (includes/segac2.h).

- Moved: aladmdb, barek2ch, barek3mb, jparkmb, sonic2mb, sonic3mb,
  twinktmb (titles as in current MAME). Same code paths as before: frames
  and audio identical to the previous build.
- New: barekch, barek2mb, barek3mba, biohzdmb, bk3ssrmb, mk3mdb, srmdb,
  srssf2mb, ssf2mdb.
- The board variants of MAME: the version register, 6 button pads (MAME's
  TH counter with the 1.5ms timeout), the 3rd I/O port coins, the DIP
  switches at 0x770070 of the scrambled boards (and the coins at 0x770078
  of biohzdmb), the 6MB linear map of ssf2mdb, the PIC16C57 of barek2mb (emulated, with its latches; the
  68000 byte writes reach both halves of the bus as on the real CPU; T0
  is not connected), the simulated PIC of barek3mba.
- The new sets take V-INT / H-INT through the VDP interrupt enables, as on
  the real hardware (mk3mdb took a V-INT before its RAM vector was set
  and crashed); the moved sets keep the old mode.
- Big-endian hosts: the descrambling of the bootlegs uses BYTE_XOR_LE,
  and the PIC program of barek2mb is put in the host order the PIC core
  fetches its opcodes in.
- Mega Drive VDP: in H32 mode the sprite table base uses bit 0 of
  register 5 (AT9), as on the real VDP and in MAME; it was always masked
  as in H40 (ssf2mdb sets 0x6d in H32: the fighters were missing; the sprites
  of mt_bbros were garbled).
- PIC16C5x core: the PC wraps at the end of the program memory (the 2K
  parts start at 0x7ff and ran past the ROM), and the save states no
  longer register the ports and STATUS through R.picRAM before it is set
  (a NULL pointer: saving a game with a PIC crashed). They are in the data
  RAM, saved with the CPU memory.
- Save states: the pad, frame counter and PIC latch state.
- Metadata: mame2003-plus.xml (the bootleg entries regenerated),
  CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 23:10:27 -04:00
mahoneyt944 0e919473ca Add files via upload 2026-10-28 19:36:32 -04:00
arcadez2003 fa9eea238c Merge pull request #2173 from grant2258/Makefile 
Makefile (Auto-Dependency Generation)
 2026-10-28 20:59:25 +00:00
arcadez2003 ad755f06ad Merge pull request #2172 from grant2258/fixit 
add Sky Robo and Big Fighter mcu support
 2026-10-28 20:36:18 +00:00
Grantonius maximus 5b5d6f8a23 update gitignore 2026-10-28 20:33:19 +00:00
Grantonius maximus faa5ddf4e9 Makefile (Auto-Dependency Generation) 2026-10-28 20:32:18 +00:00
Grantonius maximus 46f354464a i dont want meee gold 2026-10-28 20:22:55 +00:00
Grantonius maximus 3b41adc749 add Sky Robo and Big Fighter mcu support 2026-10-28 20:19:28 +00:00
arcadez2003 bdfdc977c2 Mention Sky Robo / Tatakae! Big Fighter now works + credits 2026-10-28 20:05:19 +00:00
arcadez2003 5e593b6462 Sky Robo / Big Fighter fix MCU commands grant2258 2026-10-28 19:55:37 +00:00
zanacandClaude da7b539232 Sega Mega-Tech in its own driver (drivers/megatech.c), as in current MAME (#2170) 
Phase 2.2/5 of the Sega VDP / segac2.c clean-up: the Mega-Tech BIOS,
memory maps, inputs, machine drivers, ROMs and game drivers move from
drivers/segac2.c to drivers/megatech.c. The Mega Drive part stays shared
with the other Mega Drive based boards (includes/segac2.h); genesis_base
now starts from the plain cartridge map, each board sets its own.

- Sets, ROM names and dumps as in current MAME (good dumps of mt_bbros,
  mt_ggolf, mt_gng and mt_tetri), the instruction ROMs in the cart at
  0x300000, titles and years as in current MAME.
- The Master System carts run on the Mega Drive in Mark III mode, as in
  current MAME: the 68000 is off, the sound Z80 runs the cart with the
  Sega mapper, 8KB of RAM, the PSG and the VDP in mode 4 (the 315-5313
  variant of the 315-5124 core of MAME). Astro Warrior, Great Golf,
  Shinobi, After Burner and Parlour Games work; Great Soccer is a bad
  dump (as in MAME).
- The BIOS cart slots as in current MAME (the CXD1095 port E slot select,
  the banked RAM per slot, the 0x6000 bank latch and the 0x8000 window
  into the cart): the menu lists the cart in slot 1 only, not in all 8.
- The BIOS display: the 315-5246 224 line mode the menu uses (the MENU
  title was cut), drawn line by line, its own palette levels.
- The Mega Drive VDP line timing and partial updates count its own lines
  below the BIOS screen (segavdp line_scale; 1 for the other boards).
- The H32 games are centred in the 320 pixel screen.
- Mega Play: the BIOS overlay is transparent on colour 0 of both its
  palettes and covers its borders, as in current MAME (the boot logo
  screen was behind a green background).
- Crash fix: the 68000 writes to 0xa02000-0xa03fff went to the Mega Play
  BIOS RAM pointer, NULL on the other boards (Great Golf crashed). The
  Mega Play handler moves to drivers/megaplay.c.
- Save states: the Mega-Tech BIOS, the slots and the Mark III mode state.
- Metadata: mame2003-plus.xml (Mega-Tech entries regenerated), CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 15:22:08 -04:00
zanacandClaude eb11c10f08 Sega Mega Play in its own driver (drivers/megaplay.c), as in current MAME (#2168) 
Phase 2.1/5 of the Sega VDP / segac2.c clean-up: the Mega Play BIOS, memory
maps, inputs, machine driver, NVRAM, ROMs and game drivers move from
drivers/segac2.c to drivers/megaplay.c. The Mega Drive part (68000, sound
Z80, I/O chip, interrupts, sound interfaces, pads) stays shared with the
other Mega Drive based boards and is declared in includes/segac2.h; the
Mega Play interrupt acknowledge is enabled through genesis_enable_iack().

- Set names as in current MAME: mp_twc is now mp_twcup, the BIOS version 2
  ROM is epr-a15294.ic2; new clone mp_gaxe2a (Golden Axe II, original
  revision), as in MAME.
- The Mega Play save state registrations move with the BIOS; the unused
  BIOS variables (bios_game, bios_6204, bios_6402) are removed.
- Metadata: driver.c, mame2003-plus.xml (Mega Play entries regenerated),
  catver.ini, history.dat, CHANGELOG.md.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude <[email protected]>
 2026-10-28 15:00:00 -04:00
mahoneyt944 b3328713bb segas32 fix priority for dbzvrvs and f1lap (#2169) 2026-10-28 14:43:44 -04:00
arcadez2003 7ec7d077f2 Merge pull request #2167 from zanac/sega-vdp 
Phase 1: the Sega Mega Drive VDP (315-5313) as a shared module
 2026-10-28 14:13:14 +00:00
arcadez2003 5c6f346782 Come back to it later 2026-10-28 12:49:34 +00:00
arcadez2003 51e87e8a46 FFS Forgot this 2026-10-28 12:41:15 +00:00
arcadez2003 6926b424a6 Attempt to get the main and prot MCU's talking :) 2026-10-28 12:27:07 +00:00
Claude 122405bb79 Sega VDP (315-5313) as a module shared by System C/C2, Mega-Tech, Mega Play and System 18 
The Mega Drive VDP was part of the System C/C2 video code and System 18 used
it through file-static state and a few flags, so a change for one board could
reach the others. It is now a module, vidhrdw/segavdp.c:

- all its state is in one struct, cleared at every start;
- each user starts it with its own configuration (struct segavdp_interface):
  where the CRAM writes go (paletteram16, or the 64 System 18 colors set
  directly at 0x1800), the initial palette bases, the scanline base of the
  partial updates, the initial display enable, whether register 12 resizes
  the screen, and the interrupt callback for writes to registers 0/1;
- the boards use accessors (segavdp_get_reg, segavdp_set_palbank, ...);
- vidhrdw/segac2_vidhrdw.c keeps only the C/C2, Mega-Tech, Mega Play and
  bootleg video glue, vidhrdw/segas18.c the System 18 one.

Fixed on the way (state left over from a previous game in the same process):
the display enable and the Mega Play interrupt-acknowledge/HBLANK mode
(now also reset by the C/C2 machine init). The window X
position/width and the VBLANK flag are now in the save states. The dead
ddcrew/aquario VDP kludges of the old System 18 video are removed.

Save states loaded in a new instance (netplay, RunAhead with a second
instance) now continue exactly as the instance that saved them:
- Mega Drive based boards (drivers/segac2.c): the Z80 RAM and bus state
  (running flag, bank latch) and the Mega-Tech / Mega Play BIOS registers
  and RAM were not saved (mp_gunhe and mp_mazin went out of sync);
- sound/sn76496.c: the PSG had no save state at all;
- sound/fm.c: the YM2612 postload read the DAC enable from register 0x2d
  instead of 0x2b (the DAC channel was lost or computed as FM after a load).

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-28 09:51:57 +01:00
arcadez2003 f51acae279 terraf_io_w 2026-10-28 00:43:49 +00:00
arcadez2003 02beadf6c1 hmmmmm 2026-10-28 00:30:19 +00:00
arcadez2003 c542bf7d24 Forgot cant share via port io's in this core 2026-10-28 00:11:52 +00:00
arcadez2003 4d19fd28b8 Adjust the MCU mem and port loading 2026-10-28 00:05:49 +00:00
arcadez2003 34bf3c28c6 Merge pull request #2165 from zanac/cotton 
Sega System 18 and Cotton from current MAME
 2026-10-27 23:41:19 +00:00
arcadez2003 ca185b19ad skyrobo and bigfghtr 2026-10-27 19:55:15 +00:00
arcadez2003 a2960b3fca Support Sky Robo / Tatakae! Big Fighter hook up I8071 MCU 
With thanks to AdvanceMAME

MAME WIP

0.182: Dumped i8751 MCU for Sky Robo / Tatakae! Big Fighter and added basic hookup to make it work - Game now playable. Fixed screen refresh rate in Tatakae! Big Fighter [Team CAPS0ff, Angelo Salese]. Fixed service switch and updated DIPS/inputs with locations and content to match those showing on screen and observation [Tafoid]. Added debug code for initial area and promoted game to working [Angelo Salese]. Clocks verified for Sky Robo / Tatakae! Big Fighter [Guru]. Documented DACs for clone Tatakae! Big Fighter (Japan) [AJR]. Added I8751 (8MHz) CPU3. Changed VSync to 59.314620 Hz.

0.142u2: Angelo Salese merged Tatakae! Big Fighter driver into ArmedF driver.

0.141u1: Changed Z80 CPU2 clock speed to 4MHz.

0.140u3: Angelo Salese fixed service mode and removed ROM patches in clone 'Tatakae! Big Fighter'. Changed description of clone 'Tatakae! Big Fighter' to 'Tatakae! Big Fighter (Japan)'.

0.113u2: Stefan Lindberg added 'Sky Robo' (Nichibutsu 1989).

0.86: Tomasz Slanina added 'Tatakae! Big Fighter' (Nichibutsu 1989). TODO: Scroll, controls and dips.

15th August 2004: Tomasz Slanina - Tatatake! Big Fighter preliminary driver (based on my old one). Game doesn't work due to protection (RAM shared with 8751 MCU).

1st September 2003: Tomasz Slanina - VERY preliminary Tatake! Big Fighter driver. Unemulated protection (MCU). Only attract mode is working. Partially...
 2026-10-27 19:51:44 +00:00
Claude 7d3a3547e3 Sega System 18 and Cotton from current MAME (FD1094 sets, mapper, VDP, save states) 
Cotton (System 16B): the FD1094 sets cotton, cottonu, cottonj and cottonja
now run, with the decryption of machine/fd1094.c (from Moonwalker), and the
missing bootlegs cottonud, cottonjd and cottonjad are added. The dummy
cotton/cottona of system16.c are removed.

System 18: the games run on the 315-5195 mapper layout each of them sets
(read from MAME), the segaic16 video and the VDP layer, as in MAME's
segas18.cpp:
- Alien Storm (astorm, astorm3, astormu, astormj and bootlegs), Bloxeed
  (bloxeed, bloxeeda, bloxeedd), Clutch Hitter (cltchitr, cltchitrj and
  bootlegs), D. D. Crew (the six FD1094 sets and their bootlegs, 4 players
  through the 8255), Desert Breaker (desertbr, desertbrj and bootlegs),
  Laser Ghost (lghost, lghostu, lghostj and bootlegs, light guns through
  the MSM6253, MAME's gun offset correction), Wally wo Sagase! (wwallyj,
  wwallyja, wwallyja3p and bootlegs, uPD4701 trackballs), Shadow Dancer
  (shdancer, shdancerj, shdancer1, were shdancer, shdancrj, shdancrb).
- 171-5987 ROM board: ROM 1 at 200000, tile and sprite banking, 1MB and
  2MB program ROMs; fd1094.c decrypts several address windows.
- The VDP layer shows one frame after the other layers, as in MAME, and the
  VDP sees the VBLANK (VIDEO_EOF of segac2) for its partial updates.
- astormbl, shdancbl, moonwlkb, aquario, hamaway and mwalk are unchanged.

Save states (RunAhead, netplay):
- System 16B: uPD7759, sound ROM bank, segaic16 tilemap and sprite banks,
  flip, scroll latches, display enable.
- System 18: RF5C68 (registers and wave RAM), YM2612/YM3438 (envelope and
  LFO counters, key, frequencies, algorithm memory, FM timer overflow time;
  the postload also rewrites the b6/1b6 registers), sound ROM bank, VDP
  layer, mapper and I/O registers.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-27 11:53:07 +01:00
markwkidd 993403d033 Merge pull request #2159 from markwkidd/cpu-clock-core-options 
Add a CPU Clock Scale core option for each CPU
 2026-10-26 16:20:17 -04:00
zanacandClaude Opus 5.5 64b3c38ac6 Sound: 0-100 volume standard for the mixer and samples, fix filter.c float build (#2164) 
- sample_set_volume()/sample_set_stereo_volume() take 0-100 like the
  mixer. The 0-255 callers are converted with identical results; Sea Wolf
  II and Thief get the full volume they meant, and the Sea Wolf II dive
  channels (always silent) work as in MAME 0.264.
- The mixer clamps volumes, mixing levels and default levels to 0-100.
  The old 0-255 default level conversion is removed; the drivers that
  used it get its result (25) explicitly. Buggy Boy's doubled YM2149 gain
  is kept with a doubled mixing level.
- filter.c: the non-integer build did not compile and scaled the
  coefficients twice; both builds now divide by the gain.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
 2026-10-26 13:31:46 -04:00
markwkidd 42176a69d1 Fix discrete adjuster ports and defaults (#2161) 2026-10-26 03:51:14 -04:00
zanacVanni BruttoClaude Opus 5.5
 		bbb49d84d7 PSX GPU: 11-bit signed coordinates for rectangles, sprites, lines and dots (#2162) 
Soul Calibur draws the attract transitions (the windows that open from
the title screen onto the next scene, and the wipes before each demo)
with rectangles whose coordinates only make sense as 11-bit signed
values. The core took them as 16-bit values, so the rectangles were
drawn in the wrong place or not at all, and the new scene showed
through white or washed out instead of in full colour.

As in current MAME (S11_COORD_X / S11_COORD_Y), rectangles, 8x8 and
16x16 sprites, lines and dots now take 11-bit signed coordinates, like
the polygons already did. The frame buffer fill (GP0 02h) keeps its
unsigned coordinates.


Claude-Session: https://claude.ai/code/session_01MEgow1uRCv8pxMErKhmoHZ

Co-authored-by: Vanni Brutto <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
 2026-10-26 03:49:56 -04:00
markwkidd 79a4e690a4 Update descriptions for core resolution options (#2155) 2026-10-26 03:48:57 -04:00
Mark W. Kidd 75f4dbb1d9 Name the romset in the CPU Clock Scale core option keys 2026-10-25 22:53:22 -04:00
arcadez2003 fd95cd4b28 Mention Heavy Unit and new code contributors 2026-10-25 23:39:17 +00:00
Mark W. Kidd e0815b5b43 Add a CPU Clock Scale core option for each CPU 2026-10-25 19:26:21 -04:00
arcadez2003 f584d820f6 Merge pull request #2158 from sunlollyking/model1-tgp-names 
Model 1: rename the TGP's fadd, fsub, fmul, fdiv and fsqrt
 2026-10-25 23:23:45 +00:00
arcadez2003 d373dcb4b1 New ones 2026-10-25 22:35:19 +00:00
Chris 0c777d48e6 Model 1: rename the TGP's fadd, fsub, fmul, fdiv and fsqrt 
glibc declares fadd, fsub, fmul, fdiv and fsqrt in math.h for C23, and
GCC 15 builds as C23 by default, so the static TGP functions of the same
names conflict with them and model1_machine.c no longer builds. They are
tgp_fadd and so on now.
 2026-10-25 22:33:44 +00:00
arcadez2003 8a0a74c79f Merge pull request #2154 from libretro/arcadez2003-patch-8 
Add the two missing games to the Cave CV1000 driver
 2026-10-25 22:31:03 +00:00
arcadez2003 1f8b8b71b1 Try again another time 2026-10-25 22:15:46 +00:00
arcadez2003 ae45f94fc9 Revert for now 2026-10-25 22:15:04 +00:00
arcadez2003 e7b2e2706c FFS 2026-10-25 22:08:32 +00:00
arcadez2003 cf8d7da002 Update YGV608 namcond1 video code to MAME 113 part 2 2026-10-25 21:48:53 +00:00
arcadez2003 bbf2784396 Update YGV608 namcond1 video code to MAME 113 2026-10-25 21:47:29 +00:00
arcadez2003 7a361d0dad Merge pull request #2156 from zanac/mariner-sound 
Mariner / Triple Punch: AY-8910 clock of current MAME, new clones; Galaxian/Scramble hardware save states
 2026-10-25 21:09:21 +00:00
Claude ce9db6e3cc Mariner, Triple Punch: AY-8910 clock of current MAME, new clones; Galaxian/Scramble hardware save states 
- AY-8910 of the Triple Punch board (Triple Punch, Knock Out!!, Mariner,
  800 Fathoms) at 18432000/12 = 1.536 MHz, as current MAME ("verified on
  hardware"): the sound was 16.7% too high and too fast. Mariner keeps
  GAME_IMPERFECT_SOUND: its discrete sound circuits are not emulated, in
  current MAME either; 800 Fathoms gets the flag, as in MAME
- new clones from current MAME: triplepa, knockoutb, knockoutc, 800fatha
  (names and manufacturers of the sets as in MAME)
- save states of the Galaxian/Scramble/Frogger hardware (rollback, RunAhead,
  netplay diverged):
  - Galaxian video: star scroll/blink state, star timer start, flip, graphics
    banks, background and bullet colors, rockclim scroll; a postload restores
    the tilemap flip, column scroll and tiles
  - 7474 flip-flops (machine/7474.c), registered by TTL7474_config
  - Scramble sound: the sound CPU RAM (scobra map) in the saved memory, the
    AY port B timer computed from the sound CPU cycles as current MAME
    (no state, no 32-bit overflow; same values)
  - RC filters of the sound streams (streams.c) and the global sound enable
    (mixer.c)
  - Galaxian sound statics (LFO, noise, tone generator)

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 21:12:09 +01:00
arcadez2003 0742497860 Merge pull request #2152 from zanac/tx1 
Tatsumi TX-1 / Buggy Boy from current MAME
 2026-10-25 20:08:32 +00:00
arcadez2003 02cbb28183 Merge pull request #2151 from zanac/ymf278b-state 
YMF278B, YMF262 and Fuuki FG-3: save states
 2026-10-25 20:03:31 +00:00
Claude ccdf3afc6a Tatsumi TX-1 / Buggy Boy from current MAME (TX-1, Buggy Boy, Buggy Boy Junior) Closes #1478 
The driver of current MAME (Phil Bennett) in C89: the two 8086 CPUs and the
arithmetic unit, the road, object and character layers of the three screens,
the engine/noise sound with the AY-8910 / YM2149s, save states.

- 6 sets: tx1, tx1jb, tx1jc, buggyboy, buggyboyb, buggyboyjr
- the cockpit sets show their three screens side by side (768x240, 12:3), or
  only the middle one with the new core option "TX-1 / Buggy Boy Screens"
  (offered for those sets only)
- i86 core: the TEST input (WAIT instruction) and an opt-in 16-bit data bus
  (an aligned word is one access for the handlers); both off by default, the
  other i86/i186 games run as before
- the layer select and the TX-1 road pixel logic are lookup tables built
  from MAME's logic: same pixels, TX-1 about 40% faster

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 19:42:25 +01:00
Claude 0c9afd4989 YMF278B, YMF262 and Fuuki FG-3: save states 
None of the YMF278B (OPL4 PCM), YMF262 (OPL3) or Fuuki FG-3 state was in
the save states: after a load (RunAhead, netplay rollback, rewind) the
sound kept the voices of the frames run before the load, the YMF278B
timers and IRQ their old values, the sprites buffered by two frames and
the RAM shared by the two CPUs of the FG-3 too.

- YMF278B: every slot, the chip registers, timers and IRQ state.
- YMF262: every slot and channel, the chip registers; the slot outputs
  (pointers to the channel outputs) are saved as indexes.
- Fuuki FG-3: the two buffered sprite RAMs and tile banks, the shared RAM.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
 2026-10-25 17:09:58 +01:00
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.gitignore
+1
View File
@@ -4,5 +4,6 @@
*.exe
*.dll
*.so
*.d
package.json
.npmignore
CHANGELOG.md
+89 -2
View File
@@ -2,7 +2,8 @@
* Current repository maintainers: arcadez, mahoneyt944, markwkidd, twinaphex
* Past repository maintiners: arnoldsecret, grant2258
* Significant code contributors to this project: AMadvanceMAME, BritneysPAIRS, dink, FBN Dev, grant2258, iq_132, MAME Dev, Mistydreams, ShmupMAME
* Significant code contributors to this project: AMadvanceMAME, BritneysPAIRS, dink,
* FBN Dev, grant2258, iq_132, MAME Dev, Mistydreams, ShmupMAME, Zanac, AI agent claude
The list of direct contributors to the MAME 2003-Plus github repository can be found at https://github.com/libretro/mame2003-plus-libretro/graphs/contributors. Additional contributor credits can be found in LICENSE.md, CHANGELOG.old, and in the individual driver source files.
@@ -18,6 +19,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Adventure Canoe
* Air Attack
* Air Rescue
* Akka Arrh (prototype)
* Aladdin (bootleg of Megadrive version)
* Angler Dangler (Deco Cassette)
* Argus (Gottlieb, prototype)
@@ -26,11 +28,14 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Backfire!
* Back Fire (Tecmo)
* Bang Bang Busters
* Bare Knuckle (scrambled bootleg of Mega Drive version) - Romset `barekch` - 6 button pads
* Bare Knuckle II (bootleg of Mega Drive version) - Romset `barek2mb` - its PIC16C57 emulated
* Bare Knuckle II (chinese bootleg of Megadrive version)
* Bare Knuckle III (bootleg of Megadrive version)
* Baryon: Future Assault
* Beastie Feastie (Epos Tristar 9000) - Romset `beastf`; the Pac-Man conversion is now `beastfp`, as in current MAME
* Big Fight - Big Trouble In The Atlantic Ocean
* Bio-Hazard Battle (scrambled bootleg of Mega Drive version) - Romset `biohzdmb`
* Bomb Kick
* Boogie Wings
* Born To Fight
@@ -39,6 +44,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Bubble Bobble 2 - The Return Of Super Drunk (prototype)
* Bubble Buster
* Buccaneers
* Buggy Boy/Speed Buggy (cockpit, rev. D and B), Buggy Boy Junior/Speed Buggy (upright)
* Bullet (unprotected of FD1094 317-0041 set)" )
* Cabal (World, Joystick version)
* Calorie Kun vs Moguranian
@@ -49,6 +55,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Choky! Choky!
* Choutetsu Brikin'ger - iron clad
* Clockwork Aquario
* Columns II: The Voyage Through Time (World) - Romset `columns2`; the old `columns2` (Japan) is now its clone `column2j`, as in current MAME
* Combat Hawk
* Come Back Toto
* Cookie & Bibi
@@ -115,6 +122,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Hard Times
* Head On Channel (Japan, Prototype)
* Heavy Smash
* Heavy Unit
* Hoops '96
* Hypernoid
* Hyper Crash
@@ -126,6 +134,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Indian Battle
* Invasion
* Jammin (Atari Prototype)
* Jingling Jiazu Genie 2000 - Romset `jingling`
* Joe & Mac Returns
* Jolly Jogger
* Jurassic Park (Bootleg Of Megadrive Version)
@@ -158,6 +167,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Monsters World (Bootleg Of Super Pang)
* Monster Maulers
* More More
* Mortal Kombat 3 (scrambled bootleg of Mega Drive version) - Romset `mk3mdb` - 6 button pads
* Mortal Race
* Mouse Shooter GoGo
* Ms. Pacman Twin
@@ -191,6 +201,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Power Instinct Matrimelee
* Power Up Baseball
* Progear
* Puckman Pockimon Genie 2000 - Romset `puckpkmn` - the set of current MAME; the old `puckpkmn` set is now its clone `puckpkmnb`, as in current MAME
* Puyo Puyo (World) - Romset `puyo`; the old `puyopuyo`, `puyopuya` and `puyopuyb` are now its clones `puyoj`, `puyoja` and `puyobl`, as in current MAME
* Puzz Loop 2 (All Sets)
* Puzzle Break
* Puzzle Star
@@ -221,10 +233,13 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Sega Megaplay : Streets Of Rage II
* Sega Megaplay : Tecmo World Cup
* Sega Sonic Bros (Japan, Prototype)
* SegaSonic Cosmo Fighter (World and Japan) - Romsets `sonicfgt`, `sonicfgtj`
* SegaSonic Popcorn Shop (Rev B) - Romset `sonicpop` - the popcorn machine itself isn't emulated, as in current MAME
* Sengoku 3
* Shuihu Feng Yun Zhuan
* Skater (Deco Cassette)
* Skull Fang
* Sky Robo / Tatakae! Big Fighter
* Slap Shooter
* Snow Brothers 3 - Magical Adventure
* Snk Vs Capcom : Svc Chaos (MVS)
@@ -232,11 +247,13 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Sonic Boom
* Sonic The Hedgehog 2 (Bootleg Of Megadrive Version)
* Sonic The Hedgehog 3 (Bootleg Of Megadrive Version)
* Soreike! Anpanman Popcorn Koujou (Rev B and Rev A) - Romsets `anpanman`, `anpanmana` - the popcorn machine itself isn't emulated, as in current MAME
* Space Fever High Splitter
* Space Launcher
* Space Raider
* Spectrum 2000 (Euro)
* Squash
* Stack Columns (World) - Romset `stkclmns`; the old `stkclmns` (Japan) is now its clone `stkclmnsj`, as in current MAME
* Stadium Cross (World, linkable) and (US) - Romsets `scrossa`, `scrossu`; `scross` now uses the ROM names of current MAME
* Star Fire 2
* Steel Worker
@@ -246,8 +263,10 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Super Bishi Bashi Championship (ver JAA, 2 Players)
* Super Bubble Bobble (Sun Mixing, Megadrive clone hardware)
* Super Doubles Tennis (Deco Cassette)
* Sunset Riders (scrambled bootleg of Mega Drive version) - Romset `srmdb`
* Super Monaco GP
* Super Rider
* Super Street Fighter II - The New Challengers (scrambled bootleg of Mega Drive version) - Romset `ssf2mdb` - 6 button pads
* Super Trio
* SWAT Police
* Tang Tang
@@ -263,6 +282,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* ThunderForce AC (Japan, prototype, bootleg)
* Top Driving
* Top Roller
* Top Shooter - Romset `topshoot`
* Toppy & Rappy
* Torus * Mature *
* Touch & Go (Korea, unprotected)
@@ -274,14 +294,21 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Turkey Hunting
* Twin Cobra 2
* Twin Action
* Twin Squash - Romset `twinsqua`
* Twinkle
* Twinkle Tale (Bootleg Of Megadrive Version)
* TX-1 (World, Japan rev. B and C)
* Tylz
* Ufo Senshi Yohko Chan
* Varia Metal
* Vasara 2
* Virtua Bowling
* Virtua Fighter
* Waku Waku Anpanman (Rev A and original) - Romsets `wwanpanm`, `wwanpanmo`
* Waku Waku Jumbo (Rev A) - Romset `wwjumbo`
* Waku Waku Marine - Romset `wwmarine`
* Waku Waku Pajero - Romset `wwpajero`
* Waku Waku Sonic Patrol Car - Romset `soniccar`
* Wheels Runner
* Wing Force
* Wing Shooting Championship
@@ -296,16 +323,33 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
## New Clones
* 800 Fathoms (older), Knock Out!! (bootleg, set 2 and set 3), Triple Punch (set 2) - Romsets `800fatha`, `knockoutb`, `knockoutc`, `triplepa`
* Alien Storm (bootlegs of the 3 players and Japan sets) - Romsets `astorm3d`, `astormud`, `astormjd`
* Asura Buster - Eternal Warriors (USA), (Japan, set 2) and (Japan) (ARCADIA review build) - Romsets `asurabus`, `asurabusja`, `asurabusjr`; the Japan set 1 is now `asurabusj`, as in current MAME
* Bare Knuckle III (bootleg of Mega Drive version, alt set, the PIC simulated) - Romset `barek3mba` - not working, as in current MAME
* Bare Knuckle III / Sunset Riders (scrambled bootleg of Mega Drive versions) - Romset `bk3ssrmb` - not working, as in current MAME (only Bare Knuckle III boots)
* Bloxeed (US, C System, Rev A) - Romset `bloxeedu`
* Borench (set 2) and (Japan) - Romsets `borencha`, `borenchj`
* Columns (US, cocktail, Rev A) - Romset `columnsu`
* Print Club (World) and (Japan Vol.3) - Romsets `pclub`, `pclubjv3` - not working (camera and printer), as in current MAME
* Puzzle & Action: Ichidant-R (World) (bootleg) - Romset `ichirbl`
* Puzzle & Action: Tant-R (Japan) (bootleg set 3 and set 4) - Romsets `tantrbl3`, `tantrbl4`
* Ribbit! (Japan) - Romset `ribbitj`
* Sunset Riders / Super Street Fighter II - The New Challengers (scrambled bootleg of Mega Drive versions) - Romset `srssf2mb` - not working, as in current MAME (the order of the ROMs is not known)
* Battle Shark (Japan, Joystick)
* Bloxeed (bootleg) - Romset `bloxeedd`
* Botanic (French version)
* Bubble Bobble (prototype on tokio hardware)
* Calorie Kun vs Moguranian (bootleg)
* Cannon Dancer
* Clutch Hitter (bootlegs) - Romsets `cltchitrd`, `cltchitrjd`
* Competition Golf Final Round (old version) - `compglfo`
* Cotton (bootlegs of the US and Japan sets) - Romsets `cottonud`, `cottonjd`, `cottonjad`
* Crouching Tiger Hidden Dragon 2003
* Crouching Tiger Hidden Dragon 2003 Super Plus
* Crystal Castles (Joystick Version)
* D. D. Crew (bootlegs of the six FD1094 sets) - Romsets `ddcrewd`, `ddcrewud`, `ddcrew1d`, `ddcrew2d`, `ddcrewjd`, `ddcrewj2d`
* Desert Breaker (bootlegs) - Romsets `desertbrd`, `desertbrjd`
* DJ Boy (Japan)
* DoDonPachi Dai-Ou-Jou (Black Label)
* Double Dragon 3 - The Rosetta Stone (Japan)
@@ -319,6 +363,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Gals Panic DX * Mature *
* Ghox (Joystick)
* Ganbare! Gonta!! 2 / Party Time: Gonta the Diver II * Mature *
* Golden Axe II (Mega Play, original revision) - Romset `mp_gaxe2a`
* GunNail (Location Test)
* Guwange Special Version
* Hacha Mecha Fighter (bootleg)
@@ -331,6 +376,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* King of Gladiator
* Knuckle Bash 2
* Kyukyoku Tiger (Japan, 2 Players)
* Laser Ghost (bootlegs) - Romsets `lghostd`, `lghostud`
* Mad Ball V2.0 * Mature * - Romset `madball`
* Magical Drop
* Magical Drop Plus 1
@@ -339,6 +385,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Renegade (US, Bootleg)
* Safari Rally (World) - safarir
* Sexy Parodius (Ver AAA) * Mature *
* Shadow Dancer (World, Japan and US) - Romsets `shdancer`, `shdancerj`, `shdancer1` (were `shdancer`, `shdancrj`, `shdancrb`), now on the System 18 memory mapper and video as in current MAME
* Snk Vs Capcom : Svc Chaos (bootleg)
* Super Bishi Bashi Championship (ver KAA, 3 Players)
* Target Ball * Mature * (Romset `tgtballa`)
@@ -399,6 +446,8 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Agent Super Bond - Romset `superbon` - colors fixed
* Alcon - Romset: `alcon`
* Alien Storm (World and Japan 2 players, World and US 3 players) - Romsets `astorm`, `astormj`, `astorm3`, `astormu` - FD1094 encrypted 68000, Sega System 18
* Bloxeed (Japan, two sets) - Romsets `bloxeed`, `bloxeeda` - FD1094 encrypted 68000, Sega System 18
* Arch Rivals - Romset: `archrivl`
* Avengers In Galactic Storm US - Romset: `avengrgs`
* Avengers In Galactic Storm Japan - Romset: `avengrgsj`
@@ -416,10 +465,14 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Cheeky Mouse - Romset `cheekyms` - colors fixed
* Chouji Meikyuu Legion (ver 1.05) - Romset `legiono`
* Competition Golf Final Round (revision 3) - `compgolf`
* Cotton (World, US, Japan Rev A and Rev B) - Romsets `cotton`, `cottonu`, `cottonj`, `cottonja` - FD1094 encrypted 68000
* Clutch Hitter (US and Japan) - Romsets `cltchitr`, `cltchitrj` - FD1094 encrypted 68000, Sega System 18
* Crater Raider - Romset `crater`
* Crazy Climber 2 - Romset `cclimbr2`
* Dark Edge - Romset `darkedge`
* DD Crew - Romset `ddcrew`
* D. D. Crew (all FD1094 sets: World 2, 3 and 4 players, US, Japan 2 and 4 players) - Romsets `ddcrew`, `ddcrew1`, `ddcrew2`, `ddcrewu`, `ddcrewj`, `ddcrewj2` - Sega System 18, as in current MAME
* Desert Breaker (World and Japan) - Romsets `desertbr`, `desertbrj` - FD1094 encrypted 68000, Sega System 18
* Demolition Derby - Romset `demoderb`
* Die Hard Arcade - Romset `diehard` - Requires a fast system; video and sound issues remain
* Discs Of Tron - Romsets `dotron` and `dotrone`
@@ -461,6 +514,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Kick - Romset `kick`
* Kick'N Run- Romset `kicknrun`
* Kozmik Kroozr - Romset `kroozr`
* Laser Ghost (World, US and Japan) - Romsets `lghost`, `lghostu`, `lghostj` - FD1094 encrypted 68000, Sega System 18, light guns
* Legion (ver 2.03) - Romset `legion`
* Macho Mouse - Romset `machomou` - colors fixed
* Mario's Open Golf (Playchoice 10) - Romset `pc_moglf`
@@ -494,6 +548,15 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Satan's Hollow - Romset `shollow`
* Sega Megaplay : Golden Axe II - Romset `mp_gaxe2`
* Sega Megaplay : Sonic The Hedgehog - Romset `mp_sonic`
* Sega Mega-Tech : After Burner - Romset `mt_aftrb` - SMS based
* Sega Mega-Tech : Astro Warrior - Romset `mt_astro` - SMS based
* Sega Mega-Tech : Bonanza Bros. - Romset `mt_bbros` - the good dump of current MAME
* Sega Mega-Tech : Ghouls'n Ghosts - Romset `mt_gng` - the good dump of current MAME
* Sega Mega-Tech : Golden Axe II - Romset `mt_gaxe2`
* Sega Mega-Tech : Great Golf - Romset `mt_ggolf` - SMS based, the good dump of current MAME
* Sega Mega-Tech : Parlour Games - Romset `mt_parlg` - SMS based
* Sega Mega-Tech : Shinobi - Romset `mt_shnbi` - SMS based
* Sega Mega-Tech : Tetris - Romset `mt_tetri` - the good dump of current MAME
* Shisensho II * Mature * - Romset `shisen2`
* Shogun Warriors - Romset `shogwarr`
* Shrike Avenger - Romset `shrike`
@@ -502,6 +565,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Slipstream - Romset `slipstrm`
* Snowboard Championship - Romset `snowboar`
* Solar Fox - Romset `solarfox`
* Songjiangyanyi Final - Romset `songjang` - the Mega Drive board of current MAME, the HBLANK status it waits for
* Space Position - Romset `spcpostn`
* Space Seeker - Romset `spaceskr`
* Speed Spin - Romset `speedspn` - gfx glitches
@@ -530,6 +594,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
* Under Fire - Romset `undrfire`
* U.S. Classic - Romset `usclssic` - colors fixed
* VS. Hot Smash - `hotsmash`
* Wally wo Sagase! (rev A and B, 2 and 3 players) - Romsets `wwallyj`, `wwallyja`, `wwallyja3p` - FD1094 encrypted 68000, Sega System 18, trackballs
* Wonder Boy in Monster Land (Japan New Ver.) - Romset `wbml`
* Wonder Boy in Monster Land (Japan Old Ver.) - Romset `wbmljo`
* Xenophobe - Romset `xenophob`
@@ -599,6 +664,7 @@ The list of direct contributors to the MAME 2003-Plus github repository can be f
## Games now with improved sound
* 800 Fathoms, Knock Out!!, Mariner, Triple Punch: AY-8910 clock of current MAME (1.536 MHz, verified on hardware), the sound was 16% too high and too fast
* 1945kIII
* Air Buster
* Ashita no Joe
@@ -796,6 +862,24 @@ Notes on this option:
## Misc Changes
* Save states (RunAhead, netplay) of the Galaxian/Scramble/Frogger hardware: Galaxian video (stars, flip, banks, background), the 7474 flip-flops, the Scramble sound RAM and timer, the RC filters of the sound streams, the global sound enable
* Sega System 18: all the games on the 315-5195 memory mapper, the segaic16 video and the VDP layer as in current MAME (171-5874, 171-5987 and Shadow Dancer ROM boards, FD1094 sets, Laser Ghost light guns, Wally wo Sagase! trackballs); the old `astorm` and `astorm2p` are now `astormj` and `astorm`
* Sega Mega Drive VDP (315-5313): now a module of its own (`vidhrdw/segavdp.c`), started with its own configuration by System C/C2, Mega-Tech, Mega Play, the Mega Drive bootlegs and System 18, so a change for one board no longer reaches the others; a game loaded after a Mega Play game in the same session no longer inherits its interrupt mode (e.g. Columns attract out of sync), and the VDP window position and VBLANK flag are in the save states
* Sega Mega Play: its own driver (`drivers/megaplay.c`, as in current MAME), the Mega Drive part shared with the other Mega Drive based boards; Tecmo World Cup is now `mp_twcup` and the BIOS version 2 ROM `epr-a15294.ic2`, as in current MAME
* Sega Mega-Tech: its own driver (`drivers/megatech.c`, as in current MAME), sets, ROMs and names as in current MAME (good dumps of `mt_bbros`, `mt_ggolf`, `mt_gng`, `mt_tetri`, the instruction ROMs in the cart at 0x300000); the Master System carts now run, on the Mega Drive in Mark III mode as in current MAME (the VDP in mode 4, the Z80 with the Sega mapper); the BIOS cart slots as in current MAME (the menu lists the one cart in slot 1, the slot RAM, the window into the cart), the BIOS display in its 224 line mode (the MENU title was cut) and drawn line by line; the Mega Drive VDP line timing and partial updates now count its own lines below the BIOS screen (they used the scanlines of the double screen); the 68000 writes to 0xa02000 of the boards without the Mega Play BIOS no longer go through a NULL pointer (Great Golf and Great Soccer crashed)
* Sega Mega Play: the BIOS overlay is transparent on colour 0 of both its palettes and covers its borders, as in current MAME (the boot logo screen was hidden behind a green background)
* Sega Mega Drive based bootlegs: their own driver (`drivers/megadriv_acbl.c`, as in current MAME), with the board variants of current MAME (the 6 button pads, the DIP switches at 0x770070 of the scrambled boards, the 3rd I/O port coins, the PIC16C57 of `barek2mb`); the new sets take their V-INT / H-INT through the VDP interrupt enables as on the real hardware (Mortal Kombat 3 crashed at boot), the descrambling of the bootlegs and the PIC of `barek2mb` now also work on big-endian hosts
* Genie / Y-BOX and Sun Mixing boards: their own drivers (`drivers/megadriv_ybox.c`, `drivers/megadriv_sunmix.c`, as in current MAME); the Y-BOX games run on the Mega Drive machine as in MAME (Z80, I/O, the VDP interrupts and HBLANK as on the real hardware), with the protection read back latches and the ROM address remapping of Shuihu Feng Yun Zhuan of current MAME
* Sega System C/C2: `drivers/segac2.c` now has only System C/C2, the Mega Drive part shared by the other boards is in `machine/megadriv.c` (as `megadriv.cpp` in current MAME); the sets, ROMs, titles, inputs and DIP switches as in current MAME; the protection chip as the EPM5032 logic of each game of current MAME (no more Ribbit! and Puyo Puyo 2 workarounds and fake tables, Print Club Vol.2, 4 and 5 now get past the protection); the alternate palette mode of Ribbit! and Twin Squash (instead of the palette address watching of Ribbit!); the 68000 at 8.95 MHz and the 59.92 Hz refresh as in current MAME (it ran at 7.67 MHz and 60 Hz: the games now follow the timing of MAME frame for frame), the V-INT and H-INT held until the 68000 takes them as on the board, the address mirrors, the battery-backed work RAM (high scores kept, as in current MAME) and the coin meters on the I/O chip
* YM2612 / YM3438: the busy flag after a data write (192 clocks, as in current MAME), and a timer started long after its last overflow runs a whole period instead of firing at once (Thunder Force AC, Bloxeed and the other System C2 games follow MAME again)
* Sega Mega Play: the V-INT of the BIOS VDP comes about 12 lines after the Mega Drive VBLANK, as in current MAME (it came ~80 lines early, and the BIOS/game handshake on port C could miss: Tecmo World Cup stayed on a black screen)
* Sega Mega Play / System E: the tiles of the SMS-type VDP are read byte by byte, so they are drawn right on big-endian hosts (the Mega Play BIOS screen had the wrong colours)
* Sega Mega Drive VDP: in H32 mode the sprite table base uses bit 0 of register 5, as on the real VDP (the fighters of Super Street Fighter II were missing, the sprites of Bonanza Bros. on Mega-Tech were garbled)
* PIC16C5x CPU core: the program counter wraps at the end of the program memory (the 2K parts start at 0x7ff and ran past the ROM), and the save states no longer register the ports and STATUS through a NULL pointer (the save of a game with a PIC crashed); these are in the data RAM, saved with the CPU memory
* Save states (netplay, RunAhead with a second instance) of the Mega Drive based boards: the Z80 RAM and bus state and the Mega-Tech / Mega Play BIOS registers and RAM are saved (Gunstar Heroes and Mazin Wars Mega Play went out of sync after loading a state in a new instance); the SN76496 PSG is saved, and the YM2612 DAC enable is restored from its own register (0x2b, it was read from 0x2d)
* Sega System 18 (also Moonwalker): the VDP palette writes no longer overflow the System 16 palette RAM (they corrupted the memory after it, e.g. garbled graphics in Shadow Dancer), and the sprite shadows over the VDP layer no longer index past the palette
* Save states (RunAhead, netplay) of the Sega System 18 hardware: the RF5C68 PCM, the YM2612/YM3438 envelope, LFO, frequency and timer state, the VDP layer, the sound ROM bank
* Save states (RunAhead, netplay) of the Sega System 16B hardware: the uPD7759 ADPCM chip, the sound CPU ROM bank, the segaic16 tilemap and sprite banks, flip, scroll latches and display enable
* Added HD647180 MCU sound support for Fire Shark and Vimana [arcadez]
* Added sound sample support for Cosmic Alien [BritneysPAIRS, arcadez]
* Updated sample support for Donkey Kong and Donkey kong JR to MAME87 [BritneysPAIRS, arcadez]
@@ -1202,4 +1286,7 @@ could crash on the score calc between levels is sorted [amadvance, arcadez]
* Added fixes from later MAME so that Princess Clara Daisakusen now works [MAMEDev, arcadez]
* Ported a new raiden2.c driver Raiden II Raiden DX and Zero Team etc etc now playable [Salvia, MAMEDev, FBN, vanni and claude, arcadez]
* Ported the Cave CV1000 driver from current MAME: SH-3 CPU (interpreter and a recompiler with the same results), the blitter, the YMZ770 sound chip, the NAND flash and the RTC9701 [MAMEDev, vanni and claude]
* Added support for the hvyunit.c driver ported across from my xbox project [arcadez, mistydreams, vanni and claude]
* Added Sky Robo / Tatakae! Big Fighter to armedf.c and hooked it up to the new mcs51 cpu
[arcadez, grant2258, AdvanceMAME, Zanac]
* Ported a driver for Atari's Akka Arrh across from AdvanceMAME [arcadez, AdvanceMAME]
Makefile
+36 -1
View File
@@ -100,7 +100,9 @@ endif
ifeq ($(platform), unix)
TARGET = $(TARGET_NAME)_libretro.so
fpic = -fPIC
CFLAGS += $(fpic)
# only the retro_* entry points (RETRO_API) leave the library: the rest is
# reached directly instead of through the GOT and PLT
CFLAGS += $(fpic) -fvisibility=hidden
LDFLAGS += $(fpic) -shared -Wl,--version-script=link.T
# Linux Portable
@@ -872,6 +874,24 @@ ifeq ($(HAVE_ARMv6),1)
CFLAGS += -DHAVE_ARMv6
endif
# threads (libretro-common rthreads), as the other libretro cores do (beetle-psx):
# on by default, off where there is no thread library, and on the MSVC builds
# (the ST-V threaded video needs MSVC 2015's thread-local storage, the
# buildbot's MSVC lanes are 2005 and 2010: nothing would use the threads)
HAVE_THREADS ?= 1
ifneq (,$(filter $(platform), emscripten linux-portable ngc wii wiiu ps2 ps3 psl1ght psp1 ctr vita))
HAVE_THREADS = 0
endif
ifneq (,$(findstring msvc,$(platform)))
HAVE_THREADS = 0
endif
ifeq ($(HAVE_THREADS),1)
# pthreads are in the C library on Darwin and Android, Windows uses its own threads
ifeq (,$(findstring msvc,$(platform))$(findstring android,$(platform))$(findstring ios,$(platform))$(findstring tvos,$(platform))$(filter osx win,$(platform)))
LIBS += -lpthread
endif
endif
# include the various .mak files
ifneq (,$(filter $(INCLUDE_DRV),all))
include Makefile.common
@@ -956,3 +976,18 @@ ifeq ($(SPLIT_UP_LINK), 1)
@rm $@.in
endif
$(HIDE)rm -f $(OBJECTS) $(TARGET)
# 1. Map object files to dependency trackers
DEPFILES := $(OBJECTS:.o=.d)
# 2. ONLY read or handle dependencies if we are NOT running a clean command
ifneq ($(MAKECMDGOALS),clean)
-include $(DEPFILES)
# 3. FIXED: Generate a pure, clean dependency file directly using the -MM flag
%.d: %.c
@echo "Generating dependency tracker for $<..."
$(HIDE)$(CC) -MM -MP -MT $(@:.d=.o) -MF $@ $< $(CFLAGS)
# 4. Fallback stub to prevent build errors if a header file is deleted
$(DEPFILES):
endif
Makefile.common
+22 -4
View File
@@ -172,6 +172,7 @@ CPUS+=TMS9995@
CPUS+=Z8000@
CPUS+=TMS32010@
CPUS+=TMS32025@
CPUS+=NAMCOC71@
CPUS+=TMS32031@
CPUS+=I960@
CPUS+=MB86233@
@@ -499,7 +500,7 @@ SOURCES_C += \
$(CORE_DIR)/vidhrdw/mitchell_vidhrdw.c $(CORE_DIR)/drivers/mitchell.c \
$(CORE_DIR)/vidhrdw/cbasebal_vidhrdw.c $(CORE_DIR)/drivers/cbasebal.c \
$(CORE_DIR)/vidhrdw/cps1_vidhrdw.c $(CORE_DIR)/drivers/cps1.c $(CORE_DIR)/drivers/cps2.c $(CORE_DIR)/machine/cps2crypt.c\
$(CORE_DIR)/drivers/zn.c $(CORE_DIR)/sndhrdw/taitozoom.c $(CORE_DIR)/sound/zsg2.c $(CORE_DIR)/cpu/tms57002/tms57002.c \
$(CORE_DIR)/drivers/zn.c $(CORE_DIR)/sndhrdw/acclaim_rax.c $(CORE_DIR)/sndhrdw/taitozoom.c $(CORE_DIR)/sound/zsg2.c $(CORE_DIR)/cpu/tms57002/tms57002.c \
$(CORE_DIR)/drivers/cps3.c $(CORE_DIR)/sndhrdw/cps3_sndhrdw.c \
$(CORE_DIR)/vidhrdw/tms34061_vidhrdw.c \
$(CORE_DIR)/machine/capbowl_machine.c $(CORE_DIR)/vidhrdw/capbowl_vidhrdw.c $(CORE_DIR)/drivers/capbowl.c \
@@ -529,10 +530,10 @@ SOURCES_C += \
$(CORE_DIR)/drivers/system24.c $(CORE_DIR)/machine/system24_machine.c $(CORE_DIR)/vidhrdw/system24_vidhrdw.c \
$(CORE_DIR)/vidhrdw/segaic24.c $(CORE_DIR)/vidhrdw/segas18.c \
$(CORE_DIR)/drivers/segas32.c $(CORE_DIR)/machine/segas32.c $(CORE_DIR)/vidhrdw/segas32.c \
$(CORE_DIR)/vidhrdw/segac2_vidhrdw.c $(CORE_DIR)/drivers/segac2.c \
$(CORE_DIR)/vidhrdw/segavdp.c $(CORE_DIR)/vidhrdw/segac2_vidhrdw.c $(CORE_DIR)/machine/megadriv.c $(CORE_DIR)/drivers/segac2.c $(CORE_DIR)/drivers/megaplay.c $(CORE_DIR)/drivers/megatech.c $(CORE_DIR)/drivers/megadriv_acbl.c $(CORE_DIR)/drivers/megadriv_ybox.c $(CORE_DIR)/drivers/megadriv_sunmix.c \
$(CORE_DIR)/drivers/stv.c $(CORE_DIR)/drivers/stvhacks.c $(CORE_DIR)/machine/stvcd.c \
$(CORE_DIR)/machine/scudsp.c \
$(CORE_DIR)/vidhrdw/stvvdp1_vidhrdw.c $(CORE_DIR)/vidhrdw/stvvdp2_vidhrdw.c \
$(CORE_DIR)/vidhrdw/stvvid.c \
$(CORE_DIR)/vidhrdw/deniam_vidhrdw.c $(CORE_DIR)/drivers/deniam.c \
$(CORE_DIR)/machine/btime_machine.c $(CORE_DIR)/vidhrdw/btime_vidhrdw.c $(CORE_DIR)/drivers/btime.c \
$(CORE_DIR)/machine/decocass_machine.c $(CORE_DIR)/vidhrdw/decocass_vidhrdw.c $(CORE_DIR)/drivers/decocass.c \
@@ -1068,9 +1069,11 @@ SOURCES_C += \
$(CORE_DIR)/machine/sega315_5881.c $(CORE_DIR)/machine/sega315_5838.c \
$(CORE_DIR)/drivers/calorie.c \
$(CORE_DIR)/drivers/hvyunit.c \
$(CORE_DIR)/drivers/akkaarrh.c \
$(CORE_DIR)/machine/mc8123.c \
$(CORE_DIR)/machine/namcoio_machine.c \
$(CORE_DIR)/drivers/tatsumi.c $(CORE_DIR)/vidhrdw/tatsumi.c $(CORE_DIR)/machine/tatsumi.c
$(CORE_DIR)/drivers/tatsumi.c $(CORE_DIR)/vidhrdw/tatsumi.c $(CORE_DIR)/machine/tatsumi.c \
$(CORE_DIR)/drivers/tx1.c $(CORE_DIR)/vidhrdw/tx1_vidhrdw.c $(CORE_DIR)/machine/tx1_machine.c $(CORE_DIR)/sndhrdw/tx1_sndhrdw.c
@@ -1864,6 +1867,15 @@ else
CPUDEFS += -DHAS_TMS32010=0
endif
CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/namcoc71
CPUDEFS += -DHAS_NAMCOC71=1
SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
else
CPUDEFS += -DHAS_NAMCOC71=0
endif
CPU=$(strip $(findstring TMS32025@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/tms32025
@@ -2851,6 +2863,12 @@ SOURCES_C += \
# sljit: run-time code generator of the MIPS recompilers (empty where they are not supported)
SOURCES_C += $(CORE_DIR)/lib/sljit/sljit_mame.c
# threads (libretro-common rthreads, set by the platform: see Makefile): the ST-V threaded video option
ifeq ($(HAVE_THREADS),1)
COREDEFINES += -DHAVE_THREADS
SOURCES_C += $(LIBRETRO_COMM_DIR)/rthreads/rthreads.c
endif
ifeq ($(STATIC_LINKING),1)
else
SOURCES_C += \
Makefile.split
+9
View File
@@ -1821,6 +1821,15 @@ else
CPUDEFS += -DHAS_TMS32010=0
endif
CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/namcoc71
CPUDEFS += -DHAS_NAMCOC71=1
SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
else
CPUDEFS += -DHAS_NAMCOC71=0
endif
CPU=$(strip $(findstring TMS32025@,$(CPUS)))
ifneq ($(CPU),)
OBJDIRS += $(CORE_DIR)/cpu/tms32025
docs/sega-model2.md
+16
View File
@@ -153,6 +153,22 @@ in ROM, so the interrupt was lost and the main loop waited for the timer
forever (black screen after "STAND ALONE"). With 32 bytes the commands fit
and the game plays.
**The MIDI interrupt.** The sound program reads one byte from the queue per
MIDI interrupt (level 3 on these boards). The interrupt is now dropped when
the program reads the byte, and raised again only while the queue still has
bytes, as in current MAME. Before, it could stay raised on an empty queue:
the sound program then took it again and read a stale byte as part of a
command. This corrupted the music commands of Dead or Alive (61 extra reads
in the attract mode) and Manx TT (189), whose music then played wrong or
stopped. The SCSP timers are now real timers, as in MAME, and each interrupt
source has its own level, which stays raised until the program acknowledges
it.
**How it was checked.** Each sound command the i960 sends is read once, with
no extra reads, in `doa`, `fvipers`, `hotd`, `manxtt`, `rchase2`, `srallyc`
and `vf2`. In Dead or Alive the sound commands and every slot register write
between 15 and 25 s of the attract mode are the same as in MAME 0.264.
## Rail Chase 2: mirrored sample ROMs
Sets: `rchase2`.
jni/Android.mk
+3
View File
@@ -3,6 +3,9 @@ LOCAL_PATH := $(call my-dir)
ROOT_DIR := $(LOCAL_PATH)/..
CORE_DIR := $(ROOT_DIR)/src
# threads: in bionic's C library
HAVE_THREADS := 1
include $(ROOT_DIR)/Makefile.common
COREFLAGS := $(DEFS) $(COREDEFINES) $(CPUDEFS) $(SOUNDDEFS) $(ASMDEFS) $(DBGDEFS) -ffast-math -funroll-loops -DANDROID -DHAVE_ZLIB $(INCFLAGS)
metadata/catver.ini
+55 -5
View File
@@ -259,7 +259,12 @@ asteroib=Shooter / Field
astinvad=Shooter / Gallery
kamikaze=Shooter / Gallery
astorm=Platform / Shooter Scrolling
astorm2p=Platform / Shooter Scrolling
astorm3=Platform / Shooter Scrolling
astorm3d=Platform / Shooter Scrolling
astormj=Platform / Shooter Scrolling
astormjd=Platform / Shooter Scrolling
astormu=Platform / Shooter Scrolling
astormud=Platform / Shooter Scrolling
astormbl=Platform / Shooter Scrolling
astrass=Fighter / Versus
astrob=Shooter / Gallery
@@ -487,6 +492,8 @@ bloods21=Fighter / Versus
bloods22=Fighter / Versus
bloodwar=Fighter / Versus
bloxeed=Puzzle / Drop
bloxeeda=Puzzle / Drop
bloxeedd=Puzzle / Drop
bloxeedc=Puzzle / Drop
blstroid=Shooter / Field
blsthead=Shooter / Field
@@ -610,6 +617,9 @@ buckrog=Shooter / Flying (chase view)
buckrogn=Shooter / Flying (chase view)
bucky=Shooter / Walking
buckyua=Shooter / Walking
buggyboy=Driving / Race (chase view)
buggyboyb=Driving / Race (chase view)
buggyboyjr=Driving / Race (chase view)
buggychl=Driving / Race (chase view)
buggycht=Driving / Race (chase view)
bulletd=Shooter / Walking
@@ -813,6 +823,9 @@ clowns=Ball & Paddle / Jump and Touch
clowns1=Ball & Paddle / Jump and Touch
clshroad=Driving / Race Bike
cltchitr=Sports / Baseball
cltchitrd=Sports / Baseball
cltchitrj=Sports / Baseball
cltchitrjd=Sports / Baseball
club90s=Tabletop / Mahjong * Mature *
club90sa=Tabletop / Mahjong * Mature *
cluckypo=Casino / Cards
@@ -886,10 +899,15 @@ cosmogng=Shooter / Gallery
cosmognj=Shooter / Gallery
cosmos=Shooter / Gallery
cotton=Shooter / Flying Horizontal
cottona=Shooter / Flying Horizontal
cotton2=Shooter / Flying Horizontal
cottonbm=Shooter / Flying Horizontal
cottond=Shooter / Flying Horizontal
cottonj=Shooter / Flying Horizontal
cottonja=Shooter / Flying Horizontal
cottonjad=Shooter / Flying Horizontal
cottonjd=Shooter / Flying Horizontal
cottonu=Shooter / Flying Horizontal
cottonud=Shooter / Flying Horizontal
countrun=Maze / Driving
countrunb3=Maze / Driving
countrb2=Maze / Driving
@@ -1065,6 +1083,21 @@ dcon=Shooter / Command
dday=Shooter / Gallery
ddayc=Shooter / Gallery
ddcrew=Fighter / 2.5D
ddcrew1=Fighter / 2.5D
ddcrew1d=Fighter / 2.5D
ddcrew2=Fighter / 2.5D
ddcrew2d=Fighter / 2.5D
ddcrewd=Fighter / 2.5D
ddcrewj=Fighter / 2.5D
ddcrewj2=Fighter / 2.5D
ddcrewj2d=Fighter / 2.5D
ddcrewjd=Fighter / 2.5D
ddcrewu=Fighter / 2.5D
ddcrewud=Fighter / 2.5D
desertbr=Shooter / Walking
desertbrd=Shooter / Walking
desertbrj=Shooter / Walking
desertbrjd=Shooter / Walking
ddenlovr=Tabletop / Othello - Reversi * Mature *
ddonpach=Shooter / Flying Vertical
ddonpacha=Shooter / Flying Vertical
@@ -2446,6 +2479,10 @@ lethalth=Shooter / Flying Vertical
thndblst=Shooter / Flying Vertical
levers=Platform / Run Jump
lghost=Shooter / Gun
lghostd=Shooter / Gun
lghostj=Shooter / Gun
lghostu=Shooter / Gun
lghostud=Shooter / Gun
lgtnfght=Shooter / Flying Vertical
trigon=Shooter / Flying Vertical
liberate=Shooter / Flying
@@ -2575,6 +2612,7 @@ marineb=Shooter / Flying
marinedt=Maze / Escape
mariner=Shooter / Misc. Horizontal
800fath=Shooter / Misc. Horizontal
800fatha=Shooter / Misc. Horizontal
mario=Platform / Run Jump
marioe=Platform / Run Jump
mariof=Platform / Run Jump
@@ -2818,11 +2856,12 @@ mouserc=Platform / Run Jump
mp_bio=Shooter / Flying Horizontal
mp_col3=Puzzle / Drop
mp_gaxe2=Fighter / 2.5D
mp_gaxe2a=Fighter / 2.5D
mp_shnb3=Platform / Shooter Scrolling
mp_soni2=Platform / Run, Jump & Scrolling
mp_sonic=Platform / Run, Jump & Scrolling
mp_sor2=Fighter / 2.5D
mp_twc=Sports / Soccer
mp_twcup=Sports / Soccer
mpang=Shooter / 3rd Person
mpanga=Shooter / 3rd Person
mpangj=Shooter / 3rd Person
@@ -4156,9 +4195,9 @@ shanhigw=Puzzle / Match
sharkatt=Shooter / Underwater
sharrier=Shooter / Flying (chase view)
shdancer=Platform / Fighter Scrolling
shdancer1=Platform / Fighter Scrolling
shdancerj=Platform / Fighter Scrolling
shdancbl=Platform / Fighter Scrolling
shdancrb=Platform / Fighter Scrolling
shdancrj=Platform / Fighter Scrolling
sheriff=Shooter / Field
bandido=Shooter / Field
shienryu=Shooter / Flying Vertical
@@ -4944,7 +4983,10 @@ labyrunk=Shooter / Walking
labyrunr=Shooter / Walking
triothep=Platform / Fighter Scrolling
triplep=Maze / Outline
triplepa=Maze / Outline
knockout=Maze / Outline
knockoutb=Maze / Outline
knockoutc=Maze / Outline
triplew1=Tabletop / Mahjong * Mature *
triplew2=Tabletop / Mahjong * Mature *
triplhnt=Shooter / Gun
@@ -5031,6 +5073,9 @@ twinspri=Shooter / Flying Vertical
twotiger=Shooter / Field
twotigra=Shooter / Field
tws96=Sports / Soccer
tx1=Driving / Race (chase view)
tx1jb=Driving / Race (chase view)
tx1jc=Driving / Race (chase view)
tylz=Maze / Change Surface
uballoon=Platform / Run Jump
uccops=Fighter / 2.5D
@@ -5306,6 +5351,11 @@ wschampa=Shooter / Gun
wseries=Sports / Baseball
wsf=Sports / Soccer
wtennis=Sports / Tennis
wwallyj=Puzzle / Find the Objects
wwallyja=Puzzle / Find the Objects
wwallyja3p=Puzzle / Find the Objects
wwallyjad=Puzzle / Find the Objects
wwallyjd=Puzzle / Find the Objects
wwestern=Shooter / Misc. Vertical
wwester1=Shooter / Misc. Vertical
wwfmania=Sports / Wrestling
metadata/cheat.dat
+38 -88
View File
@@ -5721,7 +5721,26 @@ astinvad:0:1F9D:99:000:Infinite Credits
astinvad:0:1D01:08:000:Infinite Lives
astinvad:0:1CD8:00:000:Invincibility
; [ Alien Storm ]
; [ Alien Storm (Japan, 2 Players) ]
astormj:0:000000:00:999:[Invincibility only works ]
astormj:0:000000:00:999:[for the following missions ]
astormj:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
astormj:0:000000:00:999:[ 3-7, 4-1, 4-5, 5-1, 5-2, ]
astormj:0:000000:00:999:[ 5-4, 6-1, 6-2, 6-4, 6-5. ]
astormj:0:FFE00D:30:000:Infinite Life PL1
astormj:0:FFE00E:80:000:Infinite Energy PL1
astormj:0:FFC061:78:000:Invincibility PL1
astormj:0:FFE031:00:000:No delay for extra weapon PL1
astormj:0:FFE08D:30:000:Infinite Life PL2
astormj:0:FFE08E:80:000:Infinite Energy PL2
astormj:0:FFC461:78:000:Invincibility PL2
astormj:0:FFE0B1:00:000:No delay for extra weapon PL2
astormj:0:FFE10D:30:000:Infinite Life PL3
astormj:0:FFE10E:80:000:Infinite Energy PL3
astormj:0:FFC861:78:000:Invincibility PL3
astormj:0:FFE131:00:000:No delay for extra weapon PL3
; [ Alien Storm (World, 2 Players) ]
astorm:0:000000:00:999:[Invincibility only works ]
astorm:0:000000:00:999:[for the following missions ]
astorm:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
@@ -5735,25 +5754,6 @@ astorm:0:FFE08D:30:000:Infinite Life PL2
astorm:0:FFE08E:80:000:Infinite Energy PL2
astorm:0:FFC461:78:000:Invincibility PL2
astorm:0:FFE0B1:00:000:No delay for extra weapon PL2
astorm:0:FFE10D:30:000:Infinite Life PL3
astorm:0:FFE10E:80:000:Infinite Energy PL3
astorm:0:FFC861:78:000:Invincibility PL3
astorm:0:FFE131:00:000:No delay for extra weapon PL3
; [ Alien Storm (2 Player) ]
astorm2p:0:000000:00:999:[Invincibility only works ]
astorm2p:0:000000:00:999:[for the following missions ]
astorm2p:0:000000:00:999:[ 1-1, 2-1, 2-3, 3-1, 3-5, ]
astorm2p:0:000000:00:999:[ 3-7, 4-1, 4-5, 5-1, 5-2, ]
astorm2p:0:000000:00:999:[ 5-4, 6-1, 6-2, 6-4, 6-5. ]
astorm2p:0:FFE00D:30:000:Infinite Life PL1
astorm2p:0:FFE00E:80:000:Infinite Energy PL1
astorm2p:0:FFC061:78:000:Invincibility PL1
astorm2p:0:FFE031:00:000:No delay for extra weapon PL1
astorm2p:0:FFE08D:30:000:Infinite Life PL2
astorm2p:0:FFE08E:80:000:Infinite Energy PL2
astorm2p:0:FFC461:78:000:Invincibility PL2
astorm2p:0:FFE0B1:00:000:No delay for extra weapon PL2
; [ Alien Storm (bootleg) ]
astormbl:0:000000:00:999:[Invincibility only works ]
@@ -15518,16 +15518,6 @@ clshroad:0:81E7:00:500:Infinite Time (3/3)
clshroad:0:81FD:03:000:Infinite Energy
clshroad:0:81FE:0E:500:Infinite Energy (2/2)
; [ Clutch Hitter ]
cltchitr:0:0000:00:999:[ There are no cheats ]:REASON 1
cltchitr:0:0000:00:999:[ for this game as it ]:REASON 1
cltchitr:0:0000:00:999:[ didn't work the last ]:REASON 1
cltchitr:0:0000:00:999:[ time it was tested. ]:REASON 1
cltchitr:0:0000:00:999:[ If the game now works ]:REASON 1
cltchitr:0:0000:00:999:[ please request cheats ]:REASON 1
cltchitr:0:0000:00:999:[ for it on the cheat ]:REASON 1
cltchitr:0:0000:00:999:[ forums. ]:REASON 1
; [ Mahjong CLUB 90's (set 1) (Japan 900919) ]
club90s:0:F0EF:63:000:Infinite Money
club90s:0:0000:00:999:[ The winning hand cheat must be ]
@@ -16588,16 +16578,6 @@ cosmos:0:1D66:01:040:Invincibility:Turn OFF to dock!
cosmos:0:1CDD:05:000:Infinite Lives PL1
cosmos:0:1CDE:05:000:Infinite Lives PL2
; [ Cotton (Japan) ]
cotton:0:0000:00:999:[ There are no cheats ]:REASON 1
cotton:0:0000:00:999:[ for this game as it ]:REASON 1
cotton:0:0000:00:999:[ didn't work the last ]:REASON 1
cotton:0:0000:00:999:[ time it was tested. ]:REASON 1
cotton:0:0000:00:999:[ If the game now works ]:REASON 1
cotton:0:0000:00:999:[ please request cheats ]:REASON 1
cotton:0:0000:00:999:[ for it on the cheat ]:REASON 1
cotton:0:0000:00:999:[ forums. ]:REASON 1
; [ Cotton 2 ]
cotton2:0:060E518F:06:000:Invincibility PL1
cotton2:0:060E5DD3:21:000:Maximum Fire Power PL1
@@ -19895,16 +19875,6 @@ ddayjlc:0:0000:00:999:[ please request cheats ]:REASON 1
ddayjlc:0:0000:00:999:[ for it on the cheat ]:REASON 1
ddayjlc:0:0000:00:999:[ forums. ]:REASON 1
; [ DD Crew ]
ddcrew:0:0000:00:999:[ There are no cheats ]:REASON 1
ddcrew:0:0000:00:999:[ for this game as it ]:REASON 1
ddcrew:0:0000:00:999:[ didn't work the last ]:REASON 1
ddcrew:0:0000:00:999:[ time it was tested. ]:REASON 1
ddcrew:0:0000:00:999:[ If the game now works ]:REASON 1
ddcrew:0:0000:00:999:[ please request cheats ]:REASON 1
ddcrew:0:0000:00:999:[ for it on the cheat ]:REASON 1
ddcrew:0:0000:00:999:[ forums. ]:REASON 1
; [ Don Den Lover Vol. 1 (Hong Kong) ]
ddenlovr:0:FF9576:64:000:Infinite Time
ddenlovr:0:FF959E:03:000:Infinite Help
@@ -59664,16 +59634,6 @@ lethalth:0:E3ADE:03:001:Get Ball Shot Now! PL2
levers:0:4175:63:000:Infinite Lives PL1
levers:0:4176:63:000:Infinite Lives PL2
; [ Laser Ghost ]
lghost:0:0000:00:999:[ There are no cheats ]:REASON 1
lghost:0:0000:00:999:[ for this game as it ]:REASON 1
lghost:0:0000:00:999:[ didn't work the last ]:REASON 1
lghost:0:0000:00:999:[ time it was tested. ]:REASON 1
lghost:0:0000:00:999:[ If the game now works ]:REASON 1
lghost:0:0000:00:999:[ please request cheats ]:REASON 1
lghost:0:0000:00:999:[ for it on the cheat ]:REASON 1
lghost:0:0000:00:999:[ forums. ]:REASON 1
; [ Lightning Fighters (US) ]
lgtnfght:0:000000:00:999:[Enable invincibility during]
lgtnfght:0:000000:00:999:[game play ONLY!! ]
@@ -114044,7 +114004,7 @@ shdancbl:0:FFC490:01:001:Get the Power-up gun Now!
shdancbl:0:FFEB0A:9A:000:Infinite Lives PL1
shdancbl:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (US) ]
; [ Shadow Dancer (World) ]
shdancer:0:FFC407:59:000:Infinite Time
shdancer:0:FFC41F:09:000:Infinite Magic
shdancer:0:FFC490:00:000:Always have the Normal gun
@@ -114054,25 +114014,25 @@ shdancer:0:FFC490:01:001:Get the Power-up gun Now!
shdancer:0:FFEB0A:9A:000:Infinite Lives PL1
shdancer:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (Rev.B) ]
shdancrb:0:FFC407:59:000:Infinite Time
shdancrb:0:FFC41F:09:000:Infinite Magic
shdancrb:0:FFC490:00:000:Always have the Normal gun
shdancrb:0:FFC490:01:000:Always have the Power-up gun
shdancrb:0:FFC490:00:001:Get the Normal gun Now!
shdancrb:0:FFC490:01:001:Get the Power-up gun Now!
shdancrb:0:FFEB0A:9A:000:Infinite Lives PL1
shdancrb:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (US) ]
shdancer1:0:FFC407:59:000:Infinite Time
shdancer1:0:FFC41F:09:000:Infinite Magic
shdancer1:0:FFC490:00:000:Always have the Normal gun
shdancer1:0:FFC490:01:000:Always have the Power-up gun
shdancer1:0:FFC490:00:001:Get the Normal gun Now!
shdancer1:0:FFC490:01:001:Get the Power-up gun Now!
shdancer1:0:FFEB0A:9A:000:Infinite Lives PL1
shdancer1:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Shadow Dancer (Japan) ]
shdancrj:0:FFC407:59:000:Infinite Time
shdancrj:0:FFC41F:09:000:Infinite Magic
shdancrj:0:FFC490:00:000:Always have the Normal gun
shdancrj:0:FFC490:01:000:Always have the Power-up gun
shdancrj:0:FFC490:00:001:Get the Normal gun Now!
shdancrj:0:FFC490:01:001:Get the Power-up gun Now!
shdancrj:0:FFEB0A:9A:000:Infinite Lives PL1
shdancrj:0:FFEB8A:9A:000:Infinite Lives PL2
shdancerj:0:FFC407:59:000:Infinite Time
shdancerj:0:FFC41F:09:000:Infinite Magic
shdancerj:0:FFC490:00:000:Always have the Normal gun
shdancerj:0:FFC490:01:000:Always have the Power-up gun
shdancerj:0:FFC490:00:001:Get the Normal gun Now!
shdancerj:0:FFC490:01:001:Get the Power-up gun Now!
shdancerj:0:FFEB0A:9A:000:Infinite Lives PL1
shdancerj:0:FFEB8A:9A:000:Infinite Lives PL2
; [ Sheriff ]
sheriff:0:6035:FF:000:Invincibility
@@ -138673,16 +138633,6 @@ wtennis:0:00C1:00:001:Set 'HER' to 0 Now! PL2
wtennis:0:00C2:03:001:Set 'HIS' to 3 Now! PL2
wtennis:0:00C1:03:001:Set 'HER' to 3 Now! PL2
; [ Where's Wally? ]
wwally:0:0000:00:999:[ There are no cheats ]:REASON 1
wwally:0:0000:00:999:[ for this game as it ]:REASON 1
wwally:0:0000:00:999:[ didn't work the last ]:REASON 1
wwally:0:0000:00:999:[ time it was tested. ]:REASON 1
wwally:0:0000:00:999:[ If the game now works ]:REASON 1
wwally:0:0000:00:999:[ please request cheats ]:REASON 1
wwally:0:0000:00:999:[ for it on the cheat ]:REASON 1
wwally:0:0000:00:999:[ forums. ]:REASON 1
; [ Wild Western (set 2) ]
wwester1:0:8620:03:000:Infinite Lives
wwester1:0:0000:00:999:[See the Dip Switch Menu to ]
metadata/history.dat
+2 -2
View File
@@ -84877,7 +84877,7 @@ The US version has the "Recycle It, Don't Trash It!" screen.
$end
$info=mp_gaxe2,
$info=mp_gaxe2,mp_gaxe2a,
$bio
Golden Axe II (c) 1993 Sega.
@@ -242217,7 +242217,7 @@ Directed by : Strong Shima
$end
$info=mp_twc,
$info=mp_twcup,
$bio
Tecmo World Cup (c) 1993 Sega.
metadata/mame2003-plus.xml
+20375 -3497
View File
File diff suppressed because it is too large. Load diff
src/cpu/h6280/h6280.c
+26
View File
@@ -60,6 +60,7 @@
#include "memory.h"
#include "cpuintrf.h"
#include "state.h"
#include "mamedbg.h"
#include "h6280.h"
@@ -138,6 +139,31 @@ UINT8 H6280_debug_mmr[8];
/*****************************************************************************/
void h6280_init(void)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT32("h6280", cpu, "PPC", &h6280.ppc.d, 1);
state_save_register_UINT32("h6280", cpu, "PC", &h6280.pc.d, 1);
state_save_register_UINT32("h6280", cpu, "SP", &h6280.sp.d, 1);
state_save_register_UINT32("h6280", cpu, "ZP", &h6280.zp.d, 1);
state_save_register_UINT32("h6280", cpu, "EA", &h6280.ea.d, 1);
state_save_register_UINT8("h6280", cpu, "A", &h6280.a, 1);
state_save_register_UINT8("h6280", cpu, "X", &h6280.x, 1);
state_save_register_UINT8("h6280", cpu, "Y", &h6280.y, 1);
state_save_register_UINT8("h6280", cpu, "P", &h6280.p, 1);
state_save_register_UINT8("h6280", cpu, "MMR", h6280.mmr, 8);
state_save_register_UINT8("h6280", cpu, "IRQ_MASK", &h6280.irq_mask, 1);
state_save_register_UINT8("h6280", cpu, "TIMER_STATUS", &h6280.timer_status, 1);
state_save_register_UINT8("h6280", cpu, "TIMER_ACK", &h6280.timer_ack, 1);
state_save_register_int("h6280", cpu, "TIMER_VALUE", &h6280.timer_value);
state_save_register_int("h6280", cpu, "TIMER_LOAD", &h6280.timer_load);
state_save_register_int("h6280", cpu, "EXTRA_CYCLES", &h6280.extra_cycles);
state_save_register_int("h6280", cpu, "NMI_STATE", &h6280.nmi_state);
state_save_register_int("h6280", cpu, "IRQ1_STATE", &h6280.irq_state[0]);
state_save_register_int("h6280", cpu, "IRQ2_STATE", &h6280.irq_state[1]);
state_save_register_int("h6280", cpu, "IRQT_STATE", &h6280.irq_state[2]);
#if LAZY_FLAGS
state_save_register_int("h6280", cpu, "NZ", &h6280.NZ);
#endif
}
void h6280_reset(void *param)
src/cpu/hd6309/hd6309.c
+3
View File
@@ -587,6 +587,8 @@ void hd6309_init(void)
state_save_register_UINT16("hd6309", cpu, "X", &X, 1);
state_save_register_UINT16("hd6309", cpu, "Y", &Y, 1);
state_save_register_UINT16("hd6309", cpu, "V", &V, 1);
state_save_register_UINT16("hd6309", cpu, "D", &D, 1); /* the accumulators A and B */
state_save_register_UINT16("hd6309", cpu, "W", &W, 1); /* the accumulators E and F */
state_save_register_UINT8("hd6309", cpu, "DP", &DP, 1);
state_save_register_UINT8("hd6309", cpu, "CC", &CC, 1);
state_save_register_UINT8("hd6309", cpu, "MD", &MD, 1);
@@ -595,6 +597,7 @@ void hd6309_init(void)
state_save_register_UINT8("hd6309", cpu, "NMI", &hd6309.nmi_state, 1);
state_save_register_UINT8("hd6309", cpu, "IRQ", &hd6309.irq_state[0], 1);
state_save_register_UINT8("hd6309", cpu, "FIRQ", &hd6309.irq_state[1], 1);
state_save_register_int("hd6309", cpu, "extra_cycles", &hd6309.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
/****************************************************************************/
src/cpu/i86/i86.c
+48
View File
@@ -63,6 +63,7 @@ typedef struct
INT8 nmi_state;
INT8 irq_state;
int extra_cycles; /* extra cycles for interrupts */
INT8 test_state; /* the TEST input */
}
i86_Regs;
@@ -123,12 +124,53 @@ static void i86_state_register(void)
state_save_register_INT8( type, cpu, "NMI_STATE", &I.nmi_state, 1);
state_save_register_INT8( type, cpu, "IRQ_STATE", &I.irq_state, 1);
state_save_register_int( type, cpu, "EXTRA_CYCLES", &I.extra_cycles);
state_save_register_INT8( type, cpu, "TEST_STATE", &I.test_state, 1);
}
/* the 16-bit data bus, see i86intf.h */
int i86_bus16;
int i86_bus16_word;
unsigned i86_read_word16(unsigned ea)
{
unsigned lo, hi;
/* an odd address is two byte cycles on the 8086 too */
if (ea & 1)
{
lo = cpu_readmem20(ea);
hi = cpu_readmem20((ea + 1) & AMASK);
return lo | (hi << 8);
}
i86_bus16_word = 1;
lo = cpu_readmem20(ea);
hi = cpu_readmem20(ea + 1);
i86_bus16_word = 0;
return lo | (hi << 8);
}
void i86_write_word16(unsigned ea, unsigned val)
{
if (ea & 1)
{
cpu_writemem20(ea, val & 0xff);
cpu_writemem20((ea + 1) & AMASK, (val >> 8) & 0xff);
return;
}
i86_bus16_word = 1;
cpu_writemem20(ea, val & 0xff);
cpu_writemem20(ea + 1, (val >> 8) & 0xff);
i86_bus16_word = 0;
}
void i86_init(void)
{
unsigned int i, j, c;
BREGS reg_name[8] = {AL, CL, DL, BL, AH, CH, DH, BH};
/* the 16-bit data bus is off unless the driver turns it on */
i86_bus16 = 0;
i86_bus16_word = 0;
for (i = 0; i < 256; i++)
{
for (j = i, c = 0; j > 0; j >>= 1)
@@ -157,6 +199,7 @@ void i86_reset(void *param)
{
memset(&I, 0, sizeof (I));
I.test_state = 1;
I.sregs[CS] = 0xf000;
I.base[CS] = SegBase(CS);
I.pc = 0xffff0 & AMASK;
@@ -287,6 +330,11 @@ void i86_set_reg(int regnum, unsigned val)
void i86_set_irq_line(int irqline, int state)
{
if (irqline == I86_TEST_LINE)
{
I.test_state = (state != CLEAR_LINE);
return;
}
if (irqline == IRQ_LINE_NMI)
{
if (I.nmi_state == state)
src/cpu/i86/i86.h
+8 -4
View File
@@ -71,20 +71,24 @@ typedef enum { AL,AH,CL,CH,DL,DH,BL,BH,SPL,SPH,BPL,BPH,SIL,SIH,DIL,DIH } BREGS;
/************************************************************************/
/* the 16-bit data bus of the 8086 (see i86intf.h): off unless a driver turns it on */
unsigned i86_read_word16(unsigned ea);
void i86_write_word16(unsigned ea, unsigned val);
#define SegBase(Seg) (I.sregs[Seg] << 4)
#define DefaultBase(Seg) ((seg_prefix && (Seg == DS || Seg == SS)) ? prefix_base : I.base[Seg])
#define GetMemB(Seg,Off) (cpu_readmem20((DefaultBase(Seg) + (Off)) & AMASK))
#define GetMemW(Seg,Off) ((WORD)GetMemB(Seg, Off) + (WORD)(GetMemB(Seg, (Off) + 1) << 8))
#define GetMemW(Seg,Off) (i86_bus16 ? i86_read_word16((DefaultBase(Seg) + (Off)) & AMASK) : ((WORD)GetMemB(Seg, Off) + (WORD)(GetMemB(Seg, (Off) + 1) << 8)))
#define PutMemB(Seg,Off,x) cpu_writemem20((DefaultBase(Seg) + (Off)) & AMASK, (x))
#define PutMemW(Seg,Off,x) { PutMemB(Seg, Off, (x) & 0xff); PutMemB(Seg, (Off) + 1, ((x) >> 8) & 0xff); }
#define PutMemW(Seg,Off,x) { if (i86_bus16) i86_write_word16((DefaultBase(Seg) + (Off)) & AMASK, (x)); else { PutMemB(Seg, Off, (x) & 0xff); PutMemB(Seg, (Off) + 1, ((x) >> 8) & 0xff); } }
#define PEEKBYTE(ea) (cpu_readmem20((ea) & AMASK))
#define ReadByte(ea) (cpu_readmem20((ea) & AMASK))
#define ReadWord(ea) (cpu_readmem20((ea) & AMASK) + (cpu_readmem20(((ea) + 1) & AMASK) << 8))
#define ReadWord(ea) (i86_bus16 ? i86_read_word16((ea) & AMASK) : (cpu_readmem20((ea) & AMASK) + (cpu_readmem20(((ea) + 1) & AMASK) << 8)))
#define WriteByte(ea,val) cpu_writemem20((ea) & AMASK, val);
#define WriteWord(ea,val) { cpu_writemem20((ea) & AMASK, (val) & 0xff); cpu_writemem20(((ea) + 1) & AMASK, ((val) >> 8) & 0xff); }
#define WriteWord(ea,val) { if (i86_bus16) i86_write_word16((ea) & AMASK, (val)); else { cpu_writemem20((ea) & AMASK, (val) & 0xff); cpu_writemem20(((ea) + 1) & AMASK, ((val) >> 8) & 0xff); } }
#define read_port(port) cpu_readport16(port)
#define write_port(port,val) cpu_writeport16(port,val)
src/cpu/i86/i86intf.h
+14
View File
@@ -11,9 +11,23 @@ enum {
I86_VECTOR, I86_PENDING, I86_NMI_STATE, I86_IRQ_STATE
};
/* the TEST input (WAIT instruction): a CPU waits at a WAIT instruction
while it is cleared; it is asserted at reset, so WAIT goes on unless a
driver clears it */
#define I86_TEST_LINE 1
/* Public variables */
extern int i86_ICount;
/* The 8086 has a 16-bit data bus, but the core accesses memory a byte at a
time. A driver whose hardware needs an aligned word access to be one bus
cycle sets i86_bus16 (all the i86 CPUs of the machine): the core then
accesses an aligned word as its low byte then its high byte, with
i86_bus16_word set during the two accesses, so the handlers can make
them one 16-bit access. Off by default: nothing changes for the others. */
extern int i86_bus16;
extern int i86_bus16_word;
/* Public functions */
extern void i86_init(void);
src/cpu/i86/instr86.c
+37 -8
View File
@@ -544,8 +544,13 @@ static void PREFIX(rep)(int flagval)
for (; count > 0; count--)
{
if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
if (i86_bus16)
PutMemW(ES,I.regs.w[DI],I.regs.w[AX])
else
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
}
I.regs.w[DI] += 2 * I.DirVal;
ICOUNT -= cycles.rep_stos16_count;
}
@@ -1994,6 +1999,15 @@ static void PREFIX86(_call_far)(void)
static void PREFIX86(_wait)(void) /* Opcode 0x9b */
{
#ifndef I286
/* the TEST input cleared: wait on this instruction */
if (!I.test_state)
{
ICOUNT = 0;
I.pc--;
return;
}
#endif
ICOUNT -= cycles.wait;
}
@@ -2060,8 +2074,13 @@ static void PREFIX86(_mov_axdisp)(void) /* Opcode 0xa1 */
addr += FETCH << 8;
ICOUNT -= cycles.mov_am16;
I.regs.b[AL] = GetMemB(DS, addr);
I.regs.b[AH] = GetMemB(DS, addr+1);
if (i86_bus16)
I.regs.w[AX] = GetMemW(DS, addr);
else
{
I.regs.b[AL] = GetMemB(DS, addr);
I.regs.b[AH] = GetMemB(DS, addr+1);
}
}
static void PREFIX86(_mov_dispal)(void) /* Opcode 0xa2 */
@@ -2083,8 +2102,13 @@ static void PREFIX86(_mov_dispax)(void) /* Opcode 0xa3 */
addr += FETCH << 8;
ICOUNT -= cycles.mov_ma16;
PutMemB(DS, addr, I.regs.b[AL]);
PutMemB(DS, addr+1, I.regs.b[AH]);
if (i86_bus16)
PutMemW(DS, addr, I.regs.w[AX])
else
{
PutMemB(DS, addr, I.regs.b[AL]);
PutMemB(DS, addr+1, I.regs.b[AH]);
}
}
static void PREFIX86(_movsb)(void) /* Opcode 0xa4 */
@@ -2148,8 +2172,13 @@ static void PREFIX86(_stosb)(void) /* Opcode 0xaa */
static void PREFIX86(_stosw)(void) /* Opcode 0xab */
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
if (i86_bus16)
PutMemW(ES,I.regs.w[DI],I.regs.w[AX])
else
{
PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
PutMemB(ES,I.regs.w[DI]+1,I.regs.b[AH]);
}
I.regs.w[DI] += 2 * I.DirVal;
ICOUNT -= cycles.stos16;
}
src/cpu/i960/i960.c
+34 -2
View File
@@ -120,9 +120,33 @@ static INLINE int i960_is_burst( UINT32 address )
return i960_burst_cb == NULL || i960_burst_cb( address );
}
/* port: the opcodes are read straight from the memory block of the last
fetch (ROM, RAM or a bank: what cpu_readmem32ledw_dword reads there);
anything else goes through the memory system. Forgotten at every
timeslice, as the banks are only set up between them */
static UINT32 i960_fetch_start, i960_fetch_len;
static const UINT8 *i960_fetch_ptr;
static UINT32 i960_readop_slow( UINT32 address )
{
offs_t start, len;
const UINT8 *p = (const UINT8 *)memory_get_read_range( cpu_getactivecpu(), address, &start, &len );
if( p != NULL )
{
/* the block in the CPU's addresses (the mask only drops high bits) */
i960_fetch_start = address - ( ( address & mem_amask ) - start );
i960_fetch_len = len;
i960_fetch_ptr = p;
}
return cpu_readmem32ledw_dword( address );
}
static INLINE UINT32 i960_readop( UINT32 address )
{
return cpu_readmem32ledw_dword( address );
UINT32 off = address - i960_fetch_start;
if( off < i960_fetch_len )
return *(const data32_t *)( i960_fetch_ptr + ( off & ~3 ) );
return i960_readop_slow( address );
}
static void i960_fatal( const char *fmt, ... )
@@ -880,7 +904,14 @@ static void execute_burst_stall_op(UINT32 opcode)
check_immediate_irqs();
}
static void execute_op(UINT32 opcode)
/* port: inlined in its only caller, the i960_execute loop: as a function,
saving and restoring its registers on every instruction cost a fifth of
the time spent in the CPU */
#if defined(__GNUC__)
static INLINE __attribute__((always_inline)) void execute_op(UINT32 opcode)
#else
static INLINE void execute_op(UINT32 opcode)
#endif
{
UINT32 t1, t2;
double t1f, t2f;
@@ -2521,6 +2552,7 @@ int i960_execute( int cycles )
UINT32 opcode;
i960_icount = cycles;
i960_fetch_len = 0;
/* delay checking irqs if we are in burst stall mode */
if( m_stall_state.burst_mode == 0 )
src/cpu/konami/konami.c
+1
View File
@@ -483,6 +483,7 @@ void konami_init(void)
state_save_register_UINT8("konami", cpu, "NMI", &konami.nmi_state, 1);
state_save_register_UINT8("konami", cpu, "IRQ", &konami.irq_state[0], 1);
state_save_register_UINT8("konami", cpu, "FIRQ", &konami.irq_state[1], 1);
state_save_register_int("konami", cpu, "extra_cycles", &konami.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
void konami_reset(void *param)
src/cpu/m37710/m37710.c
+22 -7
View File
@@ -413,6 +413,9 @@ static void m37710_timer_b2_cb(int param)
cpuintrf_pop_context();
}
/* timer A output pins (set by the driver just before it clocks the timer, not saved) */
static int m37710_timer_out[5];
static void m37710_external_tick(int timer, int state)
{
/* we only care if the state is "on" */
@@ -426,15 +429,22 @@ static void m37710_external_tick(int timer, int state)
{
if ((m37710i_cpu.m37710_regs[0x56+timer] & 0x3) == 1)
{
if (m37710i_cpu.m37710_regs[0x46+(timer*2)] == 0xff)
/* the count direction, as current MAME: timer B counts down; timer A
follows its output pin (mode bit 4) or the up/down register */
int upcount = 0;
UINT16 count = m37710i_cpu.m37710_regs[0x46+(timer*2)] | (m37710i_cpu.m37710_regs[0x46+(timer*2)+1] << 8);
if (timer <= 4)
{
m37710i_cpu.m37710_regs[0x46+(timer*2)] = 0;
m37710i_cpu.m37710_regs[0x46+(timer*2)+1]++;
}
else
{
m37710i_cpu.m37710_regs[0x46+(timer*2)]++;
if (m37710i_cpu.m37710_regs[0x56+timer] & 0x10)
upcount = m37710_timer_out[timer];
else
upcount = (m37710i_cpu.m37710_regs[0x44] >> timer) & 1;
}
count = upcount ? count + 1 : count - 1;
m37710i_cpu.m37710_regs[0x46+(timer*2)] = count & 0xff;
m37710i_cpu.m37710_regs[0x46+(timer*2)+1] = count >> 8;
}
else
{
@@ -1086,6 +1096,11 @@ void m37710_set_irq_line(int line, int state)
m37710_external_tick(line - M37710_LINE_TIMERA0TICK, state);
return;
}
if (line >= M37710_LINE_TIMERA0OUT && line <= M37710_LINE_TIMERA4OUT)
{
m37710_timer_out[line - M37710_LINE_TIMERA0OUT] = (state != CLEAR_LINE);
return;
}
FTABLE_SET_LINE(line, state);
}
src/cpu/m37710/m37710.h
+7
View File
@@ -63,6 +63,13 @@ enum
M37710_LINE_TIMERB1TICK,
M37710_LINE_TIMERB2TICK,
/* timer A output pins: the count direction of an event counter in up/down pin mode */
M37710_LINE_TIMERA0OUT,
M37710_LINE_TIMERA1OUT,
M37710_LINE_TIMERA2OUT,
M37710_LINE_TIMERA3OUT,
M37710_LINE_TIMERA4OUT,
M37710_LINE_MAX
};
src/cpu/m6800/m6800.c
+18
View File
@@ -554,6 +554,24 @@ static void state_register(const char *type)
state_save_register_UINT8 (type, cpu, "NMI_STATE", &m6800.nmi_state, 1);
state_save_register_UINT8 (type, cpu, "IRQ_STATE", &m6800.irq_state[M6800_IRQ_LINE], 1);
state_save_register_UINT8 (type, cpu, "TIN_STATE", &m6800.irq_state[M6800_TIN_LINE], 1);
state_save_register_UINT16(type, cpu, "PPC", &m6800.ppc.w.l, 1);
state_save_register_UINT8 (type, cpu, "WAI_STATE", &m6800.wai_state, 1);
state_save_register_UINT8 (type, cpu, "IC_EDDGE", &m6800.ic_eddge, 1);
state_save_register_int (type, cpu, "EXTRA_CYCLES", &m6800.extra_cycles);
/* the internal registers of the 6801/6803/63701: ports, timer, RAM control */
state_save_register_UINT8 (type, cpu, "PORT1_DDR", &m6800.port1_ddr, 1);
state_save_register_UINT8 (type, cpu, "PORT2_DDR", &m6800.port2_ddr, 1);
state_save_register_UINT8 (type, cpu, "PORT1_DATA", &m6800.port1_data, 1);
state_save_register_UINT8 (type, cpu, "PORT2_DATA", &m6800.port2_data, 1);
state_save_register_UINT8 (type, cpu, "TCSR", &m6800.tcsr, 1);
state_save_register_UINT8 (type, cpu, "PENDING_TCSR", &m6800.pending_tcsr, 1);
state_save_register_UINT8 (type, cpu, "IRQ2", &m6800.irq2, 1);
state_save_register_UINT8 (type, cpu, "RAM_CTRL", &m6800.ram_ctrl, 1);
state_save_register_UINT32(type, cpu, "COUNTER", &m6800.counter.d, 1);
state_save_register_UINT32(type, cpu, "OUTPUT_COMPARE", &m6800.output_compare.d, 1);
state_save_register_UINT16(type, cpu, "INPUT_CAPTURE", &m6800.input_capture, 1);
state_save_register_UINT32(type, cpu, "TIMER_OVER", &m6800.timer_over.d, 1);
state_save_register_UINT32(type, cpu, "TIMER_NEXT", &timer_next, 1);
}
void m6800_init(void)
src/cpu/m6809/m6809.c
+2
View File
@@ -512,12 +512,14 @@ void m6809_init(void)
state_save_register_UINT16("m6809", cpu, "S", &S, 1);
state_save_register_UINT16("m6809", cpu, "X", &X, 1);
state_save_register_UINT16("m6809", cpu, "Y", &Y, 1);
state_save_register_UINT16("m6809", cpu, "D", &D, 1); /* the accumulators A and B */
state_save_register_UINT8("m6809", cpu, "DP", &DP, 1);
state_save_register_UINT8("m6809", cpu, "CC", &CC, 1);
state_save_register_UINT8("m6809", cpu, "INT", &m6809.int_state, 1);
state_save_register_UINT8("m6809", cpu, "NMI", &m6809.nmi_state, 1);
state_save_register_UINT8("m6809", cpu, "IRQ", &m6809.irq_state[0], 1);
state_save_register_UINT8("m6809", cpu, "FIRQ", &m6809.irq_state[1], 1);
state_save_register_int("m6809", cpu, "extra_cycles", &m6809.extra_cycles); /* the cycles of an interrupt taken outside the execute loop */
}
void m6809_reset(void *param)
src/cpu/mb86233/mb86233.c
+2
View File
@@ -1160,6 +1160,8 @@ void mb86233_init( void )
state_save_register_int( "mb86233", cpu, "gpio1", &mb.gpio[ 1 ] );
state_save_register_int( "mb86233", cpu, "gpio2", &mb.gpio[ 2 ] );
state_save_register_int( "mb86233", cpu, "gpio3", &mb.gpio[ 3 ] );
/* a stalled FIFO access is retried when the CPU runs again */
state_save_register_int( "mb86233", cpu, "stall", &mb.stall );
}
void mb86233_reset( void *param )
src/cpu/namcoc71/c71.c
+1650
View File
File diff suppressed because it is too large. Load diff
src/cpu/namcoc71/c71.h
+75
View File
@@ -0,0 +1,75 @@
/***************************************************************************
Namco C71 (TMS320C25 with Namco internal ROM) - fast DSP core
Written for Namco System 22 / Super System 22. The instruction
semantics follow the TMS320C2x core of current MAME; the memory
system is a page table set up by the driver, so the core does not
go through the generic memory handlers.
Word addresses everywhere: program, data and I/O are 16-bit word
spaces.
***************************************************************************/
#ifndef C71_H
#define C71_H
#include "osd_cpu.h"
#include "cpuintrf.h"
#include "memory.h"
/* interrupt lines (IFR bits) */
#define C71_INT0 0
#define C71_INT1 1
#define C71_INT2 2
#define C71_TINT 3
#define C71_RINT 4
#define C71_XINT 5
enum
{
C71_PC=1,
C71_PFC, C71_STR0, C71_STR1, C71_IFR,
C71_RPTC, C71_ACC, C71_PREG, C71_TREG,
C71_AR0, C71_AR1, C71_AR2, C71_AR3,
C71_AR4, C71_AR5, C71_AR6, C71_AR7,
C71_STK0, C71_STK1, C71_STK2, C71_STK3,
C71_STK4, C71_STK5, C71_STK6, C71_STK7,
C71_DRR, C71_DXR, C71_TIM, C71_PRD,
C71_IMR, C71_GREG
};
/* the generic memory interface is not used: give the CPU empty maps */
#define NAMCOC71_PGM_OFFSET 0
typedef data16_t (*c71_read_fn)(offs_t offset);
typedef void (*c71_write_fn)(offs_t offset, data16_t data);
/* driver configuration, by CPU number; call from DRIVER_INIT or MACHINE_INIT */
void c71_set_internal_rom(int cpunum, const data16_t *rom); /* 0x1000 words, native order (a CPU region) */
void c71_map_data(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
void c71_map_program(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
void c71_set_data_handlers(int cpunum, c71_read_fn rd, c71_write_fn wr); /* everything not mapped */
void c71_set_io(int cpunum, int port, c71_read_fn rd, c71_write_fn wr);
void c71_set_bio(int cpunum, int (*bio)(void));
void c71_set_serial(int cpunum, data16_t (*dr_in)(void), void (*dx_out)(data16_t));
/* the DSP spins in [pc_start, pc_end] waiting for BIO or an interrupt: burn the timeslice there */
void c71_set_idle_loop(int cpunum, int slot, UINT16 pc_start, UINT16 pc_end);
extern int c71_icount;
void c71_init(void);
void c71_reset(void *param);
void c71_exit(void);
int c71_execute(int cycles);
unsigned c71_get_context(void *dst);
void c71_set_context(void *src);
unsigned c71_get_reg(int regnum);
void c71_set_reg(int regnum, unsigned val);
void c71_set_irq_line(int irqline, int state);
void c71_set_irq_callback(int (*callback)(int irqline));
const char *c71_info(void *context, int regnum);
unsigned c71_dasm(char *buffer, unsigned pc);
#endif
src/cpu/pic16c5x/pic16c5x.c
+3 -5
View File
@@ -704,11 +704,9 @@ void pic16C5x_init(void)
state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
/* STATUS and the ports are in the data RAM (picRAM), saved with the memory
of the CPU: R.picRAM is not set yet here */
state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
@@ -858,7 +856,7 @@ int pic16C5x_execute(int cycles)
CALL_MAME_DEBUG;
R.opcode.d = M_RDOP(R.PC);
R.PC++;
R.PC = (R.PC + 1) & ADDR_MASK; /* wraps to 0 after the reset vector 0x7ff of the 2K parts */
R.PCL++;
if ((R.opcode.w.l & 0xff0) != 0x000) { /* Do all opcodes except the 00? ones */
src/cpu/sh2/sh2.c
+187 -100
View File
@@ -147,10 +147,23 @@ typedef struct
int is_slave, cpu_number;
data16_t (*opcode_read)(offs_t pc);
data32_t (*dma_read_hook)(UINT32 src, UINT32 dst, data32_t data, int size);
UINT8 **jit_rpage; /* sh2jit.c: this CPU's page tables for direct reads and writes */
UINT8 **jit_wpage;
} SH2;
int sh2_icount;
static SH2 sh2;
/*
The state of the active SH-2 is its own context buffer: switching
CPUs (every timeslice, many thousand times a frame on the ST-V with
its tight interleave) only moves this pointer instead of copying
the whole state out and in. Each CPU's saved state items point into
its buffer too, so a state save reads it whether it is active or not.
*/
static SH2 sh2_boot; /* before a CPU's buffer is known */
static SH2 *sh2p = &sh2_boot;
#define sh2 (*sh2p)
/* Atrocious hack that makes the soldivid music correct*/
@@ -179,6 +192,16 @@ static void sh2_timer_callback(int data);
#define Rn ((opcode>>8)&15)
#define Rm ((opcode>>4)&15)
#ifdef SH2JIT_VERIFY
extern int sh2_jit_verify_logging;
void sh2_jit_verify_store(UINT32 address, int size);
#define SH2JIT_STORE(A, size) do { if (sh2_jit_verify_logging) sh2_jit_verify_store(A, size); if (sh2_jit_code_present) sh2_jit_ram_written((A) & AM, size); } while (0)
#else
/* a store over translated code flushes the recompiler's cache */
#define SH2JIT_STORE(A, size) do { if (sh2_jit_code_present) sh2_jit_ram_written((A) & AM, size); } while (0)
#endif
static INLINE data8_t RB(offs_t A)
{
if (A >= 0xe0000000)
@@ -233,6 +256,7 @@ static INLINE void WB(offs_t A, data8_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw(A,V);
SH2JIT_STORE(A, 1);
return;
}
@@ -240,6 +264,7 @@ static INLINE void WB(offs_t A, data8_t V)
return;
cpu_writemem32bedw(A & AM,V);
SH2JIT_STORE(A, 1);
}
static INLINE void WW(offs_t A, data16_t V)
@@ -253,6 +278,7 @@ static INLINE void WW(offs_t A, data16_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw_word(A,V);
SH2JIT_STORE(A, 2);
return;
}
@@ -260,6 +286,7 @@ static INLINE void WW(offs_t A, data16_t V)
return;
cpu_writemem32bedw_word(A & AM,V);
SH2JIT_STORE(A, 2);
}
static INLINE void WL(offs_t A, data32_t V)
@@ -273,6 +300,7 @@ static INLINE void WL(offs_t A, data32_t V)
if (A >= 0xc0000000)
{
cpu_writemem32bedw_dword(A,V);
SH2JIT_STORE(A, 4);
return;
}
@@ -280,6 +308,7 @@ static INLINE void WL(offs_t A, data32_t V)
return;
cpu_writemem32bedw_dword(A & AM,V);
SH2JIT_STORE(A, 4);
}
static INLINE void sh2_exception(const char *message, int irqline)
@@ -2291,6 +2320,61 @@ static INLINE void op1111(UINT16 opcode)
NOP();
}
/* one instruction (in the interpreter's loop and for the recompiler's checks) */
static INLINE void sh2_dispatch(UINT16 opcode)
{
switch ((opcode >> 12) & 15)
{
case 0: op0000(opcode); break;
case 1: op0001(opcode); break;
case 2: op0010(opcode); break;
case 3: op0011(opcode); break;
case 4: op0100(opcode); break;
case 5: op0101(opcode); break;
case 6: op0110(opcode); break;
case 7: op0111(opcode); break;
case 8: op1000(opcode); break;
case 9: op1001(opcode); break;
case 10: op1010(opcode); break;
case 11: op1011(opcode); break;
case 12: op1100(opcode); break;
case 13: op1101(opcode); break;
case 14: op1110(opcode); break;
default: op1111(opcode); break;
}
}
static INLINE void sh2_step(void)
{
UINT32 opcode;
if (sh2.delay)
{
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.delay) : RW(sh2.delay & AM);
change_pc32bedw(sh2.pc & AM);
sh2.pc -= 2;
}
else
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.pc) : RW(sh2.pc & AM);
CALL_MAME_DEBUG;
sh2.delay = 0;
sh2.pc += 2;
sh2.ppc = sh2.pc;
sh2_dispatch(opcode);
if(sh2.test_irq && !sh2.delay)
{
CHECK_PENDING_IRQ("mame_sh2_execute");
sh2.test_irq = 0;
}
sh2_icount--;
}
#include "sh2jit.c"
/*****************************************************************************
* MAME CPU INTERFACE
*****************************************************************************/
@@ -2324,6 +2408,10 @@ void sh2_reset(void *param)
sh2.cpu_number = cpu_getactivecpu();
/* code and memory handlers may differ after a reset */
if (jit_enabled)
jit_flush();
sh2.pc = RL(0);
sh2.r[15] = RL(4);
sh2.sr = I;
@@ -2335,11 +2423,15 @@ void sh2_reset(void *param)
/* Shut down CPU core */
void sh2_exit(void)
{
sh2_jit_set(0);
if (sh2.m)
free(sh2.m);
sh2.m = NULL;
/* the core frees the buffers after this */
sh2p = &sh2_boot;
}
/* Execute cycles - returns number of cycles actually run */
int sh2_execute(int cycles)
{
@@ -2350,49 +2442,10 @@ int sh2_execute(int cycles)
do
{
UINT32 opcode;
if (sh2.delay)
{
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.delay) : RW(sh2.delay & AM);
change_pc32bedw(sh2.pc & AM);
sh2.pc -= 2;
}
else
opcode = sh2.opcode_read ? sh2.opcode_read(sh2.pc) : RW(sh2.pc & AM);
CALL_MAME_DEBUG;
sh2.delay = 0;
sh2.pc += 2;
sh2.ppc = sh2.pc;
switch ((opcode >> 12) & 15)
{
case 0: op0000(opcode); break;
case 1: op0001(opcode); break;
case 2: op0010(opcode); break;
case 3: op0011(opcode); break;
case 4: op0100(opcode); break;
case 5: op0101(opcode); break;
case 6: op0110(opcode); break;
case 7: op0111(opcode); break;
case 8: op1000(opcode); break;
case 9: op1001(opcode); break;
case 10: op1010(opcode); break;
case 11: op1011(opcode); break;
case 12: op1100(opcode); break;
case 13: op1101(opcode); break;
case 14: op1110(opcode); break;
default: op1111(opcode); break;
}
if(sh2.test_irq && !sh2.delay)
{
CHECK_PENDING_IRQ("mame_sh2_execute");
sh2.test_irq = 0;
}
sh2_icount--;
/* a block, when there is one for the PC (no slot or interrupt test pending) */
if (jit_enabled && !sh2.delay && !sh2.test_irq && sh2_jit_run())
continue;
sh2_step();
} while( sh2_icount > 0 );
return cycles - sh2_icount;
@@ -2401,16 +2454,17 @@ int sh2_execute(int cycles)
/* Get registers, return context size */
unsigned sh2_get_context(void *dst)
{
if( dst )
memcpy(dst, &sh2, sizeof(SH2));
if( dst && dst != (void *)sh2p )
memcpy(dst, sh2p, sizeof(SH2));
return sizeof(SH2);
}
/* Set registers */
void sh2_set_context(void *src)
{
/* the core passes a CPU's own buffer: it becomes the live state */
if( src )
memcpy(&sh2, src, sizeof(SH2));
sh2p = (SH2 *)src;
}
static void sh2_timer_resync(void)
@@ -2597,6 +2651,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst --;
cpu_writemem32bedw(dst, DMA_READ(src, dst, cpu_readmem32bedw(src), 0));
SH2JIT_STORE(dst, 1);
if(incs == 1)
src ++;
if(incd == 1)
@@ -2613,6 +2668,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst -= 2;
cpu_writemem32bedw_word(dst, DMA_READ(src, dst, cpu_readmem32bedw_word(src), 1));
SH2JIT_STORE(dst, 2);
if(incs == 1)
src += 2;
if(incd == 1)
@@ -2629,6 +2685,7 @@ static void sh2_dmac_check(int dma)
if(incd == 2)
dst -= 4;
cpu_writemem32bedw_dword(dst, DMA_READ(src, dst, cpu_readmem32bedw_dword(src), 2));
SH2JIT_STORE(dst, 4);
if(incs == 1)
src += 4;
if(incd == 1)
@@ -2647,6 +2704,7 @@ static void sh2_dmac_check(int dma)
cpu_writemem32bedw_dword(dst+4, DMA_READ(src+4, dst+4, cpu_readmem32bedw_dword(src+4), 2));
cpu_writemem32bedw_dword(dst+8, DMA_READ(src+8, dst+8, cpu_readmem32bedw_dword(src+8), 2));
cpu_writemem32bedw_dword(dst+12, DMA_READ(src+12, dst+12, cpu_readmem32bedw_dword(src+12), 2));
SH2JIT_STORE(dst, 16);
src += 16;
if(incd == 1)
dst += 16;
@@ -2666,6 +2724,46 @@ static void sh2_dmac_check(int dma)
}
}
/* the division unit, as in current MAME (sh7604.cpp) */
static void sh2_divu_start(INT64 dividend)
{
INT32 divisor = (INT32)sh2.m[0x40];
INT64 remainder;
UINT32 quotient;
int i, negative;
sh2.m[0x41] = (UINT32)dividend;
if (divisor && (dividend != (INT64)((UINT64)1 << 63) || divisor != -1))
{
INT64 q = dividend / divisor;
if (q == (INT32)q)
{
sh2.m[0x45] = (UINT32)q;
sh2.m[0x44] = (UINT32)(dividend % divisor);
return;
}
}
/* overflow (zero divisor or a quotient outside 32 bits): the unit stops after three
steps, leaving the partial remainder in DVDNTH; with OVFIE clear DVDNTL saturates */
remainder = dividend >> 32;
quotient = (UINT32)dividend;
for (i = 0; i < 3; i++)
{
int subtract = (remainder < 0) == (divisor < 0);
remainder = (remainder << 1) | ((quotient >> 31) & 1);
quotient <<= 1;
remainder += subtract ? -(INT64)divisor : (INT64)divisor;
quotient |= ((remainder < 0) == (divisor < 0)) ? 1 : 0;
}
negative = (dividend < 0) != (divisor < 0);
sh2.m[0x44] = (UINT32)remainder;
sh2.m[0x45] = (sh2.m[0x42] & 2) ? quotient : negative ? 0x80000000 : 0x7fffffff;
sh2.m[0x42] |= 1;
sh2_recalc_irq();
}
WRITE32_HANDLER( sh2_internal_w )
{
UINT32 old = sh2.m[offset];
@@ -2728,64 +2826,19 @@ WRITE32_HANDLER( sh2_internal_w )
/* Division box*/
case 0x40: /* DVSR*/
break;
case 0x41: /* DVDNT*/
{
INT32 a = sh2.m[0x41];
INT32 b = sh2.m[0x40];
log_cb(RETRO_LOG_DEBUG, LOGPRE "SH2 #%d div+mod %d/%d\n", cpu_getactivecpu(), a, b);
if (b)
{
sh2.m[0x45] = a / b;
sh2.m[0x44] = a % b;
}
else
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
break;
}
case 0x42: /* DVCR*/
sh2.m[0x42] = (sh2.m[0x42] & ~0x00001000) | (old & sh2.m[0x42] & 0x00010000);
sh2_recalc_irq();
case 0x41: /* DVDNT: a 32-bit division, the dividend sign-extended into DVDNTH */
sh2_divu_start((INT32)sh2.m[0x41]);
break;
case 0x42: /* DVCR: OVF (bit 0) and OVFIE (bit 1) are plain read/write bits */
break;
case 0x43: /* VCRDIV*/
sh2_recalc_irq();
break;
case 0x44: /* DVDNTH*/
break;
case 0x45: /* DVDNTL*/
{
INT64 a = sh2.m[0x45] | ((UINT64)(sh2.m[0x44]) << 32);
INT64 b = sh2.m[0x40];
log_cb(RETRO_LOG_DEBUG, LOGPRE "SH2 #%d div+mod %08x%08x/%08x\n", cpu_getactivecpu(), sh2.m[0x44], sh2.m[0x45], sh2.m[0x40]);
if (b)
{
INT64 q = a / b;
if (q != (INT32)q)
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
else
{
sh2.m[0x45] = q;
sh2.m[0x44] = a % b;
}
}
else
{
sh2.m[0x42] |= 0x00010000;
sh2.m[0x45] = 0x7fffffff;
sh2.m[0x44] = 0x7fffffff;
sh2_recalc_irq();
}
break;
}
case 0x45: /* DVDNTL: a 64-bit division of DVDNTH:DVDNTL */
sh2_divu_start((INT64)(((UINT64)sh2.m[0x44] << 32) | sh2.m[0x45]));
break;
/* DMA controller*/
case 0x60: /* SAR0*/
@@ -2840,7 +2893,11 @@ READ32_HANDLER( sh2_internal_r )
switch( offset )
{
case 0x04: /* TIER, FTCSR, FRC*/
sh2_timer_resync();
/* only a read of FRC brings it up to date, as in current MAME (frc_r):
reading TIER or FTCSR does not (a slave CPU waiting for its input
capture flag reads FTCSR tens of thousands of times a frame) */
if ((mem_mask & 0xffff) != 0xffff)
sh2_timer_resync();
return (sh2.m[4] & 0xffff0000) | sh2.frc;
case 0x05: /* OCRx, TCR, TOCR*/
if(sh2.m[5] & 0x10)
@@ -3096,6 +3153,12 @@ void sh2_init(void)
{
int cpu = cpu_getactivecpu();
/* this CPU's buffer from now on (the core allocated it before the init) */
sh2p = (SH2 *)cpunum_get_context_buffer(cpu);
if (!sh2p)
sh2p = &sh2_boot;
memset(sh2p, 0, sizeof(SH2));
sh2.timer = timer_alloc(sh2_timer_callback);
timer_adjust(sh2.timer, TIME_NEVER, 0, 0);
@@ -3136,5 +3199,29 @@ void sh2_init(void)
state_save_register_UINT32("sh2", cpu, "R13", &sh2.r[13], 1);
state_save_register_UINT32("sh2", cpu, "R14", &sh2.r[14], 1);
state_save_register_UINT32("sh2", cpu, "EA", &sh2.ea, 1);
/* the rest of the CPU: the delay slot, the divider, the interrupts and
the on-chip modules (their registers, the free running timer, the DMA) */
state_save_register_UINT32("sh2", cpu, "PPC", &sh2.ppc, 1);
state_save_register_UINT32("sh2", cpu, "delay", &sh2.delay, 1);
state_save_register_UINT32("sh2", cpu, "cpu_off", &sh2.cpu_off, 1);
state_save_register_UINT32("sh2", cpu, "dvsr", &sh2.dvsr, 1);
state_save_register_UINT32("sh2", cpu, "dvdnth", &sh2.dvdnth, 1);
state_save_register_UINT32("sh2", cpu, "dvdntl", &sh2.dvdntl, 1);
state_save_register_UINT32("sh2", cpu, "dvcr", &sh2.dvcr, 1);
state_save_register_UINT32("sh2", cpu, "pending_irq", &sh2.pending_irq, 1);
state_save_register_UINT32("sh2", cpu, "test_irq", &sh2.test_irq, 1);
state_save_register_INT32("sh2", cpu, "irq_queue", (INT32 *)sh2.irq_queue, 16 * 2);
state_save_register_INT8("sh2", cpu, "irq_line_state", sh2.irq_line_state, 16);
state_save_register_INT8("sh2", cpu, "nmi_line_state", &sh2.nmi_line_state, 1);
state_save_register_UINT32("sh2", cpu, "m", sh2.m, 0x200 / 4);
state_save_register_UINT16("sh2", cpu, "frc", &sh2.frc, 1);
state_save_register_UINT16("sh2", cpu, "ocra", &sh2.ocra, 1);
state_save_register_UINT16("sh2", cpu, "ocrb", &sh2.ocrb, 1);
state_save_register_UINT16("sh2", cpu, "icr", &sh2.icr, 1);
state_save_register_UINT32("sh2", cpu, "frc_base", &sh2.frc_base, 1);
state_save_register_int("sh2", cpu, "frt_input", &sh2.frt_input);
state_save_register_int("sh2", cpu, "internal_irq_level", &sh2.internal_irq_level);
state_save_register_int("sh2", cpu, "internal_irq_vector", &sh2.internal_irq_vector);
state_save_register_INT32("sh2", cpu, "dma_timer_active", (INT32 *)sh2.dma_timer_active, 2);
return;
}
src/cpu/sh2/sh2.h
+11
View File
@@ -69,6 +69,17 @@ struct sh2_config
data32_t (*dma_read_hook)(UINT32 src, UINT32 dst, data32_t data, int size);
};
/* optional recompiler (sh2jit.c): a driver declares the RAM the CPUs run
from and read directly ('base': host memory of 'start', as the memory
system keeps it), then enables it; anything else stays with the
interpreter. Writes the driver makes there by other means than the
CPUs (DMA) must be reported with sh2_jit_ram_written. */
int sh2_jit_available(void);
void sh2_jit_add_fastram(offs_t start, offs_t end, int readonly, void *base);
void sh2_jit_set(int enable);
void sh2_jit_ram_written(UINT32 address, UINT32 bytes);
extern int sh2_jit_code_present;
extern void sh2_init(void);
extern void sh2_reset (void *param); /* Reset registers to the initial values */
extern void sh2_exit (void); /* Shut down CPU core */
src/cpu/sh2/sh2jit.c
+2229
View File
File diff suppressed because it is too large. Load diff
src/cpu/sh3/sh3.c
+138 -53
View File
@@ -87,6 +87,19 @@ typedef struct
UINT32 ea;
UINT32 sleep_mode;
/* bus timing (first: the fields of every access near the start) */
int cache_timing;
UINT32 cache_port_free;
UINT32 burst_continuation_remaining_cycles;
UINT32 last_access_address;
INT32 last_op_rel; /* see last_op_cycles() */
UINT32 wb_address;
UINT32 last_area_accessed;
UINT32 last_area_accessed_was_write;
UINT32 wb_active_cycles;
UINT32 last_op_cycles_lo, last_op_cycles_hi; /* 64-bit cycle counts, saved */
UINT32 total_cycles_lo, total_cycles_hi;
/* interrupts */
UINT32 pending_irq;
UINT32 test_irq;
@@ -109,26 +122,21 @@ typedef struct
UINT8 dma_timer_active[4];
void *dma_timer[4];
/* cache and bus timing */
UINT32 cache_tag[CACHE_BLOCKS][CACHE_ASSOC];
UINT8 cache_lru[CACHE_BLOCKS][CACHE_ASSOC];
UINT8 cache_dirty[CACHE_BLOCKS][CACHE_ASSOC];
UINT32 wb_address;
UINT32 last_area_accessed;
UINT32 last_area_accessed_was_write;
UINT32 wb_active_cycles;
UINT32 burst_continuation_remaining_cycles;
UINT32 cache_port_free;
UINT32 last_access_address;
UINT32 last_op_cycles_lo, last_op_cycles_hi; /* 64-bit cycle counts, saved */
UINT32 total_cycles_lo, total_cycles_hi;
/* configuration */
int cpunum;
int cache_timing;
int pm_clock;
data8_t (*port_r)(int port);
void (*port_w)(int port, data8_t data);
/* the cache: the most recently used way of each block (the one with
LRU 3) or CACHE_ASSOC, and its tag (CACHE_NO_TAG for no way or a tag
of 0); kept with cache_lru and cache_tag, rebuilt from them when
the cache is cleared or comes from a state */
UINT32 cache_mru_tag[CACHE_BLOCKS];
UINT8 cache_mru[CACHE_BLOCKS];
UINT32 cache_tag[CACHE_BLOCKS][CACHE_ASSOC];
UINT8 cache_lru[CACHE_BLOCKS][CACHE_ASSOC];
UINT8 cache_dirty[CACHE_BLOCKS][CACHE_ASSOC];
} SH3;
int sh3_ICount;
@@ -149,6 +157,11 @@ typedef struct
static sh3_fastram fastram[SH3_FASTRAM_MAX];
static int fastram_count;
/* the region of each 64 KB page of the physical space: its index, -1 for
none, -2 for a page that is not all in one region (looked for one by one) */
#define FASTRAM_PAGE_SHIFT 16
static INT8 fastram_page[(AM + 1) >> FASTRAM_PAGE_SHIFT];
/* the recompiler (sh3jit.c): where its code comes from in RAM, one byte
per 4-byte granule of the physical address; a write there flushes it */
#define JIT_CODEMAP_SIZE (1 << 22)
@@ -175,15 +188,36 @@ static INLINE UINT64 total_cycles(void)
return sh3_exec_base + (sh3_exec_cycles - sh3_ICount);
}
static INLINE UINT64 last_op_cycles(void)
/* the cycle count of the last bus access, kept in 32 bits: relative to
sh3_exec_base, or LAST_OP_FAR when it is more than 2^30 cycles away from
it. The bus timing only compares the cycles elapsed since that access
with small counts, so far is the same as any large count. The exact
64-bit value is in sh3.last_op_cycles_lo/hi for the save states, and
while far. */
#define LAST_OP_NEAR (1 << 30)
#define LAST_OP_FAR ((INT32)0x80000000)
/* the cycles from the last bus access to 'now' (sh3_exec_cycles -
sh3_ICount): exact up to 2^30, and at least 2^30 when more (far: 2^31
and more) or when the access is ahead */
static INLINE UINT32 elapsed_since_last_op(INT32 now)
{
return ((UINT64)sh3.last_op_cycles_hi << 32) | sh3.last_op_cycles_lo;
return (UINT32)now - (UINT32)sh3.last_op_rel;
}
static INLINE void set_last_op_cycles(UINT64 c)
static UINT64 last_op_cycles(void)
{
if (sh3.last_op_rel == LAST_OP_FAR)
return ((UINT64)sh3.last_op_cycles_hi << 32) | sh3.last_op_cycles_lo;
return sh3_exec_base + (INT64)sh3.last_op_rel;
}
static void set_last_op_cycles(UINT64 c)
{
INT64 d = (INT64)(c - sh3_exec_base);
sh3.last_op_cycles_lo = (UINT32)c;
sh3.last_op_cycles_hi = (UINT32)(c >> 32);
sh3.last_op_rel = (d < -LAST_OP_NEAR || d > LAST_OP_NEAR) ? LAST_OP_FAR : (INT32)d;
}
@@ -471,22 +505,26 @@ static INLINE int is_sdram_region(UINT32 address)
return get_area(address) == 3;
}
/* the most recently used way of each block (the one with LRU 3), or
CACHE_ASSOC: derived from cache_lru, rebuilt when cache_mru_valid is 0 */
static UINT8 cache_mru[CACHE_BLOCKS];
static int cache_mru_valid;
#define CACHE_NO_TAG 0xffffffff
static INLINE void cache_set_mru(UINT32 block, UINT32 way)
{
UINT32 tag = sh3.cache_tag[block][way];
sh3.cache_mru[block] = way;
sh3.cache_mru_tag[block] = tag ? tag : CACHE_NO_TAG;
}
static void cache_mru_rebuild(void)
{
UINT32 b, i;
for (b = 0; b < CACHE_BLOCKS; b++)
{
cache_mru[b] = CACHE_ASSOC;
sh3.cache_mru[b] = CACHE_ASSOC;
sh3.cache_mru_tag[b] = CACHE_NO_TAG;
for (i = 0; i < CACHE_ASSOC; i++)
if (sh3.cache_lru[b][i] == CACHE_ASSOC - 1)
cache_mru[b] = i;
cache_set_mru(b, i);
}
cache_mru_valid = 1;
}
static int cache_access(UINT32 address, int write)
@@ -513,7 +551,7 @@ static int cache_access(UINT32 address, int write)
if (sh3.cache_lru[cache_block][j] > sh3.cache_lru[cache_block][i])
sh3.cache_lru[cache_block][j]--;
sh3.cache_lru[cache_block][i] = CACHE_ASSOC - 1;
cache_mru[cache_block] = i;
cache_set_mru(cache_block, i);
}
return 1;
}
@@ -528,7 +566,7 @@ static int cache_access(UINT32 address, int write)
sh3.wb_address = sh3.cache_tag[cache_block][i] * CACHE_LINE_SIZE;
sh3.cache_tag[cache_block][i] = cache_address;
sh3.cache_lru[cache_block][i] = CACHE_ASSOC - 1;
cache_mru[cache_block] = i;
cache_set_mru(cache_block, i);
sh3.cache_dirty[cache_block][i] = write;
for (j = 0; j < CACHE_ASSOC; j++)
if (i != j && sh3.cache_lru[cache_block][j] != 0)
@@ -620,22 +658,22 @@ static void bsc_decode(void)
bsc_valid = 1;
}
static INLINE UINT64 remaining_cycles(UINT64 elapsed, UINT64 cycles)
static INLINE UINT32 remaining_cycles(UINT32 elapsed, UINT32 cycles)
{
return (elapsed < cycles) ? (cycles - elapsed) : 0;
}
static UINT32 access_penalty(UINT32 address, int write)
static UINT32 access_penalty(UINT32 address, int write, INT32 now)
{
int is_in_cache;
UINT64 elapsed_cycles;
UINT32 elapsed_cycles;
UINT32 cpu_penalty = 0;
UINT32 area, bus_penalty = 0;
if (!bsc_valid)
bsc_decode();
is_in_cache = cache_access(address, write);
elapsed_cycles = total_cycles() - last_op_cycles();
elapsed_cycles = elapsed_since_last_op(now);
if (!sh3.cache_port_free)
cpu_penalty++;
@@ -674,7 +712,7 @@ static UINT32 access_penalty(UINT32 address, int write)
if (area != sh3.last_area_accessed || (!sh3.last_area_accessed_was_write && !is_cacheable(address) && write))
{
UINT32 wcr1_idle_cycles = bsc_wcr1[area] * 2;
UINT64 wcr1_idle_cycles_left = remaining_cycles(elapsed_cycles, wcr1_idle_cycles);
UINT32 wcr1_idle_cycles_left = remaining_cycles(elapsed_cycles, wcr1_idle_cycles);
cpu_penalty += (UINT32)wcr1_idle_cycles_left;
elapsed_cycles -= (elapsed_cycles < wcr1_idle_cycles) ? elapsed_cycles : wcr1_idle_cycles;
}
@@ -684,7 +722,7 @@ static UINT32 access_penalty(UINT32 address, int write)
if (sh3.burst_continuation_remaining_cycles > 0)
{
UINT64 burst_cycles_left = remaining_cycles(elapsed_cycles, sh3.burst_continuation_remaining_cycles);
UINT32 burst_cycles_left = remaining_cycles(elapsed_cycles, sh3.burst_continuation_remaining_cycles);
cpu_penalty += (UINT32)burst_cycles_left;
elapsed_cycles -= (elapsed_cycles < sh3.burst_continuation_remaining_cycles) ? elapsed_cycles : sh3.burst_continuation_remaining_cycles;
sh3.burst_continuation_remaining_cycles = 0;
@@ -692,7 +730,7 @@ static UINT32 access_penalty(UINT32 address, int write)
if (sh3.wb_active_cycles > 0)
{
UINT64 wb_cycles_left = remaining_cycles(elapsed_cycles, sh3.wb_active_cycles);
UINT32 wb_cycles_left = remaining_cycles(elapsed_cycles, sh3.wb_active_cycles);
cpu_penalty += (UINT32)wb_cycles_left;
elapsed_cycles -= (elapsed_cycles < sh3.wb_active_cycles) ? elapsed_cycles : sh3.wb_active_cycles;
sh3.wb_active_cycles = 0;
@@ -726,24 +764,19 @@ static UINT32 access_penalty(UINT32 address, int write)
is already the most recent one) and the miss path. A tag of 0 can be in
more than one way (lines never filled), and cache_access() takes the
first one: those go through access_penalty(). */
static INLINE UINT32 access_penalty_fast(UINT32 address, int write)
static INLINE UINT32 access_penalty_fast(UINT32 address, int write, INT32 now)
{
if (is_cacheable(address))
{
UINT32 cache_address = (address & AM) / CACHE_LINE_SIZE;
UINT32 cache_block = cache_address % CACHE_BLOCKS;
UINT32 way;
if (!cache_mru_valid)
cache_mru_rebuild();
way = cache_mru[cache_block];
if (cache_address != 0 && way < CACHE_ASSOC && sh3.cache_tag[cache_block][way] == cache_address)
if (sh3.cache_mru_tag[cache_block] == cache_address)
{
UINT64 elapsed_cycles = total_cycles() - last_op_cycles();
UINT32 elapsed_cycles = elapsed_since_last_op(now);
UINT32 cpu_penalty = sh3.cache_port_free ? 0 : 1;
if (write)
sh3.cache_dirty[cache_block][way] = 1;
sh3.cache_dirty[cache_block][sh3.cache_mru[cache_block]] = 1;
sh3.cache_port_free = !sh3.cache_port_free;
if (elapsed_cycles < 6 && sh3.burst_continuation_remaining_cycles >= 6)
{
@@ -754,19 +787,26 @@ static INLINE UINT32 access_penalty_fast(UINT32 address, int write)
return cpu_penalty;
}
}
return access_penalty(address, write);
return access_penalty(address, write, now);
}
static INLINE void update_access_cycles(UINT32 address, int write)
{
/* the instruction fetch, sampled at the data accesses */
INT32 icount = sh3_ICount;
INT32 now = sh3_exec_cycles - icount;
UINT32 penalty;
if (is_cacheable(sh3.pc))
{
sh3_ICount -= access_penalty_fast(sh3.pc, 0);
set_last_op_cycles(total_cycles());
penalty = access_penalty_fast(sh3.pc, 0, now);
icount -= penalty;
now += penalty;
sh3.last_op_rel = now;
}
sh3_ICount -= access_penalty_fast(address, write);
set_last_op_cycles(total_cycles());
penalty = access_penalty_fast(address, write, now);
icount -= penalty;
sh3.last_op_rel = now + penalty;
sh3_ICount = icount;
}
void sh3_update_access_cycles(UINT32 address, int write)
@@ -793,7 +833,7 @@ static void sh3_cache_invalidate_penalty(void)
memset(sh3.cache_tag, 0, sizeof(sh3.cache_tag));
memset(sh3.cache_lru, 0, sizeof(sh3.cache_lru));
memset(sh3.cache_dirty, 0, sizeof(sh3.cache_dirty));
cache_mru_valid = 0;
cache_mru_rebuild();
if (sh3.cache_timing)
{
/* the uncached fetches of the flush loop, as current MAME */
@@ -1385,6 +1425,27 @@ static void internal_write(UINT32 a, UINT32 data, int size)
memory accesses
***************************************************************************/
static void fastram_build_pages(void)
{
UINT32 p;
int i;
for (p = 0; p < sizeof(fastram_page); p++)
{
UINT32 first = p << FASTRAM_PAGE_SHIFT, last = first + (1 << FASTRAM_PAGE_SHIFT) - 1;
INT8 v = -1;
for (i = 0; i < fastram_count; i++)
{
if (fastram[i].end < first || fastram[i].start > last)
continue;
if (v == -1 && fastram[i].start <= first && fastram[i].end >= last)
v = (INT8)i;
else
v = -2;
}
fastram_page[p] = v;
}
}
void sh3_set_fastram(UINT32 start, UINT32 end, int readonly, data32_t *base)
{
if (fastram_count < SH3_FASTRAM_MAX)
@@ -1395,6 +1456,7 @@ void sh3_set_fastram(UINT32 start, UINT32 end, int readonly, data32_t *base)
fastram[fastram_count].base = (UINT8 *)base;
fastram_count++;
}
fastram_build_pages();
}
/* the regions don't overlap: the one of the previous access first */
@@ -1403,6 +1465,14 @@ static int fastram_last;
static INLINE sh3_fastram *find_fastram(UINT32 a)
{
int i;
if (a <= AM)
{
i = fastram_page[a >> FASTRAM_PAGE_SHIFT];
if (i >= 0)
return &fastram[i];
if (i == -1)
return NULL;
}
if (fastram_last < fastram_count && a >= fastram[fastram_last].start && a <= fastram[fastram_last].end)
return &fastram[fastram_last];
for (i = 0; i < fastram_count; i++)
@@ -2771,9 +2841,12 @@ static void execute_one(UINT16 opcode)
int sh3_execute(int cycles)
{
UINT64 last_op = last_op_cycles();
sh3_ICount = cycles;
sh3_exec_cycles = cycles;
sh3_exec_base = ((UINT64)sh3.total_cycles_hi << 32) | sh3.total_cycles_lo;
set_last_op_cycles(last_op);
/* asleep with nothing to wake up: the cycles go */
if (sh3.sleep_mode == 1 && !sh3.test_irq)
@@ -2818,10 +2891,12 @@ int sh3_execute(int cycles)
{
UINT64 total = sh3_exec_base + (cycles - sh3_ICount);
last_op = last_op_cycles();
sh3.total_cycles_lo = (UINT32)total;
sh3.total_cycles_hi = (UINT32)(total >> 32);
sh3_exec_base = total;
sh3_exec_cycles = sh3_ICount = 0;
set_last_op_cycles(last_op);
}
return cycles - sh3_ICount;
}
@@ -2858,11 +2933,17 @@ void sh3_set_irq_callback(int (*callback)(int irqline))
sh3.irq_callback = callback;
}
static void sh3_presave(void)
{
set_last_op_cycles(last_op_cycles());
}
static void sh3_postload(void)
{
set_last_op_cycles(((UINT64)sh3.last_op_cycles_hi << 32) | sh3.last_op_cycles_lo);
fetch_region = NULL;
bsc_valid = 0;
cache_mru_valid = 0;
cache_mru_rebuild();
jit_flush_pending = 1;
}
@@ -2872,9 +2953,11 @@ void sh3_init(void)
int i;
memset(&sh3, 0, sizeof(sh3));
cache_mru_valid = 0;
cache_mru_rebuild();
set_last_op_cycles(0);
sh3.cpunum = cpu;
fastram_count = 0;
fastram_build_pages();
fetch_region = NULL;
build_special_tables();
@@ -2927,6 +3010,7 @@ void sh3_init(void)
state_save_register_UINT32("sh3", cpu, "last_op_hi", &sh3.last_op_cycles_hi, 1);
state_save_register_UINT32("sh3", cpu, "total_lo", &sh3.total_cycles_lo, 1);
state_save_register_UINT32("sh3", cpu, "total_hi", &sh3.total_cycles_hi, 1);
state_save_register_func_presave(sh3_presave);
state_save_register_func_postload(sh3_postload);
}
@@ -2952,7 +3036,7 @@ void sh3_reset(void *param)
irq_callback = sh3.irq_callback;
memset(&sh3, 0, sizeof(sh3));
cache_mru_valid = 0;
cache_mru_rebuild();
for (i = 0; i < 3; i++)
sh3.timer[i] = timer[i];
for (i = 0; i < 4; i++)
@@ -2961,6 +3045,7 @@ void sh3_reset(void *param)
sh3.cpunum = cpunum;
sh3.total_cycles_lo = total_lo;
sh3.total_cycles_hi = total_hi;
set_last_op_cycles(0);
if (conf)
{
@@ -3028,7 +3113,7 @@ void sh3_set_context(void *src)
memcpy(&sh3, src, sizeof(sh3));
fetch_region = NULL;
bsc_valid = 0;
cache_mru_valid = 0;
cache_mru_rebuild();
}
unsigned sh3_get_reg(int regnum)
src/cpu/sharc/sharc.c
+2 -1
View File
@@ -1188,7 +1188,8 @@ int sharc_execute(int cycles)
}
}
if (!m_core->write_stalled)
/* port: no call when channels 6 and 7 are idle (most instructions) */
if (!m_core->write_stalled && (m_core->dma_status & ((1 << 6) | (1 << 7))))
{
dma_stalled = dma_run_cycle(6);
dma_stalled |= dma_run_cycle(7);
src/cpu/z80/z80.c
+6
View File
@@ -3487,6 +3487,7 @@ if( _BC > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x0b] + \
cc[Z80_TABLE_op][0x78] + \
cc[Z80_TABLE_op][0xb1] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3505,6 +3506,7 @@ if( _BC > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x0b] + \
cc[Z80_TABLE_op][0x78] + \
cc[Z80_TABLE_op][0xb1] + \
cc[Z80_TABLE_op][0xc2] + \
@@ -3530,6 +3532,7 @@ if( _DE > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x1b] + \
cc[Z80_TABLE_op][0x7a] + \
cc[Z80_TABLE_op][0xb3] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3548,6 +3551,7 @@ if( _DE > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x1b] + \
cc[Z80_TABLE_op][0x7a] + \
cc[Z80_TABLE_op][0xb3] + \
cc[Z80_TABLE_op][0xc2] + \
@@ -3573,6 +3577,7 @@ if( _HL > 1 && _PCD < 0xfffc ) { \
if( op3==0x20 && op4==0xfb ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x2b] + \
cc[Z80_TABLE_op][0x7c] + \
cc[Z80_TABLE_op][0xb5] + \
cc[Z80_TABLE_op][0x20] + \
@@ -3591,6 +3596,7 @@ if( _HL > 1 && _PCD < 0xfffc ) { \
if( (ad1 + 256 * ad2) == (_PCD - 1) ) \
{ \
int cnt = \
cc[Z80_TABLE_op][0x2b] + \
cc[Z80_TABLE_op][0x7c] + \
cc[Z80_TABLE_op][0xb5] + \
cc[Z80_TABLE_op][0xc2] + \
src/cpuexec.c
+69 -16
View File
@@ -142,7 +142,8 @@ struct cpuinfo
UINT64 totalcycles; /* total CPU cycles executed */
double localtime; /* local time, relative to the timer system's global time */
double clockscale; /* current active clock scale factor */
double clockscale; /* current active clock scale factor, set by drivers and CPU cores */
double overclock; /* user overclock factor (core options), applied on top of clockscale */
int vblankint_countdown; /* number of vblank callbacks left until we interrupt */
int vblankint_multiplier; /* number of vblank callbacks per interrupt */
@@ -188,6 +189,9 @@ static UINT32 saved_cycles[MAX_CPU * 2];
#define EXACT_PER_CPU 7
static INT32 saved_exact[MAX_CPU * EXACT_PER_CPU];
static INT32 saved_exact_globals[3];
/* the triggers of cpu_spinuntil_time() and cpu_yielduntil_time(): numbered in
turn, the number is in the state (the CPU waits on it, a timer pulls it) */
static INT32 spin_timetrig, yield_timetrig;
static int vblank;
static int current_frame;
static int vblank_countdown;
@@ -340,9 +344,10 @@ int cpu_init(void)
memset(&cpu[cpunum], 0, sizeof(cpu[cpunum]));
cpu[cpunum].suspend = SUSPEND_REASON_RESET;
cpu[cpunum].clockscale = cputype_get_interface(cputype)->overclock;
cpu[cpunum].overclock = 1.0;
/* compute the cycle times */
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * Machine->drv->cpu[cpunum].cpu_clock;
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * cpu[cpunum].overclock * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
/* initialize this CPU */
@@ -361,6 +366,9 @@ int cpu_init(void)
state_save_register_UINT32("cpu", 0, "totalcycles", saved_cycles, cpu_gettotalcpu() * 2);
state_save_register_INT32("cpu", 0, "exact", saved_exact, cpu_gettotalcpu() * EXACT_PER_CPU);
state_save_register_INT32("cpu", 0, "exact globals", saved_exact_globals, 3);
spin_timetrig = yield_timetrig = 0;
state_save_register_INT32("cpu", 0, "spin timetrig", &spin_timetrig, 1);
state_save_register_INT32("cpu", 0, "yield timetrig", &yield_timetrig, 1);
state_save_register_func_presave(cpu_suspend_presave);
state_save_register_func_postload(cpu_suspend_postload);
@@ -934,6 +942,24 @@ double cpunum_get_clockscale(int cpunum)
/*************************************
*
* Recomputes a CPU's cycle times from
* its clock, clock scale and overclock
*
*************************************/
static void update_cycle_rate(int cpunum)
{
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * cpu[cpunum].overclock * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
/* re-compute the perfect interleave factor */
compute_perfect_interleave();
}
/*************************************
*
* Sets the current scaling factor
@@ -946,11 +972,42 @@ void cpunum_set_clockscale(int cpunum, double clockscale)
VERIFY_CPUNUM_VOID(cpunum_set_clockscale);
cpu[cpunum].clockscale = clockscale;
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
update_cycle_rate(cpunum);
}
/* re-compute the perfect interleave factor */
compute_perfect_interleave();
/*************************************
*
* Returns the user overclock factor
* for a CPU's clock speed
*
*************************************/
double cpunum_get_overclock(int cpunum)
{
VERIFY_CPUNUM(1.0, cpunum_get_overclock);
return cpu[cpunum].overclock;
}
/*************************************
*
* Sets the user overclock factor for
* a CPU's clock speed. It multiplies
* the clock scale, so a clock scale
* that a driver or CPU core sets is
* kept
*
*************************************/
void cpunum_set_overclock(int cpunum, double overclock)
{
VERIFY_CPUNUM_VOID(cpunum_set_overclock);
cpu[cpunum].overclock = overclock;
update_cycle_rate(cpunum);
}
@@ -1419,21 +1476,17 @@ void cpu_yield(void)
void cpu_spinuntil_time(double duration)
{
static int timetrig = 0;
cpu_spinuntil_trigger(TRIGGER_SUSPENDTIME + timetrig);
cpu_triggertime(duration, TRIGGER_SUSPENDTIME + timetrig);
timetrig = (timetrig + 1) & 255;
cpu_spinuntil_trigger(TRIGGER_SUSPENDTIME + spin_timetrig);
cpu_triggertime(duration, TRIGGER_SUSPENDTIME + spin_timetrig);
spin_timetrig = (spin_timetrig + 1) & 255;
}
void cpu_yielduntil_time(double duration)
{
static int timetrig = 0;
cpu_yielduntil_trigger(TRIGGER_YIELDTIME + timetrig);
cpu_triggertime(duration, TRIGGER_YIELDTIME + timetrig);
timetrig = (timetrig + 1) & 255;
cpu_yielduntil_trigger(TRIGGER_YIELDTIME + yield_timetrig);
cpu_triggertime(duration, TRIGGER_YIELDTIME + yield_timetrig);
yield_timetrig = (yield_timetrig + 1) & 255;
}
src/cpuexec.h
+8 -2
View File
@@ -179,6 +179,12 @@ double cpunum_get_clockscale(int cpunum);
/* Sets the current scaling factor for a CPU's clock speed */
void cpunum_set_clockscale(int cpunum, double clockscale);
/* Returns the user overclock factor for a CPU's clock speed */
double cpunum_get_overclock(int cpunum);
/* Sets the user overclock factor, which multiplies the clock scale */
void cpunum_set_overclock(int cpunum, double overclock);
/* Temporarily boosts the interleave factor */
void cpu_boost_interleave(double timeslice_time, double boost_duration);
@@ -186,8 +192,8 @@ void cpu_boost_interleave(double timeslice_time, double boost_duration);
#define timer_suspendcpu(cpunum, suspend, reason) do { if (suspend) cpunum_suspend(cpunum, reason, 1); else cpunum_resume(cpunum, reason); } while (0)
#define timer_holdcpu(cpunum, suspend, reason) do { if (suspend) cpunum_suspend(cpunum, reason, 0); else cpunum_resume(cpunum, reason); } while (0)
#define cpu_getstatus(cpunum) (!cpunum_is_suspended(cpunum, SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE))
#define timer_get_overclock(cpunum) cpunum_get_clockscale(cpunum)
#define timer_set_overclock(cpunum, overclock) cpunum_set_clockscale(cpunum, overclock)
#define timer_get_overclock(cpunum) cpunum_get_overclock(cpunum)
#define timer_set_overclock(cpunum, overclock) cpunum_set_overclock(cpunum, overclock)
src/cpuintrf.c
+16
View File
@@ -124,6 +124,9 @@
#if (HAS_TMS32025)
#include "cpu/tms32025/tms32025.h"
#endif
#if (HAS_NAMCOC71)
#include "cpu/namcoc71/c71.h"
#endif
#if (HAS_I960)
#include "cpu/i960/i960.h"
#endif
@@ -573,6 +576,10 @@ const struct cpu_interface cpuintrf[] =
#if (HAS_TMS32025)
CPU3(TMS32025,tms32025, 3, 0,1.00,16,18bew, -1,18,BE,2, 4 ),
#endif
#if (HAS_NAMCOC71)
#define c71_ICount c71_icount
CPU0(NAMCOC71, c71, 6, 0,1.00,16,16bew, -1,16,BE,2, 4 ),
#endif
#if (HAS_TMS32031)
#define tms32031_ICount tms32031_icount
CPU0(TMS32031,tms32031, 4, 0,1.00,32,26ledw,-2,26,LE,4, 4 ),
@@ -1286,6 +1293,15 @@ void *cpunum_get_context_ptr(int cpunum)
return (cpu_active_context[cpu[cpunum].family] == cpunum) ? NULL : cpu[cpunum].context;
}
/* the context buffer of a CPU, also from its init function (when the CPU
does not count in totalcpu yet), whether it is active or not */
void *cpunum_get_context_buffer(int cpunum)
{
if (cpunum < 0 || cpunum >= MAX_CPU)
return NULL;
return cpu[cpunum].context;
}
/*--------------------------
Get/set cycle table
src/cpuintrf.h
+4
View File
@@ -235,6 +235,9 @@ enum
#if (HAS_TMS32025)
CPU_TMS32025,
#endif
#if (HAS_NAMCOC71)
CPU_NAMCOC71,
#endif
#if (HAS_TMS32031)
CPU_TMS32031,
#endif
@@ -636,6 +639,7 @@ void cpunum_write_bytes(int cpunum, offs_t address, const UINT8 *data, UINT32 co
/* return a pointer to the saved context of a given CPU, or NULL if the
context is active (and contained within the CPU core */
void *cpunum_get_context_ptr(int cpunum);
void *cpunum_get_context_buffer(int cpunum);
/* return a pointer to the active cycle count table for a given CPU */
const void *cpunum_get_cycle_table(int cpunum, int which);
src/drawgfx.c
+11 -1
View File
@@ -1,6 +1,7 @@
#ifndef DECLARE
#include "driver.h"
#include "state.h"
#ifdef MSB_FIRST
@@ -3516,11 +3517,20 @@ static INLINE void plotclip(struct mame_bitmap *bitmap,int x,int y,int pen,const
plot_pixel(bitmap,x,y,pen);
}
/* where each crosshair was and since which frame: in the save states, so a
crosshair hides at the same frame after a load or a run-ahead rewind */
static INT32 inactive_xy [MAX_PLAYER_COUNT][3];
void crosshair_state_save_register(void)
{
memset(inactive_xy, 0, sizeof(inactive_xy));
state_save_register_INT32("crosshair", 0, "inactive", &inactive_xy[0][0], MAX_PLAYER_COUNT * 3);
}
void draw_crosshair(int player_number, struct mame_bitmap *bitmap,int x,int y,const struct rectangle *clip)
{
unsigned long color,black,white;
int i;
static int inactive_xy [MAX_PLAYER_COUNT][3];
if (!options.crosshair_enable)
{
src/drawgfx.h
+1
View File
@@ -272,6 +272,7 @@ void mdrawgfxzoom( struct mame_bitmap *dest_bmp,const struct GfxElement *gfx,
void drawgfx_toggle_crosshair(void);
void draw_crosshair(int player_number, struct mame_bitmap *bitmap,int x,int y,const struct rectangle *clip);
void crosshair_state_save_register(void);
static INLINE void sect_rect(struct rectangle *dst, const struct rectangle *src)
{
src/driver.c
+241 -71
View File
@@ -250,9 +250,13 @@ const struct GameDriver *test_drivers[] =
DRIVER( froggers ) /* bootleg */
DRIVER( amidars ) /* GX337 (c) 1982 Konami */
DRIVER( triplep ) /* (c) 1982 KKI */ /* made by Sanritsu? */
DRIVER( triplepa ) /* (c) 1982 KKI */
DRIVER( knockout ) /* (c) 1982 KKK */
DRIVER( knockoutb ) /* bootleg */
DRIVER( knockoutc ) /* bootleg (ESG) */
DRIVER( mariner ) /* (c) 1981 Amenip */
DRIVER( 800fath ) /* (c) 1981 Amenip + U.S. Billiards license */
DRIVER( 800fatha ) /* (c) 1981 Amenip + U.S. Billiards license */
DRIVER( mars ) /* (c) 1981 Artic */
DRIVER( devilfsh ) /* (c) 1982 Artic */
DRIVER( newsin7 ) /* (c) 1983 ATW USA, Inc. */
@@ -371,6 +375,8 @@ const struct GameDriver *test_drivers[] =
DRIVER( kodure ) /* (c) 1987 (Japan) */
DRIVER( armedf ) /* (c) 1988 */
DRIVER( cclimbr2 ) /* (c) 1988 (Japan) */
DRIVER( skyrobo ) /* (c) 1989 */
DRIVER( bigfghtr ) /* (c) 1989 */
/* Nichibutsu Mahjong games */
DRIVER( hyhoo ) /* (c) 1987 */
@@ -742,18 +748,49 @@ const struct GameDriver *test_drivers[] =
DRIVER( cybsled ) /* (c) 1993 */
/* Namco System 22 games */
DRIVER( namcoc74 ) /* C74 BIOS */
DRIVER( ridgerac ) /* (c) 1993 */
DRIVER( ridgeraca ) /* (c) 1993 */
DRIVER( ridgeracb ) /* (c) 1993 */
DRIVER( ridgeracc ) /* (c) 1993 */
DRIVER( ridgeracj ) /* (c) 1993 */
DRIVER( ridgera2 ) /* (c) 1994 */
DRIVER( ridgera2j ) /* (c) 1994 */
DRIVER( ridgera2ja ) /* (c) 1994 */
DRIVER( ridgera28 ) /* (c) 1994 */
DRIVER( cybrcomm ) /* (c) 1994 */
DRIVER( raverace ) /* (c) 1995 */
DRIVER( raveracej ) /* (c) 1995 */
DRIVER( raveraceja ) /* (c) 1995 */
DRIVER( acedrive ) /* (c) 1994 */
DRIVER( victlap ) /* (c) 1996 */
DRIVER( victlapa ) /* (c) 1996 */
DRIVER( victlapj ) /* (c) 1996 */
/* Namco Super System 22 games */
DRIVER( alpinerd ) /* (c) 1994 */
DRIVER( alpinerc ) /* (c) 1994 */
DRIVER( raveracw ) /* (c) 1995 */
DRIVER( ridgeraj )
DRIVER( ridger2j )
DRIVER( acedrvrw )
DRIVER( victlapw )
DRIVER( cybrcomm )
DRIVER( airco22b )
DRIVER( cybrcycc )
DRIVER( timecrsa )
DRIVER( alpinerjc ) /* (c) 1994 */
DRIVER( airco22b ) /* (c) 1995 */
DRIVER( cybrcycc ) /* (c) 1995 */
DRIVER( cybrcyccj ) /* (c) 1995 */
DRIVER( dirtdash ) /* (c) 1995 */
DRIVER( dirtdasha ) /* (c) 1995 */
DRIVER( dirtdashb ) /* (c) 1995 */
DRIVER( dirtdashj ) /* (c) 1995 */
DRIVER( timecris ) /* (c) 1996 */
DRIVER( timecrisa ) /* (c) 1996 */
DRIVER( timecrisj ) /* (c) 1996 */
DRIVER( propcycl ) /* (c) 1996 */
DRIVER( propcyclj ) /* (c) 1996 */
DRIVER( alpines ) /* (c) 1996 */
DRIVER( tokyowar ) /* (c) 1996 */
DRIVER( tokyowarj ) /* (c) 1996 */
DRIVER( aquajet ) /* (c) 1996 */
DRIVER( alpinr2b ) /* (c) 1996 */
DRIVER( alpinr2a ) /* (c) 1996 */
DRIVER( adillor ) /* (c) 1997 */
DRIVER( adillorj ) /* (c) 1997 */
/* Universal games */
@@ -2023,6 +2060,8 @@ V-V TP-027
DRIVER( ddpdfk ) /* DoDonPachi Dai-Fukkatsu Ver 1.5 (Japan, 2008/06/23 MASTER VER 1.5) */
DRIVER( ddpdfk10 ) /* DoDonPachi Dai-Fukkatsu Ver 1.0 (Japan, 2008/05/16 MASTER VER) */
DRIVER( dfkbl ) /* DoDonPachi Dai-Fukkatsu Black Label (Japan, 2010/1/18 BLACK LABEL) */
DRIVER( akatana ) /* Akai Katana (2010/ 8/13 MASTER VER.) */
DRIVER( ddpsdoj ) /* DoDonPachi SaiDaiOuJou (2012/ 4/20) */
/* Kyugo games */
/* Kyugo only made four games: Repulse, Flash Gal, SRD Mission and Air Wolf. */
@@ -2123,6 +2162,24 @@ V-V TP-027
DRIVER( gngmaidencenh ) /* Hack */
DRIVER( gngmaident ) /* Hack */
DRIVER( gngmaidentenh ) /* Hack */
DRIVER( gngprincess ) /* Hack */
DRIVER( gngprincessa ) /* Hack */
DRIVER( gngprincessaenh ) /* Hack */
DRIVER( gngprincessb ) /* Hack */
DRIVER( gngprincessbenh ) /* Hack */
DRIVER( gngprincessc ) /* Hack */
DRIVER( gngprincesscenh ) /* Hack */
DRIVER( gngprincessenh ) /* Hack */
DRIVER( gngprincesst ) /* Hack */
DRIVER( gngprincesstenh ) /* Hack */
DRIVER( makprincess ) /* Hack */
DRIVER( makprincessb ) /* Hack */
DRIVER( makprincessbenh ) /* Hack */
DRIVER( makprincessc ) /* Hack */
DRIVER( makprincesscenh ) /* Hack */
DRIVER( makprincessenh ) /* Hack */
DRIVER( makprincessg ) /* Hack */
DRIVER( makprincessgenh ) /* Hack */
DRIVER( gngknight ) /* Hack */
DRIVER( gngknightenh ) /* Hack */
DRIVER( gngknighta ) /* Hack */
@@ -3295,14 +3352,11 @@ DokiDoki Penguin Land *not confirmed
DRIVER( aliensya ) /* (c) 1987 (protected) */
DRIVER( aliensyb ) /* (c) 1987 (protected) */
DRIVER( aliensyj ) /* (c) 1987 (protected. Japan) */
DRIVER( astorm ) /* (c) 1990 (protected) */
DRIVER( astorm2p ) /* (c) 1990 (protected 2 Players) */
DRIVER( aurail1 ) /* (c) 1990 Sega / Westone (protected) */
DRIVER( aurailj ) /* (c) 1990 Sega / Westone (protected) */
DRIVER( bayrouta ) /* (c) 1989 (protected) */
DRIVER( bayrtbl1 ) /* (c) 1989 (protected) (bootleg) */
DRIVER( bayrtbl2 ) /* (c) 1989 (protected) (bootleg) */
DRIVER( enduror ) /* (c) 1985 (protected) */
DRIVER( eswat ) /* (c) 1989 (protected) */
DRIVER( fpoint ) /* (c) 1989 (protected) */
DRIVER( goldnaxb ) /* (c) 1989 (protected) */
@@ -3311,7 +3365,6 @@ DokiDoki Penguin Land *not confirmed
DRIVER( jyuohki ) /* (c) 1988 (protected. Altered Beast Japan) */
DRIVER( passsht ) /* (protected) */
DRIVER( sdioj ) /* (c) 1987 (protected. Japan) */
DRIVER( shangon ) /* (c) 1992 (protected) */
DRIVER( shinobia ) /* (c) 1987 (protected) */
DRIVER( shinobib ) /* (c) 1987 (protected) */
DRIVER( tetris ) /* (c) 1988 (protected) */
@@ -3322,11 +3375,6 @@ DokiDoki Penguin Land *not confirmed
DRIVER( hamaway )
DRIVER( aceattac ) /* (protected) */
DRIVER( afighter ) /* (protected) */
DRIVER( bloxeed ) /* (protected) */
DRIVER( cltchitr ) /* (protected) */
DRIVER( cotton ) /* (protected) */
DRIVER( cottona ) /* (protected) */
DRIVER( ddcrew ) /* (protected) */
DRIVER( dunkshot ) /* (protected) */
DRIVER( dunkshota ) /* (protected) */
DRIVER( dunkshoto ) /* (protected) */
@@ -3334,7 +3382,6 @@ DokiDoki Penguin Land *not confirmed
DRIVER( sdib ) /* (protected) */
DRIVER( sjryuko ) /* (protected) */
DRIVER( exctleag ) /* (protected) */
DRIVER( lghost ) /* (protected) */
DRIVER( loffire ) /* (protected) */
DRIVER( mvp ) /* (protected) */
DRIVER( ryukyu ) /* (protected) */
@@ -3359,13 +3406,26 @@ DokiDoki Penguin Land *not confirmed
DRIVER( aurail1d ) /* (c) 1990 Sega / Westone */
DRIVER( aurailjd ) /* (c) 1990 Sega / Westone */
DRIVER( bayroute ) /* (c) 1989 Sunsoft / Sega */
DRIVER( cottond )
DRIVER( cotton ) /* (c) 1991 (FD1094 317-0181a) */
DRIVER( cottonu ) /* (c) 1991 (FD1094 317-0180) */
DRIVER( cottonj ) /* (c) 1991 (FD1094 317-0179b) */
DRIVER( cottonja ) /* (c) 1991 (FD1094 317-0179a) */
DRIVER( cottond ) /* bootleg (decrypted cotton) */
DRIVER( cottonud ) /* bootleg (decrypted cottonu) */
DRIVER( cottonjd ) /* bootleg (decrypted cottonj) */
DRIVER( cottonjad ) /* bootleg (decrypted cottonja) */
DRIVER( bulletd )
DRIVER( bodyslam ) /* (c) 1986 */
DRIVER( dduxbl ) /* (c) 1989 (Datsu bootleg) */
DRIVER( dumpmtmt ) /* (c) 1986 (Japan) */
DRIVER( endurob2 ) /* (c) 1985 (Beta bootleg) */
DRIVER( endurobl ) /* (c) 1985 (Herb bootleg) */
DRIVER( enduror ) /* (c) 1986 (FD1089B) */
DRIVER( endurora ) /* (c) 1986 (FD1089B) */
DRIVER( endurorb ) /* (c) 1986 (FD1089B) */
DRIVER( enduror1 ) /* (c) 1986 (FD1089B) */
DRIVER( endurobl ) /* (c) 1986 (Herb bootleg) */
DRIVER( endurob2 ) /* (c) 1986 (Beta bootleg) */
DRIVER( endurord ) /* (c) 1986 (bootleg) */
DRIVER( enduror1d ) /* (c) 1986 (bootleg) */
DRIVER( eswatbl ) /* (c) 1989 (but bootleg) */
DRIVER( fantzone ) /* (c) 1986 */
DRIVER( fantzono ) /* (c) 1986 */
@@ -3377,6 +3437,46 @@ DokiDoki Penguin Land *not confirmed
DRIVER( hangon ) /* (c) 1985 */
DRIVER( hwchamp ) /* (c) 1987 */
DRIVER( mjleague ) /* (c) 1985 */
DRIVER( astorm ) /* (c) 1990 (FD1094 317-0154) */
DRIVER( astorm3 ) /* (c) 1990 (FD1094 317-0148) */
DRIVER( astormu ) /* (c) 1990 (FD1094 317-0147) */
DRIVER( astormj ) /* (c) 1990 (FD1094 317-0146) */
DRIVER( astorm3d ) /* bootleg (decrypted astorm3) */
DRIVER( astormud ) /* bootleg (decrypted astormu) */
DRIVER( astormjd ) /* bootleg (decrypted astormj) */
DRIVER( bloxeed ) /* (c) 1989 (FD1094 317-0139) */
DRIVER( bloxeeda ) /* (c) 1989 (FD1094 317-0139) */
DRIVER( bloxeedd ) /* bootleg (decrypted bloxeed) */
DRIVER( cltchitr ) /* (c) 1991 (FD1094 317-0176) */
DRIVER( cltchitrj ) /* (c) 1991 (FD1094 317-0175) */
DRIVER( cltchitrd ) /* bootleg (decrypted cltchitr) */
DRIVER( cltchitrjd ) /* bootleg (decrypted cltchitrj) */
DRIVER( wwallyj ) /* (c) 1992 (FD1094 317-0197B) */
DRIVER( wwallyja ) /* (c) 1992 (FD1094 317-0197A) */
DRIVER( wwallyja3p ) /* (c) 1992 (FD1094 317-0198A) */
DRIVER( wwallyjd ) /* bootleg (decrypted wwallyj) */
DRIVER( wwallyjad ) /* bootleg (decrypted wwallyja) */
DRIVER( ddcrew ) /* (c) 1991 (FD1094 317-0190) */
DRIVER( ddcrewu ) /* (c) 1991 (FD1094 317-0186) */
DRIVER( ddcrew2 ) /* (c) 1991 (FD1094 317-0184) */
DRIVER( ddcrew1 ) /* (c) 1991 (FD1094 317-0187) */
DRIVER( ddcrewj ) /* (c) 1991 (FD1094 317-0185) */
DRIVER( ddcrewj2 ) /* (c) 1991 (FD1094 317-0182) */
DRIVER( ddcrewd ) /* bootleg (decrypted ddcrew) */
DRIVER( ddcrewud ) /* bootleg (decrypted ddcrewu) */
DRIVER( ddcrew2d ) /* bootleg (decrypted ddcrew2) */
DRIVER( ddcrew1d ) /* bootleg (decrypted ddcrew1) */
DRIVER( ddcrewjd ) /* bootleg (decrypted ddcrewj) */
DRIVER( ddcrewj2d ) /* bootleg (decrypted ddcrewj2) */
DRIVER( desertbr ) /* (c) 1992 (FD1094 317-0196) */
DRIVER( desertbrj ) /* (c) 1992 (FD1094 317-0194) */
DRIVER( desertbrd ) /* bootleg (decrypted desertbr) */
DRIVER( desertbrjd ) /* bootleg (decrypted desertbrj) */
DRIVER( lghost ) /* (c) 1990 (FD1094 317-0166) */
DRIVER( lghostu ) /* (c) 1990 (FD1094 317-0165) */
DRIVER( lghostj ) /* (c) 1990 (FD1094 317-0164) */
DRIVER( lghostd ) /* bootleg (decrypted lghost) */
DRIVER( lghostud ) /* bootleg (decrypted lghostu) */
DRIVER( mwalk ) /* (c) 1990 (FD1094/8751 317-0159) */
DRIVER( mwalku ) /* (c) 1990 (FD1094/8751 317-0158) */
DRIVER( mwalkj ) /* (c) 1990 (FD1094/8751 317-0157) */
@@ -3396,12 +3496,19 @@ DokiDoki Penguin Land *not confirmed
DRIVER( rachero ) /* 1989 (decrypted) */
DRIVER( riotcity ) /* (c) 1991 Sega / Westone */
DRIVER( sdi ) /* (c) 1987 */
DRIVER( shangonb ) /* (c) 1992 (but bootleg) */
DRIVER( shangon ) /* (c) 1987 */
DRIVER( shangon1 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon2 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon3 ) /* (c) 1987 (FD1089B) */
DRIVER( shangon3d ) /* (c) 1987 (bootleg) */
DRIVER( shangonle ) /* (c) 1991 */
DRIVER( shangonrb ) /* (c) 1992 (bootleg) */
DRIVER( shangonrb2 ) /* (c) 1987 (Beta bootleg) */
DRIVER( sharrier ) /* (c) 1985 */
DRIVER( shdancbl ) /* (c) 1989 (but bootleg) */
DRIVER( shdancer ) /* (c) 1989 */
DRIVER( shdancrj ) /* (c) 1989 */
DRIVER( shdancrb ) /* (c) 1989 */
DRIVER( shdancerj ) /* (c) 1989 */
DRIVER( shdancer1 ) /* (c) 1989 */
DRIVER( shinobi ) /* (c) 1987 */
DRIVER( shinobl ) /* (c) 1987 (but bootleg) */
DRIVER( smgp ) /* 1989 (decrypted) */
@@ -3493,7 +3600,9 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( bakubaku )
DRIVER( colmns97 )
DRIVER( cotton2 )
DRIVER( cotton2e )
DRIVER( cottonbm )
DRIVER( cottonbme ) /* bootleg (English translation) */
DRIVER( decathlt )
DRIVER( diehard )
DRIVER( dnmtdeka )
@@ -3515,14 +3624,25 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( pblbeach )
DRIVER( prikura )
DRIVER( puyosun )
DRIVER( puyosune ) /* bootleg, English translation */
DRIVER( rsgun )
DRIVER( sandor )
DRIVER( thunt )
DRIVER( sassisu )
DRIVER( sasissu )
DRIVER( sanjeon )
DRIVER( critcrsh )
DRIVER( tatacot )
DRIVER( danchiq )
DRIVER( micrombc )
DRIVER( patocar )
DRIVER( skychal )
DRIVER( supgoal )
DRIVER( techbowl )
DRIVER( wasafari )
DRIVER( seabass )
DRIVER( shanhigw )
DRIVER( shienryu )
DRIVER( sleague )
DRIVER( smleague )
DRIVER( sokyugrt )
DRIVER( sss )
DRIVER( suikoenb )
@@ -3532,6 +3652,8 @@ Sep.1994 Quiz Ghost Hunter
DRIVER( vmahjong )
DRIVER( winterht )
DRIVER( znpwfv )
DRIVER( znpwfvt )
DRIVER( znpwfve )
DRIVER( danchih )
DRIVER( mausuke )
@@ -3561,57 +3683,94 @@ Propose deniam-16c 1997/06/21
BOMULEUL CHAJARA SEGA ST-V 1997/04/11
*/
/* System C games */
DRIVER( bloxeedc ) /* (c) 1989 Sega / Elorg*/
DRIVER( columns ) /* (c) 1990 Sega */
/* System C / C-2 (drivers/segac2.c) */
DRIVER( bloxeedc ) /* (c) 1989 Sega / Elorg */
DRIVER( bloxeedu ) /* (c) 1989 Sega / Elorg */
DRIVER( columns ) /* (c) 1990 Sega */
DRIVER( columnsu ) /* (c) 1990 Sega */
DRIVER( columnsj ) /* (c) 1990 Sega */
DRIVER( columns2 ) /* (c) 1990 Sega */
/* System C-2 games */
DRIVER( ssonicbr ) /* Sega, Unreleased */
DRIVER( borench ) /* (c) 1990 Sega */
DRIVER( tfrceac ) /* (c) 1990 Sega / Technosoft */
DRIVER( tfrceacj ) /* (c) 1990 Sega / Technosoft */
DRIVER( tfrceacb ) /* bootleg */
DRIVER( tfrceacjpb ) /* Prototype Bootleg */
DRIVER( ribbit ) /* (c) 1991 Sega */
DRIVER( column2j ) /* (c) 1990 Sega */
DRIVER( tfrceac ) /* (c) 1990 Technosoft / Sega */
DRIVER( tfrceacj ) /* (c) 1990 Technosoft / Sega */
DRIVER( tfrceacb ) /* (c) 1990 bootleg */
DRIVER( tfrceacjpb ) /* (c) 1990 bootleg */
DRIVER( borench ) /* (c) 1990 Sega */
DRIVER( borencha ) /* (c) 1990 Sega */
DRIVER( borenchj ) /* (c) 1990 Sega */
DRIVER( ribbit ) /* (c) 1991 Sega */
DRIVER( ribbitj ) /* (c) 1991 Sega */
DRIVER( twinsqua ) /* (c) 1991 Sega */
DRIVER( soniccar ) /* (c) 1991 Sega */
DRIVER( ssonicbr ) /* (c) 1992 hack */
DRIVER( ooparts ) /* (c) 1992 hack */
DRIVER( puyo ) /* (c) 1992 Compile / Sega */
DRIVER( puyobl ) /* (c) 1992 bootleg */
DRIVER( puyoj ) /* (c) 1992 Compile / Sega */
DRIVER( puyoja ) /* (c) 1992 Compile / Sega */
DRIVER( tantr ) /* (c) 1992 Sega */
DRIVER( tantrkor ) /* (c) 1993 Sega */
DRIVER( tantrbl ) /* bootleg */
DRIVER( tantrbl2 ) /* bootleg */
DRIVER( puyopuyo ) /* (c) 1992 Sega / Compile */
DRIVER( puyopuya ) /* (c) 1992 Sega / Compile */
DRIVER( puyopuyb ) /* bootleg */
DRIVER( ichir ) /* (c) 1994 Sega */
DRIVER( ichirk ) /* (c) 1994 Sega */
DRIVER( ichirj ) /* (c) 1994 Sega */
DRIVER( ichirjbl ) /* bootleg */
DRIVER( stkclmns ) /* (c) 1994 Sega */
DRIVER( puyopuy2 ) /* (c) 1994 Compile + Sega license */
DRIVER( tantrbl ) /* (c) 1992 bootleg */
DRIVER( tantrbl4 ) /* (c) 1992 bootleg */
DRIVER( tantrbl2 ) /* (c) 1994 bootleg */
DRIVER( tantrbl3 ) /* (c) 1994 bootleg */
DRIVER( wwanpanm ) /* (c) 1992 Sega */
DRIVER( wwanpanmo ) /* (c) 1992 Sega */
DRIVER( wwjumbo ) /* (c) 1990 Sega */
DRIVER( wwmarine ) /* (c) 1992 Sega */
DRIVER( wwpajero ) /* (c) 1990 Sega */
DRIVER( anpanman ) /* (c) 1992 Sega */
DRIVER( anpanmana ) /* (c) 1992 Sega */
DRIVER( sonicpop ) /* (c) 1993 Sega */
DRIVER( sonicfgt ) /* (c) 1993 Sega */
DRIVER( sonicfgtj ) /* (c) 1993 Sega */
DRIVER( potopoto ) /* (c) 1994 Sega */
DRIVER( zunkyou ) /* (c) 1994 Sega */
DRIVER( headonch ) /* Sega Unreleased */
DRIVER( ooparts ) /* Sega Unreleased */
DRIVER( stkclmns ) /* (c) 1994 Sega */
DRIVER( stkclmnsj ) /* (c) 1994 Sega */
DRIVER( ichir ) /* (c) 1994 Sega */
DRIVER( ichirbl ) /* (c) 1994 bootleg */
DRIVER( ichirk ) /* (c) 1994 Sega */
DRIVER( ichirj ) /* (c) 1994 Sega */
DRIVER( ichirjbl ) /* (c) 1994 bootleg */
DRIVER( puyopuy2 ) /* (c) 1994 Compile (Sega license) */
DRIVER( zunkyou ) /* (c) 1994 Sega */
DRIVER( headonch ) /* (c) 1994 hack */
DRIVER( pclubj ) /* (c) 1995 Atlus */
DRIVER( pclubjv2 ) /* (c) 1995 Atlus */
DRIVER( pclub ) /* (c) 1995 Atlus */
DRIVER( pclubjv3 ) /* (c) 1995 Atlus */
DRIVER( pclubjv4 ) /* (c) 1996 Atlus */
DRIVER( pclubjv5 ) /* (c) 1996 Atlus */
/* Atlus Print Club 'Games' C-2 board */
DRIVER( pclubj )
DRIVER( pclubjv2 )
DRIVER( pclubjv4 )
DRIVER( pclubjv5 )
/* Genie Hardware (uses Genesis VDP) also has 'Sun Mixing Co' put into tile ram */
DRIVER( puckpkmn ) /* (c) 2000 Genie */
/* Genie / Y-BOX hardware (drivers/megadriv_ybox.c) */
DRIVER( puckpkmn ) /* (c) 2000 Sun Mixing */
DRIVER( jingling ) /* (c) 2000 IBS Co. Ltd */
DRIVER( puckpkmnb ) /* bootleg */
DRIVER( jzth ) /* (c) 2000 <unknown> */
DRIVER( songjang ) /* (c) 2000 WAH LAB */
DRIVER( shuifeng ) /* (c) 1999 WAH LAB */
DRIVER( songjang ) /* (c) 2000 WAH LAP */
DRIVER( shuifeng ) /* (c) 1999 WAH LAP */
/* Sun Mixing Mega Drive based boards (drivers/megadriv_sunmix.c) */
DRIVER( topshoot ) /* (c) 1995 Sun Mixing */
DRIVER( sbubsm ) /* (c) 1996 Sun Mixing */
DRIVER( barek3mb ) /* (c) 1994 bootleg / Sega */
DRIVER( aladmdb ) /* (c) 1993 bootleg / Sega */
DRIVER( barek2ch ) /* (c) 1994 bootleg / Sega */
DRIVER( sonic2mb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic3mb ) /* (c) 1993 bootleg / Sega */
DRIVER( jparkmb ) /* (c) 1993 bootleg / Sega */
DRIVER( twinktmb ) /* (c) 1993 bootleg / Sega */
/* Mega Drive based bootlegs (drivers/megadriv_acbl.c) */
DRIVER( aladmdb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic2mb ) /* (c) 1993 bootleg / Sega */
DRIVER( sonic3mb ) /* (c) 1993 bootleg / Sega */
DRIVER( barek2mb ) /* (c) 1994 bootleg / Sega */
DRIVER( barek3mba ) /* (c) 1994 bootleg / Sega */
DRIVER( twinktmb ) /* (c) 1993 bootleg / Sega */
DRIVER( jparkmb ) /* (c) 1993 bootleg / Sega */
DRIVER( barekch ) /* (c) 1994 bootleg */
DRIVER( bk3ssrmb ) /* (c) 1994 bootleg / Sega */
DRIVER( srssf2mb ) /* (c) 1994 bootleg / Sega */
DRIVER( biohzdmb ) /* (c) 1995 bootleg / Sega */
DRIVER( mk3mdb ) /* (c) 1996 bootleg / Midway */
DRIVER( ssf2mdb ) /* (c) 1994 bootleg / Capcom */
DRIVER( srmdb ) /* (c) 1993 bootleg / Konami */
DRIVER( barek3mb ) /* (c) 1994 bootleg / Sega */
DRIVER( barek2ch ) /* (c) 1994 bootleg */
/* Sega MegaTech, the number shown ia on the label of the instruction rom */
DRIVER( mt_beast ) /* 01 */
@@ -3678,9 +3837,10 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
/* Sega MegaPlay */
DRIVER( mp_sonic ) /* 01 */
DRIVER( mp_gaxe2 ) /* 02 */
DRIVER( mp_gaxe2a ) /* 02 */
DRIVER( mp_gslam ) /* 03 */
DRIVER( mp_sor2 ) /* 03 */
DRIVER( mp_twc ) /* 04 */
DRIVER( mp_twcup ) /* 04 */
DRIVER( mp_soni2 ) /* 05 */
DRIVER( mp_bio ) /* 06 */
DRIVER( mp_shnb3 ) /* 07 */
@@ -4521,6 +4681,7 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
DRIVER( foodf ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( foodf2 ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( foodfc ) /* 136020 (c) 1982 */ /* made by Gencomp */
DRIVER( akkaarrh )
DRIVER( ccastles ) /* 136022 (c) 1983 */
DRIVER( ccastle3 ) /* 136022 (c) 1983 */
DRIVER( ccastle2 ) /* 136022 (c) 1983 */
@@ -5548,6 +5709,7 @@ BOMULEUL CHAJARA SEGA ST-V 1997/04/11
DRIVER( fromancr ) /* (c) 1995 Video System Co. (Japan) */
DRIVER( fromanc4 ) /* (c) 1998 Video System Co. (Japan) */
DRIVER( inufuku ) /* (c) 1998 Video System Co. (Japan) */
DRIVER( 3on3dunk ) /* (c) 1996 Video System Co. ( US ) */
/* Psikyo games */
DRIVER( samuraia ) /* (c) 1993 (World) */
@@ -6779,4 +6941,12 @@ Other Sun games
DRIVER( roundup5 )
DRIVER( bigfight )
DRIVER( cyclwarr )
/* Tatsumi TX-1 / Buggy Boy */
DRIVER( tx1 ) /* (c) 1983 Tatsumi (Atari/Namco/Taito license) */
DRIVER( tx1jb ) /* (c) 1983 Tatsumi */
DRIVER( tx1jc ) /* (c) 1983 Tatsumi */
DRIVER( buggyboy ) /* (c) 1985 Tatsumi */
DRIVER( buggyboyb ) /* (c) 1986 Tatsumi */
DRIVER( buggyboyjr ) /* (c) 1986 Tatsumi */
#endif /* DRIVER_RECURSIVE */
src/drivers/8080bw_drivers.c
+9
View File
@@ -2241,6 +2241,15 @@ INPUT_PORTS_START( polaris )
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
PORT_START /* 4, read by POLARIS_ADJ_VR1 */
PORT_ADJUSTER( 80, "Sub Volume VR1" )
PORT_START /* 5, read by POLARIS_ADJ_VR2 */
PORT_ADJUSTER( 70, "Sub Volume VR2" )
PORT_START /* 6, read by POLARIS_ADJ_VR3 */
PORT_ADJUSTER( 90, "Sub Volume VR3" )
INPUT_PORTS_END
static MACHINE_DRIVER_START( polaris )
src/drivers/akkaarrh.c
+307
View File
@@ -0,0 +1,307 @@
// license:BSD-3-Clause
// copyright-holders:Aaron Giles
/*
Atari Akka Arrh hardware
*/
#include "driver.h"
#include "cpu/m6502/m6502.h"
#include "sound/pokey.h"
static UINT8 *akkaarrh_videoram;
static UINT8 *akkaarrh_spriteram;
static struct tilemap *akkaarrh_tilemap[4];
static UINT8 video_mirror;
static UINT8 earom[64];
static UINT8 earom_address, earom_data, earom_control;
static void get_tile_info(int tile_index)
{
int attr = akkaarrh_videoram[tile_index + 0x400];
SET_TILE_INFO(0, akkaarrh_videoram[tile_index], attr & 15, TILE_FLIPYX(attr >> 6))
}
static VIDEO_START( akkaarrh )
{
int i;
for (i = 0; i < 4; ++i)
{
akkaarrh_tilemap[i] = tilemap_create(get_tile_info, tilemap_scan_rows, TILEMAP_OPAQUE, 8, 8, 32, 30);
if (!akkaarrh_tilemap[i])
return 1;
tilemap_set_flip(akkaarrh_tilemap[i], ((i & 1) ? TILEMAP_FLIPX : 0) | ((i & 2) ? TILEMAP_FLIPY : 0));
}
return 0;
}
static VIDEO_UPDATE( akkaarrh )
{
int i;
if (!(video_mirror & 1))
tilemap_draw(bitmap, cliprect, akkaarrh_tilemap[0], 0, 0);
else
{
/* Zoom uses reflected copies of the upper-left quadrant. */
for (i = 0; i < 4; ++i)
{
struct rectangle clip = *cliprect;
int left = (i & 1) * 128;
int top = (i >> 1) * 120;
if (clip.min_x < left) clip.min_x = left;
if (clip.max_x > left + 127) clip.max_x = left + 127;
if (clip.min_y < top) clip.min_y = top;
if (clip.max_y > top + 119) clip.max_y = top + 119;
if (clip.min_x <= clip.max_x && clip.min_y <= clip.max_y)
tilemap_draw(bitmap, &clip, akkaarrh_tilemap[i], 0, 0);
}
}
for (i = 0; i < 0x100; i += 4)
drawgfx(bitmap, Machine->gfx[1], akkaarrh_spriteram[i + 1], akkaarrh_spriteram[i] & 15,
0, 0, akkaarrh_spriteram[i + 3], 240 - akkaarrh_spriteram[i + 2], cliprect, TRANSPARENCY_PEN, 0);
}
static WRITE_HANDLER( akkaarrh_videoram_w )
{
int i;
akkaarrh_videoram[offset] = data;
for (i = 0; i < 4; ++i)
tilemap_mark_tile_dirty(akkaarrh_tilemap[i], offset & 0x3ff);
}
static WRITE_HANDLER( akkaarrh_palette_w )
{
paletteram[offset] = data;
palette_set_color(offset, pal3bit(data >> 5), pal2bit(data >> 3), pal3bit(data));
}
static WRITE_HANDLER( akkaarrh_irq_ack_w )
{
cpu_set_irq_line(0, M6502_IRQ_LINE, CLEAR_LINE);
}
static WRITE_HANDLER( akkaarrh_mirror_w )
{
video_mirror = data;
}
static WRITE_HANDLER( akkaarrh_output_w )
{
int i;
if (!offset)
{
set_led_status(0, !(data & 8));
set_led_status(1, !(data & 4));
coin_counter_w(0, data & 1);
coin_counter_w(1, data & 2);
}
else
for (i = 0; i < 8; ++i)
set_led_status(2 + (offset - 1) * 8 + i, (data >> i) & 1);
}
static READ_HANDLER( akkaarrh_earom_r )
{
return earom_data;
}
static WRITE_HANDLER( akkaarrh_earom_w )
{
earom_address = offset & 63;
earom_data = data;
}
static void earom_update(void)
{
if (!(earom_control & 2))
{
/* Programming only clears bits; an erase cycle must precede it. */
if (earom_control & 4)
earom[earom_address] = 0xff;
else
earom[earom_address] &= earom_data;
}
}
static WRITE_HANDLER( akkaarrh_earom_control_w )
{
UINT8 old = earom_control;
earom_control = (old & 1) | ((data & 4) ? 0 : 2) | ((data & 2) ? 4 : 0) | (data & 8);
if ((earom_control & 8) && earom_control != old)
earom_update();
old = earom_control;
earom_control = (earom_control & ~1) | (data & 1);
/* Reads latch on the falling clock edge while chip select is active. */
if ((earom_control & 8) && (old & 1) && !(data & 1))
{
if (earom_control & 2)
earom_data = earom[earom_address];
earom_update();
}
}
static NVRAM_HANDLER( akkaarrh )
{
if (read_or_write)
mame_fwrite(file, earom, sizeof(earom));
else if (file)
mame_fread(file, earom, sizeof(earom));
else
memset(earom, 0xff, sizeof(earom));
}
static MEMORY_READ_START( akkaarrh_readmem )
{ 0x0000, 0x07ff, MRA_RAM },
{ 0x1000, 0x10ff, MRA_RAM },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x3000, 0x30ff, MRA_RAM },
{ 0x7010, 0x701f, pokey1_r },
{ 0x7020, 0x702f, pokey2_r },
{ 0x7040, 0x707f, MRA_NOP },
{ 0x7080, 0x7080, input_port_0_r },
{ 0x7081, 0x7081, input_port_1_r },
{ 0x7082, 0x7082, input_port_2_r },
{ 0x7083, 0x7083, input_port_3_r },
{ 0x7087, 0x7087, akkaarrh_earom_r },
{ 0x8000, 0xffff, MRA_ROM },
MEMORY_END
static MEMORY_WRITE_START( akkaarrh_writemem )
{ 0x0000, 0x07ff, MWA_RAM },
{ 0x1000, 0x10ff, MWA_RAM, &akkaarrh_spriteram },
{ 0x2000, 0x27ff, akkaarrh_videoram_w, &akkaarrh_videoram },
{ 0x3000, 0x30ff, akkaarrh_palette_w, &paletteram },
{ 0x4000, 0x4000, akkaarrh_irq_ack_w },
{ 0x5000, 0x5000, watchdog_reset_w },
{ 0x6000, 0x6000, akkaarrh_mirror_w },
{ 0x7010, 0x701f, pokey1_w },
{ 0x7020, 0x702f, pokey2_w },
{ 0x7040, 0x707f, akkaarrh_earom_w },
{ 0x70c0, 0x70c3, akkaarrh_output_w },
{ 0x70c7, 0x70c7, akkaarrh_earom_control_w },
{ 0x8000, 0xffff, MWA_ROM },
MEMORY_END
INPUT_PORTS_START( akkaarrh )
PORT_START
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) //Zoom
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) //Fire
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) //Power blaster
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_ANALOG( 0x0f, 0x00, IPT_TRACKBALL_X | IPF_REVERSE, 30, 20, 0, 0)
PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_ANALOG( 0x0f, 0x00, IPT_TRACKBALL_Y, 30, 20, 0, 0)
PORT_BIT( 0x30, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_VBLANK )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
static struct GfxLayout tile_layout =
{
8, 8, RGN_FRAC(1,4), 4,
{ RGN_FRAC(3,4), RGN_FRAC(2,4), RGN_FRAC(1,4), RGN_FRAC(0,4) },
{ 0,1,2,3,4,5,6,7 },
{ 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 },
8*8
};
static struct GfxLayout sprite_layout =
{
16, 16, RGN_FRAC(1,4), 4,
{ RGN_FRAC(3,4), RGN_FRAC(2,4), RGN_FRAC(1,4), RGN_FRAC(0,4) },
{ 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
{ 0*16,1*16,2*16,3*16,4*16,5*16,6*16,7*16,8*16,9*16,10*16,11*16,12*16,13*16,14*16,15*16 },
16*16
};
static struct GfxDecodeInfo gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tile_layout, 0, 16 },
{ REGION_GFX2, 0, &sprite_layout, 0, 16 },
{ -1 }
};
static struct POKEYinterface pokey_interface =
{
2, /* 2 chips */
1250000, /* 125 MHz */
{ 50, 50 },
/* The 8 pot handlers */
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
/* The allpot handler */
{ 0, 0 },
};
static MACHINE_DRIVER_START( akkaarrh )
MDRV_CPU_ADD(M6502, 12096000/8)
MDRV_CPU_MEMORY(akkaarrh_readmem, akkaarrh_writemem)
/* The interrupt handler must sample VBLANK once per group of four IRQs. */
MDRV_CPU_VBLANK_INT(irq0_line_assert, 4)
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION((int)(1000000.0 * 22 / (60 * 262)))
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
MDRV_SCREEN_SIZE(256, 262)
MDRV_VISIBLE_AREA(0, 255, 0, 239)
MDRV_GFXDECODE(gfxdecodeinfo)
MDRV_PALETTE_LENGTH(256)
MDRV_NVRAM_HANDLER(akkaarrh)
MDRV_VIDEO_START(akkaarrh)
MDRV_VIDEO_UPDATE(akkaarrh)
/* sound hardware */
MDRV_SOUND_ADD(POKEY, pokey_interface)
MACHINE_DRIVER_END
ROM_START( akkaarrh )
ROM_REGION( 0x10000, REGION_CPU1, 0 )
ROM_LOAD( "akka_8000.p1", 0x8000, 0x1000, CRC(578bb162) SHA1(f003d9a63e397c377e4738ca31a637da1da2cbdb) )
ROM_LOAD( "akka_9000.m1", 0x9000, 0x1000, CRC(837fa612) SHA1(2a2ccbf879fd9cfc0342e6c5bbcd23962bdbbcde) )
ROM_LOAD( "akka_a000.l1", 0xa000, 0x1000, CRC(13c769e9) SHA1(8e6c7b21fa555850ba8d00abbb4516e483964b5d) )
ROM_LOAD( "akka_b000.j1", 0xb000, 0x1000, CRC(35c04f28) SHA1(71ad7eaf5bf96c1a0a321f1b04706afd40d9757f) )
ROM_LOAD( "akka_c000.h1", 0xc000, 0x1000, CRC(17e85ac4) SHA1(bd010060eaf8fbf27176d4fdec241ee3b42aece8) )
ROM_LOAD( "akka_d000.e1", 0xd000, 0x1000, CRC(03fb4143) SHA1(3a2106d7322139b9924566133d084bb7c5d769bc) )
ROM_LOAD( "akka_e000.f1", 0xe000, 0x1000, CRC(8d3e671c) SHA1(c99d92c4afaa1ba043520b98d925f83490e49f0a) )
ROM_RELOAD( 0xf000, 0x1000 )
ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "akka_pf0.l6", 0x0000, 0x0800, CRC(5c10b63e) SHA1(27ac6cebb3f6733cb830210f4723938ec2ddaafc) )
ROM_LOAD( "akka_pf1.j6", 0x0800, 0x0800, CRC(636fd64c) SHA1(c2985332b8f32a8dd096fc081df12ae1a132e6a3) )
ROM_LOAD( "akka_pf2.p6", 0x1000, 0x0800, CRC(a5f25d69) SHA1(8f5af774db3ed3969c8c0a0b530ea62198830e3d) )
ROM_LOAD( "akka_pf3.m6", 0x1800, 0x0800, CRC(a3449469) SHA1(42f2ccf6ea02987bfb91ff1ca42684e9700f2f8f) )
ROM_REGION( 0x4000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "akka_mo0.f11", 0x0000, 0x1000, CRC(71bd1bc6) SHA1(9c3d2c039c648834a7a0b98cd2dcbbbb88f74dd8) )
ROM_LOAD( "akka_mo1.d11", 0x1000, 0x1000, CRC(a5ee8ecc) SHA1(d2a8c9791dca9157d9d20b8a4f6e760e6db35f05) )
ROM_LOAD( "akka_mo2.a11", 0x2000, 0x1000, CRC(11cec4d9) SHA1(32ea614c25473aeb9a012a3980ad616592f6c3bb) )
ROM_LOAD( "akka_mo3.b11", 0x3000, 0x1000, CRC(adcf6a36) SHA1(0555a252ba39400d2c533add6ac492926674d6ad) )
ROM_END
GAME( 1982, akkaarrh, 0, akkaarrh, akkaarrh, 0, ROT0, "Atari", "Akka Arrh (prototype)" )
src/drivers/armedf.c
+323 -1
View File
@@ -147,6 +147,7 @@ Stephh's notes (based on the games M68000 code and some tests) :
#include "vidhrdw/generic.h"
#include "cpu/m68000/m68000.h"
#include "cpu/z80/z80.h"
#include "cpu/i8051/i8051.h"
#define LEGION_HACK 0
@@ -178,6 +179,24 @@ extern data16_t *terraf_text_videoram;
extern data16_t *legion_cmd;
extern struct tilemap *armedf_tx_tilemap;
static UINT8 bigfghtr_sharedram[0x3a00];
static READ_HANDLER( bigfghtr_mcu_movx_r )
{
if ( offset >= 0x0600 && offset <= 0x3fff)
return bigfghtr_sharedram[offset-0x600];
else
printf("offset mcu_read: %x\n",offset-0x600);
}
static WRITE_HANDLER( bigfghtr_mcu_movx_w )
{
if ( offset >= 0x0600 && offset <= 0x3fff)
bigfghtr_sharedram[offset-0x600] = data;
else
printf("unmapped offset mcu_write: %x\n",offset);
}
static WRITE16_HANDLER( io_w )
{
@@ -414,6 +433,113 @@ static MEMORY_WRITE16_START( armedf_writemem )
MEMORY_END
static READ16_HANDLER( bigfghtr_sharedram_r )
{
return (bigfghtr_sharedram[offset * 2] << 8) | bigfghtr_sharedram[offset * 2 + 1];
}
static WRITE16_HANDLER( bigfghtr_sharedram_w )
{
if (ACCESSING_MSB)
bigfghtr_sharedram[offset * 2] = data >> 8;
if (ACCESSING_LSB)
bigfghtr_sharedram[offset * 2 + 1] = data;
}
static READ_HANDLER( bigfghtr_mcu_sharedram_r )
{
return bigfghtr_sharedram[offset];
}
static WRITE_HANDLER( bigfghtr_mcu_sharedram_w )
{
bigfghtr_sharedram[offset] = data;
}
static READ_HANDLER( bigfghtr_mcu_p1_r )
{
return 0xdf;
}
static READ16_HANDLER( bigfghtr_latch_r )
{
cpu_set_irq_line(2, I8051_INT0_LINE, CLEAR_LINE);
cpu_set_irq_line(2, I8051_INT0_LINE, ASSERT_LINE);
return 0;
}
static WRITE16_HANDLER( bigfghtr_irq_ack_w )
{
cpu_set_irq_line(0, 1, CLEAR_LINE);
}
static INTERRUPT_GEN( bigfghtr_interrupt )
{
cpu_set_irq_line(0, 1, ASSERT_LINE);
}
static MACHINE_INIT( bigfghtr )
{
memset(bigfghtr_sharedram, 0, sizeof(bigfghtr_sharedram));
armedf_vreg = 0;
cpu_set_irq_line(2, I8051_INT0_LINE, CLEAR_LINE);
}
static MEMORY_READ16_START( bigfghtr_readmem )
{ 0x000000, 0x07ffff, MRA16_ROM },
{ 0x080000, 0x0805ff, MRA16_RAM },
{ 0x080600, 0x083fff, bigfghtr_sharedram_r },
{ 0x084000, 0x085fff, MRA16_RAM },
{ 0x086000, 0x086fff, MRA16_RAM },
{ 0x087000, 0x087fff, MRA16_RAM },
{ 0x088000, 0x089fff, MRA16_RAM },
{ 0x08a000, 0x08afff, MRA16_RAM },
{ 0x08b000, 0x08bfff, MRA16_RAM },
{ 0x08c000, 0x08c001, input_port_0_word_r },
{ 0x08c002, 0x08c003, input_port_1_word_r },
{ 0x08c004, 0x08c005, input_port_2_word_r },
{ 0x08c006, 0x08c007, input_port_3_word_r },
{ 0x400000, 0x400001, bigfghtr_latch_r },
MEMORY_END
static MEMORY_WRITE16_START( bigfghtr_writemem )
{ 0x000000, 0x07ffff, MWA16_ROM },
{ 0x080000, 0x0805ff, MWA16_RAM, &spriteram16, &spriteram_size },
{ 0x080600, 0x083fff, bigfghtr_sharedram_w },
{ 0x084000, 0x085fff, MWA16_RAM },
{ 0x086000, 0x086fff, armedf_bg_videoram_w, &armedf_bg_videoram },
{ 0x087000, 0x087fff, armedf_fg_videoram_w, &armedf_fg_videoram },
{ 0x088000, 0x089fff, armedf_text_videoram_w, &terraf_text_videoram },
{ 0x08a000, 0x08afff, paletteram16_xxxxRRRRGGGGBBBB_word_w, &paletteram16 },
{ 0x08b000, 0x08bfff, MWA16_RAM, &spr_pal_clut },
{ 0x08d000, 0x08d001, terraf_io_w },
{ 0x08d002, 0x08d003, armedf_bg_scrollx_w },
{ 0x08d004, 0x08d005, armedf_bg_scrolly_w },
{ 0x08d006, 0x08d007, armedf_fg_scrollx_w },
{ 0x08d008, 0x08d009, armedf_fg_scrolly_w },
{ 0x08d00a, 0x08d00b, sound_command_w },
{ 0x08d00c, 0x08d00d, MWA16_NOP },
{ 0x08d00e, 0x08d00f, bigfghtr_irq_ack_w },
MEMORY_END
static MEMORY_READ_START( bigfghtr_mcu_readmem )
{ 0x0000, 0x0fff, MRA_ROM },
{ 0x0600, 0x3fff, bigfghtr_mcu_sharedram_r },
MEMORY_END
static MEMORY_WRITE_START( bigfghtr_mcu_writemem )
{ 0x0000, 0x0fff, MWA_ROM },
{ 0x0600, 0x3fff, bigfghtr_mcu_sharedram_w },
MEMORY_END
static PORT_READ_START( bigfghtr_mcu_readport )
{ I8051_P1, I8051_P1, bigfghtr_mcu_p1_r },
PORT_END
static PORT_WRITE_START( bigfghtr_mcu_writeport )
{ I8051_P1, I8051_P3, MWA_NOP },
PORT_END
static MEMORY_READ_START( soundreadmem )
{ 0x0000, 0xf7ff, MRA_ROM },
{ 0xf800, 0xffff, MRA_RAM },
@@ -792,6 +918,83 @@ INPUT_PORTS_START( armedf )
INPUT_PORTS_END
INPUT_PORTS_START( bigfghtr )
PORT_START
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x0200, IP_ACTIVE_LOW )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xf800, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x02, "4" )
PORT_DIPSETTING( 0x01, "5" )
PORT_DIPSETTING( 0x00, "6" )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
PORT_DIPSETTING( 0x0c, "80k then every 80k" )
PORT_DIPSETTING( 0x04, "80k then every 100k" )
PORT_DIPSETTING( 0x08, "100k then every 80k" )
PORT_DIPSETTING( 0x00, "100k then every 100k" )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Demo_Sounds ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0xc0, "Easy" )
PORT_DIPSETTING( 0x80, "Normal" )
PORT_DIPSETTING( 0x40, "Hard" )
PORT_DIPSETTING( 0x00, "Hardest" )
PORT_START
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, "Debug 2 (requires Debug On) (P2 Start skip stage, Invulnerability)" )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, "Debug (P1 Start to pause)" )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
static struct GfxLayout char_layout =
{
@@ -839,7 +1042,14 @@ static struct GfxDecodeInfo gfxdecodeinfo[] =
{ -1 } /* end of array */
};
static struct GfxDecodeInfo bigfghtr_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &char_layout, 0 * 16, 32 },
{ REGION_GFX2, 0, &tile_layout, 64 * 16, 32 },
{ REGION_GFX3, 0, &tile_layout, 96 * 16, 32 },
{ REGION_GFX4, 0, &tile_layout, 32 * 16, 32 },
{ -1 }
};
static struct YM3812interface ym3812_interface =
{
@@ -848,6 +1058,13 @@ static struct YM3812interface ym3812_interface =
{ 50 } /* (not supported) */
};
static struct YM3812interface bigfghtr_ym3812_interface =
{
1, /* 1 chip (no more supported) */
24000000/6, /* 4 MHz */
{ 50 } /* (not supported) */
};
static struct DACinterface dac_interface =
{
2, /* 2 channels */
@@ -861,6 +1078,38 @@ static struct DACinterface cclimbr2_dac_interface =
};
static MACHINE_DRIVER_START( bigfghtr )
MDRV_CPU_ADD(M68000, 16000000/2)
MDRV_CPU_MEMORY(bigfghtr_readmem, bigfghtr_writemem)
MDRV_CPU_VBLANK_INT(bigfghtr_interrupt, 1)
MDRV_CPU_ADD(Z80, 24000000/6)
MDRV_CPU_MEMORY(soundreadmem, soundwritemem)
MDRV_CPU_PORTS(readport, writeport)
MDRV_CPU_PERIODIC_INT(irq0_line_hold, (8000000/2/512))
MDRV_CPU_ADD(I8751, 16000000/2/I8051_CLOCK_DIVIDER)
MDRV_CPU_MEMORY(bigfghtr_mcu_readmem, bigfghtr_mcu_writemem)
MDRV_CPU_PORTS(bigfghtr_mcu_readport, bigfghtr_mcu_writeport)
MDRV_FRAMES_PER_SECOND(8000000.0 / (531 * 254))
MDRV_VBLANK_DURATION(DEFAULT_REAL_60HZ_VBLANK_DURATION)
MDRV_INTERLEAVE(100)
MDRV_MACHINE_INIT(bigfghtr)
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_BUFFERS_SPRITERAM)
MDRV_SCREEN_SIZE(64 * 8, 32 * 8)
MDRV_VISIBLE_AREA(12 * 8, (64 - 12) * 8 - 1, 8, 247)
MDRV_GFXDECODE(bigfghtr_gfxdecodeinfo)
MDRV_PALETTE_LENGTH(2048)
MDRV_VIDEO_EOF(armedf)
MDRV_VIDEO_START(armedf)
MDRV_VIDEO_UPDATE(armedf)
/* sound hardware */
MDRV_SOUND_ADD(YM3812, bigfghtr_ym3812_interface)
MDRV_SOUND_ADD(DAC, dac_interface)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( terraf )
@@ -1272,6 +1521,71 @@ ROM_START( armedf )
ROM_LOAD( "af_12.rom", 0x20000, 0x20000, CRC(23cb6bfe) SHA1(34cb013827206bea71f5336b308ba92bee688506) )
ROM_END
ROM_START( skyrobo )
ROM_REGION( 0x80000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "3", 0x00000, 0x20000, CRC(02d8ba9f) SHA1(7622cc17561e5d1c069341b5f412f732f901d4a8) )
ROM_LOAD16_BYTE( "1", 0x00001, 0x20000, CRC(fcfd9e2e) SHA1(c69b34653f04af8d488e323bc2db89656f76c332) )
ROM_LOAD16_BYTE( "4", 0x40000, 0x20000, CRC(37ced4b7) SHA1(9ded66f795d3c0886f48e52de632e6edb8c57e84) )
ROM_LOAD16_BYTE( "2", 0x40001, 0x20000, CRC(88d52f8e) SHA1(33b0d2b3cd38a13d8580694e7c50c059914eebe2) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "8.17k", 0x00000, 0x10000, CRC(0aeab61e) SHA1(165e0ad58542b65383fef714578da21f62df7b74) )
ROM_REGION( 0x10000, REGION_CPU3, 0 )
ROM_LOAD( "i8751.bin", 0x00000, 0x1000, BAD_DUMP CRC(64a0d225) SHA1(ccc5c33c0c412bf9e3a4f7de5e39b042e00c41dd) )
ROM_REGION( 0x08000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "7", 0x00000, 0x08000, CRC(f556ef28) SHA1(2acb83cdf23356091056f2cfbbc2b9828ee25b6f) )
ROM_REGION( 0x30000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "5.13f", 0x00000, 0x20000, CRC(d440a29f) SHA1(9e6ea7c9903e5e3e8e10ac7680c6120e1aa27250) )
ROM_LOAD( "6.15f", 0x20000, 0x10000, CRC(27469a76) SHA1(ebf2c60e1f70a589680c05adf10771ac2097b9d0) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "12.8a", 0x00000, 0x10000, CRC(a5694ea9) SHA1(ea94174495b3a65b3797932074a94df3b55fa0a2) )
ROM_LOAD( "11.6a", 0x10000, 0x10000, CRC(10b74e2c) SHA1(e3ec68726e7f277dc2043424f2e4d863eb01b3dc) )
ROM_REGION( 0x40000, REGION_GFX4, ROMREGION_DISPOSE )
ROM_LOAD16_BYTE( "9.8d", 0x00000, 0x20000, CRC(fe67800e) SHA1(0d3c4c3cb185270260fa691a97cddf082d6a056e) )
ROM_LOAD16_BYTE( "10.9d", 0x00001, 0x20000, CRC(dcb828c4) SHA1(607bc86580a6fe6e15e91131532b0eecd8b7a0cb) )
ROM_REGION( 0x0100, REGION_PROMS, 0 )
ROM_LOAD( "tf.13h", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) )
ROM_END
ROM_START( bigfghtr )
ROM_REGION( 0x80000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "3.ic3", 0x00000, 0x20000, CRC(e1e1f291) SHA1(dbbd707be6250d9ffcba3fee265869b72f790e26) )
ROM_LOAD16_BYTE( "1.ic2", 0x00001, 0x20000, CRC(1100d991) SHA1(3c79398804b3a26b3df0c5734b270c37e1ba6a60) )
ROM_LOAD16_BYTE( "4.ic5", 0x40000, 0x20000, CRC(2464a83b) SHA1(00f5ac81bc33148daafeab757647b63894e0e0ca) )
ROM_LOAD16_BYTE( "2.ic4", 0x40001, 0x20000, CRC(b47bbcd5) SHA1(811bd4bc8fb662abf4734ab51e24c863d5cc3df3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "8.17k", 0x00000, 0x10000, CRC(0aeab61e) SHA1(165e0ad58542b65383fef714578da21f62df7b74) )
ROM_REGION( 0x10000, REGION_CPU3, 0 )
ROM_LOAD( "i8751.bin", 0x00000, 0x1000, CRC(64a0d225) SHA1(ccc5c33c0c412bf9e3a4f7de5e39b042e00c41dd) )
ROM_REGION( 0x08000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "7.11c", 0x00000, 0x08000, CRC(1809e79f) SHA1(730547771f803857acb552a84a8bc21bd3bda33f) )
ROM_REGION( 0x30000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "5.13f", 0x00000, 0x20000, CRC(d440a29f) SHA1(9e6ea7c9903e5e3e8e10ac7680c6120e1aa27250) )
ROM_LOAD( "6.15f", 0x20000, 0x10000, CRC(27469a76) SHA1(ebf2c60e1f70a589680c05adf10771ac2097b9d0) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "12.8a", 0x00000, 0x10000, CRC(a5694ea9) SHA1(ea94174495b3a65b3797932074a94df3b55fa0a2) )
ROM_LOAD( "11.6a", 0x10000, 0x10000, CRC(10b74e2c) SHA1(e3ec68726e7f277dc2043424f2e4d863eb01b3dc) )
ROM_REGION( 0x40000, REGION_GFX4, ROMREGION_DISPOSE )
ROM_LOAD16_BYTE( "9.8d", 0x00000, 0x20000, CRC(fe67800e) SHA1(0d3c4c3cb185270260fa691a97cddf082d6a056e) )
ROM_LOAD16_BYTE( "10.9d", 0x00001, 0x20000, CRC(dcb828c4) SHA1(607bc86580a6fe6e15e91131532b0eecd8b7a0cb) )
ROM_REGION( 0x0100, REGION_PROMS, 0 )
ROM_LOAD( "tf.13h", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) )
ROM_END
DRIVER_INIT( terraf )
{
@@ -1288,6 +1602,12 @@ DRIVER_INIT( armedf )
armedf_setgfxtype(1);
}
DRIVER_INIT( bigfghtr )
{
armedf_setgfxtype(1);
i8051_set_movx_handlers(2, bigfghtr_mcu_movx_r, bigfghtr_mcu_movx_w);
}
DRIVER_INIT( kodure )
{
data16_t *ROM = (data16_t *)memory_region(REGION_CPU1);
@@ -1341,3 +1661,5 @@ GAMEX( 1987, terrafu, terraf, terraf, terraf, terrafu, ROT0, "Nichibutsu
GAMEX( 1987, kodure, 0, kodure, kodure, kodure, ROT0, "Nichibutsu", "Kodure Ookami (Japan)", GAME_IMPERFECT_GRAPHICS | GAME_UNEMULATED_PROTECTION )
GAMEX( 1988, cclimbr2, 0, cclimbr2, cclimbr2, cclimbr2, ROT0, "Nichibutsu", "Crazy Climber 2 (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, armedf, 0, armedf, armedf, armedf, ROT270, "Nichibutsu", "Armed Formation", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1989, skyrobo, 0, bigfghtr, bigfghtr, bigfghtr, ROT0, "Nichibutsu", "Sky Robo", GAME_IMPERFECT_GRAPHICS )
GAMEX( 1989, bigfghtr, skyrobo,bigfghtr, bigfghtr, bigfghtr, ROT0, "Nichibutsu", "Tatakae! Big Fighter (Japan)", GAME_IMPERFECT_GRAPHICS )
src/drivers/astrocde.c
+4 -4
View File
@@ -156,8 +156,8 @@ static WRITE_HANDLER( seawolf2_sound_2_w ) /* Port 41 */
sample_set_volume(9, (data & 0x80) ? 100 : 0);
/* dive panning controlled by low 3 bits */
sample_set_volume(2, (float)(~data & 0x07) / 70);
sample_set_volume(7, (float)(data & 0x07) / 70);
sample_set_volume(2, (~data & 0x07) * 100 / 7);
sample_set_volume(7, (data & 0x07) * 100 / 7);
if (rising_bits & 0x08)
{
@@ -664,14 +664,14 @@ static struct astrocade_interface astrocade_2chip_interface =
{
2, /* Number of chips */
1789773, /* Clock speed */
{255,255} /* Volume */
{25,25} /* Volume */
};
static struct astrocade_interface astrocade_1chip_interface =
{
1, /* Number of chips */
1789773, /* Clock speed */
{255} /* Volume */
{25} /* Volume */
};
static struct CustomSound_interface gorf_custom_interface =
src/drivers/battlera.c
+13 -4
View File
@@ -23,6 +23,7 @@
#include "driver.h"
#include "vidhrdw/generic.h"
#include "cpu/h6280/h6280.h"
#include "state.h"
VIDEO_UPDATE( battlera );
VIDEO_START( battlera );
@@ -107,11 +108,10 @@ static WRITE_HANDLER( YM2203_w )
}
static int msm5205next;
static int toggle;
static void battlera_adpcm_int(int data)
{
static int toggle;
MSM5205_data_w(0,msm5205next >> 4);
msm5205next<<=4;
@@ -368,5 +368,14 @@ ROM_END
/******************************************************************************/
GAMEX( 1988, battlera, 0, battlera, battlera, 0, ROT0, "Data East Corporation", "Battle Rangers (World)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, bldwolf, battlera, battlera, battlera, 0, ROT0, "Data East USA", "Bloody Wolf (US)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
static DRIVER_INIT( battlera )
{
state_save_register_int("battlera", 0, "control_port_select", &control_port_select);
state_save_register_int("battlera", 0, "msm5205next", &msm5205next);
state_save_register_int("battlera", 0, "adpcm_toggle", &toggle);
}
/******************************************************************************/
GAMEX( 1988, battlera, 0, battlera, battlera, battlera, ROT0, "Data East Corporation", "Battle Rangers (World)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
GAMEX( 1988, bldwolf, battlera, battlera, battlera, battlera, ROT0, "Data East USA", "Bloody Wolf (US)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
src/drivers/bublbobl.c
+41 -1
View File
@@ -138,6 +138,7 @@ CPU 3
#include "driver.h"
#include "vidhrdw/generic.h"
#include "cpu/m6805/m6805.h"
#include "state.h"
static int ddr1, ddr2, ddr3, ddr4;
static int port1_in, port2_in, port3_in, port4_in;
@@ -170,6 +171,26 @@ WRITE_HANDLER( bublbobl_sh_nmi_disable_w );
WRITE_HANDLER( bublbobl_sh_nmi_enable_w );
void bublbobl_save_state(void);
/* save states: the M6801 ports here, the rest in machine/bublbobl_machine.c */
static void bublbobl_register_state(void)
{
bublbobl_save_state();
state_save_register_int("bublbobl", 0, "ddr1", &ddr1);
state_save_register_int("bublbobl", 0, "ddr2", &ddr2);
state_save_register_int("bublbobl", 0, "ddr3", &ddr3);
state_save_register_int("bublbobl", 0, "ddr4", &ddr4);
state_save_register_int("bublbobl", 0, "port1_in", &port1_in);
state_save_register_int("bublbobl", 0, "port2_in", &port2_in);
state_save_register_int("bublbobl", 0, "port3_in", &port3_in);
state_save_register_int("bublbobl", 0, "port4_in", &port4_in);
state_save_register_int("bublbobl", 0, "port1_out", &port1_out);
state_save_register_int("bublbobl", 0, "port2_out", &port2_out);
state_save_register_int("bublbobl", 0, "port3_out", &port3_out);
state_save_register_int("bublbobl", 0, "port4_out", &port4_out);
}
READ_HANDLER( bublbobl_mcu_ddr1_r )
{
return ddr1;
@@ -302,6 +323,24 @@ static unsigned char portA_in,portA_out,ddrA;
static unsigned char portB_in,portB_out,ddrB;
static unsigned char portC_in,portC_out,ddrC;
static void tokio_register_state(void)
{
bublbobl_save_state();
state_save_register_UINT8("tokio", 0, "from_main", &from_main, 1);
state_save_register_UINT8("tokio", 0, "from_mcu", &from_mcu, 1);
state_save_register_int ("tokio", 0, "mcu_sent", &mcu_sent);
state_save_register_int ("tokio", 0, "main_sent", &main_sent);
state_save_register_UINT8("tokio", 0, "portA_in", &portA_in, 1);
state_save_register_UINT8("tokio", 0, "portA_out", &portA_out, 1);
state_save_register_UINT8("tokio", 0, "ddrA", &ddrA, 1);
state_save_register_UINT8("tokio", 0, "portB_in", &portB_in, 1);
state_save_register_UINT8("tokio", 0, "portB_out", &portB_out, 1);
state_save_register_UINT8("tokio", 0, "ddrB", &ddrB, 1);
state_save_register_UINT8("tokio", 0, "portC_in", &portC_in, 1);
state_save_register_UINT8("tokio", 0, "portC_out", &portC_out, 1);
state_save_register_UINT8("tokio", 0, "ddrC", &ddrC, 1);
}
READ_HANDLER( tokio_68705_portA_r )
{
return (portA_out & ddrA) | (portA_in & ~ddrA);
@@ -1720,6 +1759,7 @@ static DRIVER_INIT( bublbobl )
memcpy(ROM+0x08000,ROM+0x10000,0x4000);
bublbobl_video_enable = 1;
bublbobl_register_state();
}
static DRIVER_INIT( boblbobl )
@@ -1745,7 +1785,7 @@ static DRIVER_INIT( tokio )
/* preemptively enable video, the bit is not mapped for this game and */
/* I don't know if it even has it. */
bublbobl_video_enable = 1;
bublbobl_video_enable = 1; tokio_register_state();
}
src/drivers/circus.c
+1 -1
View File
@@ -345,7 +345,7 @@ static INTERRUPT_GEN( ripcord_interrupt )
static struct DACinterface dac_interface =
{
1,
{ 255, 255 }
{ 25, 25 }
};
static MACHINE_DRIVER_START( circus )
src/drivers/cps2.c
+2 -2
View File
@@ -1389,9 +1389,9 @@ static int cps2turbo_music_start(int side, int tune)
return 0;
}
if (side)
sample_set_stereo_volume(1, 0, 255);
sample_set_stereo_volume(1, 0, 100);
else
sample_set_stereo_volume(0, 255, 0);
sample_set_stereo_volume(0, 100, 0);
return 1;
}
src/drivers/djboy.c
+1 -1
View File
@@ -953,7 +953,7 @@ static struct YM2203interface ym2203_interface =
{
1,
3000000, /* ? */
{ YM2203_VOL(0xff,0xff) }, /* gain,volume */
{ YM2203_VOL(25,25) }, /* gain,volume */
{ 0 }, /* port A read */
{ 0 }, /* port B read */
{ 0 }, /* port A write */
src/drivers/firetrk.c
+4 -4
View File
@@ -750,7 +750,7 @@ INPUT_PORTS_START( firetrk )
PORT_START
PORT_BITX(0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_PLAYER1, "Horn", IP_KEY_DEFAULT, IP_JOY_DEFAULT)
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
INPUT_PORTS_END
@@ -816,7 +816,7 @@ INPUT_PORTS_START( superbug )
PORT_BITX(0x04, IP_ACTIVE_HIGH, IPT_BUTTON4, "Gear 3", KEYCODE_C, IP_JOY_DEFAULT )
PORT_BITX(0x08, IP_ACTIVE_HIGH, IPT_BUTTON5, "Gear 4", KEYCODE_V, IP_JOY_DEFAULT )
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
INPUT_PORTS_END
@@ -893,10 +893,10 @@ INPUT_PORTS_START( montecar )
PORT_BITX(0x04, IP_ACTIVE_HIGH, IPT_BUTTON4, "Gear 3", KEYCODE_C, IP_JOY_DEFAULT )
PORT_BITX(0x08, IP_ACTIVE_HIGH, IPT_BUTTON5, "Gear 4", KEYCODE_V, IP_JOY_DEFAULT )
PORT_START /* 8 */
PORT_ADJUSTER( 85, "Motor Frequency" )
PORT_ADJUSTER( 80, "Motor Frequency" )
PORT_START /* 9 */
PORT_ADJUSTER( 80, "Motor Frequency" )
PORT_ADJUSTER( 75, "Drone Motor Frequency" )
INPUT_PORTS_END
src/drivers/fuukifg3.c
+11 -5
View File
@@ -86,6 +86,7 @@ FG-3J ROM-J 507KA0301P04 Rev:1.3
***************************************************************************/
#include "driver.h"
#include "state.h"
#include "vidhrdw/generic.h"
static int fuuki32_raster_enable = 1; /* Enabled by default */
@@ -814,8 +815,13 @@ ROM_END
***************************************************************************/
GAMEX( 1998, asurabld, 0, fuuki32, asurabld, 0, ROT0, "Fuuki", "Asura Blade - Sword of Dynasty (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX( 2001, asurabus, 0, fuuki32, asurabus, 0, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (USA)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusj, asurabus, fuuki32, asurabus, 0, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 1)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusja, asurabus, fuuki32, asurabus, 0, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 2)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusjr, asurabus, fuuki32, asurabusa, 0, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan) (ARCADIA review build)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
static DRIVER_INIT( fuuki32 )
{
state_save_register_UINT8("fuuki32", 0, "shared_ram", fuuki32_shared_ram, sizeof(fuuki32_shared_ram));
}
GAMEX( 1998, asurabld, 0, fuuki32, asurabld, fuuki32, ROT0, "Fuuki", "Asura Blade - Sword of Dynasty (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX( 2001, asurabus, 0, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (USA)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusj, asurabus, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 1)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusja, asurabus, fuuki32, asurabus, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan, set 2)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAMEX( 2000, asurabusjr, asurabus, fuuki32, asurabusa, fuuki32, ROT0, "Fuuki", "Asura Buster - Eternal Warriors (Japan) (ARCADIA review build)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
src/drivers/gng.c
+538
View File
@@ -1233,6 +1233,525 @@ ROM_START( gngmaidentenh )
ROM_LOAD( "mm17maiden.4n", 0x000000, 0x004000, CRC(9fb0faaf) SHA1(903b926b0c22879721fdc8a551c1512dd0773802) )
ROM_END
ROM_START( gngprincess )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_princess_04", 0x04000, 0x004000, CRC(3b6d9dcf) )
ROM_LOAD( "mm_c_princess_03", 0x08000, 0x008000, CRC(134db50c) )
ROM_LOAD( "mm_c_princess_05", 0x10000, 0x008000, CRC(d7e126e2) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessa )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mjg_04princess.10n", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "mjg_03princess.8n", 0x08000, 0x008000, CRC(be9d1e56) )
ROM_LOAD( "mjg_05princess.12n", 0x10000, 0x008000, CRC(f5eb84e6) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mjg_01p_princess.11e", 0x00000, 0x004000, CRC(4ef3637e) )
ROM_IGNORE( 0x004000 )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_08.3e", 0x00000, 0x008000, CRC(c09a716f) )
ROM_LOAD( "capsom_m5m23256p_p_61710z_mmg_07.3c", 0x08000, 0x008000, CRC(0b92b129) )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_06.3b", 0x10000, 0x008000, CRC(830176af) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_12p_princess.4n", 0x00000, 0x008000, CRC(f23401c4) )
ROM_LOAD( "capsom_m5m23256p_p_620108_mjg_11p_princess.3n", 0x08000, 0x008000, CRC(1ab10e35) )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_10p_princess.4l", 0x10000, 0x008000, CRC(3801cb66) )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_09p_princess.3l", 0x18000, 0x008000, CRC(e9edb4bc) )
ROM_END
ROM_START( gngprincessaenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mjg_04princess.10n", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "mjg_03princess.8n", 0x08000, 0x008000, CRC(81cb0d2a) )
ROM_LOAD( "mjg_05princess.12n", 0x10000, 0x008000, CRC(2caa03e3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mjg_01p_princess.11e", 0x00000, 0x004000, CRC(4ef3637e) )
ROM_IGNORE( 0x004000 )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_08.3e", 0x00000, 0x008000, CRC(c09a716f) )
ROM_LOAD( "capsom_m5m23256p_p_61710z_mmg_07.3c", 0x08000, 0x008000, CRC(0b92b129) )
ROM_LOAD( "capsom_m5m23256p_p_616105_mmg_06.3b", 0x10000, 0x008000, CRC(830176af) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_12p_princess.4n", 0x00000, 0x008000, CRC(f23401c4) )
ROM_LOAD( "capsom_m5m23256p_p_620108_mjg_11p_princess.3n", 0x08000, 0x008000, CRC(1ab10e35) )
ROM_LOAD( "capsom_m5m23256p_p_62410p_mjg_10p_princess.4l", 0x10000, 0x008000, CRC(3801cb66) )
ROM_LOAD( "capsom_m5m23256p_p_61710g_mjg_09p_princess.3l", 0x18000, 0x008000, CRC(e9edb4bc) )
ROM_END
ROM_START( gngprincessb )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gg4princess.bin", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "gg3princess.bin", 0x08000, 0x008000, CRC(be9d1e56) )
ROM_LOAD( "gg5princess.bin", 0x10000, 0x008000, CRC(f5eb84e6) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessbenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gg4princess.bin", 0x04000, 0x004000, CRC(1299e52b) )
ROM_LOAD( "gg3princess.bin", 0x08000, 0x008000, CRC(81cb0d2a) )
ROM_LOAD( "gg5princess.bin", 0x10000, 0x008000, CRC(2caa03e3) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessc )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gngprincess.n10", 0x04000, 0x004000, CRC(36e043ad) )
ROM_LOAD( "gng.n9", 0x08000, 0x004000, CRC(b6b91cfb) )
ROM_LOAD( "gngprincess.n8", 0x0c000, 0x004000, CRC(bd17085c) )
ROM_LOAD( "gng.n13", 0x10000, 0x004000, CRC(fd9a8dda) )
ROM_LOAD( "gngprincess.n12", 0x14000, 0x004000, CRC(5199ea50) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesscenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "gngprincess.n10", 0x04000, 0x004000, CRC(36e043ad) )
ROM_LOAD( "gngprincess.n9", 0x08000, 0x004000, CRC(3632f7f5) )
ROM_LOAD( "gngprincess.n8", 0x0c000, 0x004000, CRC(393780fd) )
ROM_LOAD( "gng.n13", 0x10000, 0x004000, CRC(fd9a8dda) )
ROM_LOAD( "gngprincess.n12", 0x14000, 0x004000, CRC(98ce9232) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincessenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_princess_04", 0x04000, 0x004000, CRC(3b6d9dcf) )
ROM_LOAD( "mm_c_princess_03", 0x08000, 0x008000, CRC(a5921aeb) )
ROM_LOAD( "mm_c_princess_05", 0x10000, 0x008000, CRC(d1542dec) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gg17princess.bin", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gg14princess.bin", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesst )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mmt04dprincess.10n", 0x04000, 0x004000, CRC(11dd8836) )
ROM_LOAD( "mmt03dprincess.8n", 0x08000, 0x008000, CRC(9ff8665c) )
ROM_LOAD( "mmt05dprincess.13n", 0x10000, 0x008000, CRC(7e06e90f) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mm01princess.11e", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mm17princess.4n", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "mm16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mm15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mm14princess.4l", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "mm13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mm12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngprincesstenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mmt04dprincess.10n", 0x04000, 0x004000, CRC(11dd8836) )
ROM_LOAD( "mmt03dprincess.8n", 0x08000, 0x008000, CRC(b57e52d7) )
ROM_LOAD( "mmt05dprincess.13n", 0x10000, 0x008000, CRC(e4ee3423) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mm01princess.11e", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mm17princess.4n", 0x00000, 0x004000, CRC(e2043162) )
ROM_LOAD( "mm16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mm15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mm14princess.4l", 0x0c000, 0x004000, CRC(19847a61) )
ROM_LOAD( "mm13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mm12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincess )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "10nprincess.rom", 0x04000, 0x004000, CRC(49dc2d12) )
ROM_LOAD( "8nprincess.rom", 0x08000, 0x008000, CRC(ff005be0) )
ROM_LOAD( "12nprincess.rom", 0x10000, 0x008000, CRC(7c2064ca) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessb )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04bprincess.10n", 0x04000, 0x004000, CRC(3084ed7d) )
ROM_LOAD( "mj03bprincess.8n", 0x08000, 0x008000, CRC(b80cae7a) )
ROM_LOAD( "mj05bprincess.12n", 0x10000, 0x008000, CRC(6f8d3556) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mj01princess.11e", 0x00000, 0x004000, CRC(824ae0fc) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mj17princess.4n", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "mj16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mj15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mj14princess.4l", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "mj13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mj12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessbenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04bprincess.10n", 0x04000, 0x004000, CRC(3084ed7d) )
ROM_LOAD( "mj03bprincess.8n", 0x08000, 0x008000, CRC(de44ac2d) )
ROM_LOAD( "mj05bprincess.12n", 0x10000, 0x008000, CRC(7aefa8a0) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "mm02.14h", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "mj01princess.11e", 0x00000, 0x004000, CRC(824ae0fc) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "mm11.3e", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "mm10.1e", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "mm09.3c", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "mm08.1c", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "mm07.3b", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "mm06.1b", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "mj17princess.4n", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "mj16princess.3n", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "mj15princess.1n", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "mj14princess.4l", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "mj13princess.3l", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "mj12princess.1l", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessc )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04cprincess.bin", 0x04000, 0x004000, CRC(daada743) )
ROM_LOAD( "mj03cprincess.bin", 0x08000, 0x008000, CRC(7d0909cf) )
ROM_LOAD( "mj05cprincess.bin", 0x10000, 0x008000, CRC(0c9ed2e0) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincesscenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04cprincess.bin", 0x04000, 0x004000, CRC(daada743) )
ROM_LOAD( "mj03cprincess.bin", 0x08000, 0x008000, CRC(16fe9d4a) )
ROM_LOAD( "mj05cprincess.bin", 0x10000, 0x008000, CRC(0547b319) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "10nprincess.rom", 0x04000, 0x004000, CRC(49dc2d12) )
ROM_LOAD( "8nprincess.rom", 0x08000, 0x008000, CRC(b526a64b) )
ROM_LOAD( "12nprincess.rom", 0x10000, 0x008000, CRC(1abdbe3e) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessg )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04gprincess.bin", 0x04000, 0x004000, CRC(bd45de21) )
ROM_LOAD( "mj03gprincess.bin", 0x08000, 0x008000, CRC(e6bbe084) )
ROM_LOAD( "mj05gprincess.bin", 0x10000, 0x008000, CRC(cd6ce99c) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( makprincessgenh )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mj04gprincess.bin", 0x04000, 0x004000, CRC(bd45de21) )
ROM_LOAD( "mj03gprincess.bin", 0x08000, 0x008000, CRC(20b5aeeb) )
ROM_LOAD( "mj05gprincess.bin", 0x10000, 0x008000, CRC(21288a1b) )
ROM_REGION( 0x10000, REGION_CPU2, 0 )
ROM_LOAD( "gg2.bin", 0x000000, 0x008000, CRC(615f5b6f) )
ROM_REGION( 0x04000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "gg1princess.bin", 0x00000, 0x004000, CRC(7935494f) )
ROM_REGION( 0x18000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD( "gg11.bin", 0x00000, 0x004000, CRC(ddd56fa9) )
ROM_LOAD( "gg10.bin", 0x04000, 0x004000, CRC(7302529d) )
ROM_LOAD( "gg9.bin", 0x08000, 0x004000, CRC(20035bda) )
ROM_LOAD( "gg8.bin", 0x0c000, 0x004000, CRC(f12ba271) )
ROM_LOAD( "gg7.bin", 0x10000, 0x004000, CRC(e525207d) )
ROM_LOAD( "gg6.bin", 0x14000, 0x004000, CRC(2d77e9b2) )
ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE | ROMREGION_ERASEFF )
ROM_LOAD( "gng13princess.n4", 0x00000, 0x004000, CRC(07c9138a) )
ROM_LOAD( "gg16princess.bin", 0x04000, 0x004000, CRC(1ad1d899) )
ROM_LOAD( "gg15princess.bin", 0x08000, 0x004000, CRC(439d6e7b) )
ROM_LOAD( "gng16princess.l4", 0x0c000, 0x004000, CRC(3cc87995) )
ROM_LOAD( "gg13princess.bin", 0x10000, 0x004000, CRC(05e0c809) )
ROM_LOAD( "gg12princess.bin", 0x14000, 0x004000, CRC(28fe68a2) )
ROM_END
ROM_START( gngknight )
ROM_REGION( 0x18000, REGION_CPU1, 0 )
ROM_LOAD( "mm_c_knight_03", 0x08000, 0x008000, CRC(57f4f653) SHA1(7fce045ccffd4274edb75ebd726e42c2cb797dcb) )
@@ -2022,6 +2541,25 @@ GAME( 2026, gngmaidenc, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Gobl
GAME( 2026, gngmaidencenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (Enhanced) (World? 4)" )
GAME( 2026, gngmaident, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (US)" )
GAME( 2026, gngmaidentenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Maiden Artoria Edition (Enhanced) (US)" )
GAME( 2026, gngprincess, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 1)" )
GAME( 2026, gngprincessa, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 2)" )
GAME( 2026, gngprincessaenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 2)" )
GAME( 2026, gngprincessb, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 3)" )
GAME( 2026, gngprincessbenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 3)" )
GAME( 2026, gngprincessc, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (World? 4)" )
GAME( 2026, gngprincesscenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 4)" )
GAME( 2026, gngprincessenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (World? 1)" )
GAME( 2026, gngprincesst, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (US)" )
GAME( 2026, gngprincesstenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Princess Prin Prin Edition (Enhanced) (US)" )
GAME( 2026, makprincess, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition" )
GAME( 2026, makprincessb, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision B)" )
GAME( 2026, makprincessbenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision B)" )
GAME( 2026, makprincessc, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision C)" )
GAME( 2026, makprincesscenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision C)" )
GAME( 2026, makprincessenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced)" )
GAME( 2026, makprincessg, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Japan revision G)" )
GAME( 2026, makprincessgenh, gng, gng, makaimur, 0, ROT0, "GoodLuckTrying", "Makaimura - Princess Prin Prin Edition (Enhanced) (Japan revision G)" )
GAME( 2026, gngknight, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (World? 1)" )
GAME( 2026, gngknightenh, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (Enhanced) (World? 1)" )
GAME( 2026, gngknighta, gng, gng, gng, 0, ROT0, "GoodLuckTrying", "Ghosts'n Goblins - Knight Artoria Edition (World? 2)" )
src/drivers/inufuku.c
+236 -4
View File
@@ -75,6 +75,8 @@ TODO:
VIDEO_UPDATE( inufuku );
VIDEO_START( inufuku );
void dunk_buffer_sprites(void);
int inufuku_is_dunk;
data16_t *inufuku_bg_videoram;
data16_t *inufuku_bg_rasterram;
@@ -104,17 +106,19 @@ static WRITE16_HANDLER( inufuku_soundcommand_w )
if (ACCESSING_LSB) {
/* hack... sound doesn't work otherwise */
if (data == 0x08) return;
if (!inufuku_is_dunk && data == 0x08) return;
pending_command = 1;
soundlatch_w(0, data & 0xff);
cpu_set_irq_line(1, IRQ_LINE_NMI, PULSE_LINE);
cpu_set_irq_line(1, IRQ_LINE_NMI, inufuku_is_dunk ? ASSERT_LINE : PULSE_LINE);
}
}
static WRITE_HANDLER( pending_command_clear_w )
{
pending_command = 0;
if (inufuku_is_dunk)
cpu_set_irq_line(1, IRQ_LINE_NMI, CLEAR_LINE);
}
static WRITE_HANDLER( inufuku_soundrombank_w )
@@ -133,15 +137,27 @@ static WRITE_HANDLER( inufuku_soundrombank_w )
static MACHINE_INIT( inufuku )
{
;
if (inufuku_is_dunk)
{
pending_command = 0;
inufuku_soundrombank_w(0, 0);
cpu_set_irq_line(1, IRQ_LINE_NMI, CLEAR_LINE);
}
}
static DRIVER_INIT( inufuku )
{
inufuku_is_dunk = 0;
pending_command = 1;
inufuku_soundrombank_w(0, 0);
}
static DRIVER_INIT( dunk )
{
inufuku_is_dunk = 1;
pending_command = 0;
inufuku_soundrombank_w(0, 0);
}
/******************************************************************************
@@ -223,6 +239,50 @@ static MEMORY_WRITE16_START( inufuku_writemem )
{ 0xfd0000, 0xfdffff, MWA16_RAM }, /* work ram*/
MEMORY_END
static MEMORY_READ16_START( dunk_readmem )
{ 0x000000, 0x0fffff, MRA16_ROM }, /* main rom*/
{ 0x180000, 0x180001, input_port_0_word_r },
{ 0x180002, 0x180003, input_port_1_word_r },
{ 0x180004, 0x180005, input_port_2_word_r },
{ 0x180006, 0x180007, input_port_3_word_r },
{ 0x180008, 0x180009, inufuku_eeprom_r }, /* eeprom + input_port_4_word_r*/
{ 0x18000a, 0x18000b, input_port_5_word_r },
{ 0x300000, 0x301fff, MRA16_RAM }, /* palette ram*/
{ 0x400000, 0x401fff, inufuku_bg_videoram_r }, /* bg ram*/
{ 0x402000, 0x403fff, inufuku_text_videoram_r },/* text ram*/
{ 0x404000, 0x40ffff, MRA16_RAM },
{ 0x580000, 0x581fff, MRA16_RAM }, /* sprite table + sprite attribute*/
{ 0x600000, 0x61ffff, MRA16_RAM }, /* cell table*/
{ 0x800000, 0xbfffff, MRA16_ROM }, /* data rom*/
{ 0xfd0000, 0xfdffff, MRA16_RAM }, /* work ram*/
MEMORY_END
static MEMORY_WRITE16_START( dunk_writemem )
{ 0x000000, 0x0fffff, MWA16_ROM }, /* main rom*/
{ 0x100000, 0x100007, MWA16_NOP }, /* ?*/
{ 0x200000, 0x200001, inufuku_eeprom_w }, /* eeprom*/
{ 0x280000, 0x280001, inufuku_soundcommand_w }, /* sound command*/
{ 0x300000, 0x301fff, paletteram16_xGGGGGBBBBBRRRRR_word_w, &paletteram16 }, /* palette ram*/
{ 0x380000, 0x3801ff, MWA16_RAM, &inufuku_bg_rasterram }, /* bg raster ram*/
{ 0x400000, 0x401fff, inufuku_bg_videoram_w, &inufuku_bg_videoram }, /* bg ram*/
{ 0x402000, 0x403fff, inufuku_text_videoram_w, &inufuku_text_videoram }, /* text ram*/
{ 0x404000, 0x40ffff, MWA16_RAM },
{ 0x580000, 0x581fff, MWA16_RAM, &inufuku_spriteram1, &inufuku_spriteram1_size }, /* sprite table + sprite attribute*/
{ 0x600000, 0x61ffff, MWA16_RAM, &inufuku_spriteram2 }, /* cell table*/
{ 0x780000, 0x780013, inufuku_palettereg_w }, /* bg & text palettebank register*/
{ 0x7a0000, 0x7a0023, inufuku_scrollreg_w }, /* bg & text scroll register*/
{ 0x7e0000, 0x7e0001, MWA16_NOP }, /* ?*/
{ 0x800000, 0xbfffff, MWA16_ROM }, /* data rom*/
{ 0xfd0000, 0xfdffff, MWA16_RAM }, /* work ram*/
MEMORY_END
/******************************************************************************
@@ -329,6 +389,70 @@ INPUT_PORTS_START( inufuku )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER3 )
INPUT_PORTS_END
INPUT_PORTS_START( dunk )
PORT_START /* 0*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
PORT_START /* 1*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
PORT_START /* 2*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
PORT_SERVICE_NO_TOGGLE( 0x10, IP_ACTIVE_LOW )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* 3*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER4 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER4 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER4 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER4 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER4 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER4 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER4 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER4 )
PORT_START /* 4*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
PORT_DIPNAME( 0x10, 0x10, "3P/4P" )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* pending sound command*/
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* 5*/
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER3 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER3 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER3 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER3 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER3 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER3 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER3 )
INPUT_PORTS_END
/******************************************************************************
@@ -360,6 +484,19 @@ static struct GfxLayout spritelayout =
128*8
};
static struct GfxLayout dunk_spritelayout =
{
16, 16,
RGN_FRAC(1, 1),
4,
{ 0, 1, 2, 3 },
{ 1*4, 0*4, 3*4, 2*4, 5*4, 4*4, 7*4, 6*4,
9*4, 8*4, 11*4, 10*4, 13*4, 12*4, 15*4, 14*4 },
{ 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64,
8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 },
128*8
};
static struct GfxDecodeInfo inufuku_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tilelayout, 0, 256*16 }, /* bg*/
@@ -368,6 +505,14 @@ static struct GfxDecodeInfo inufuku_gfxdecodeinfo[] =
{ -1 } /* end of array */
};
static struct GfxDecodeInfo dunk_gfxdecodeinfo[] =
{
{ REGION_GFX1, 0, &tilelayout, 0, 256*16 }, // bg
{ REGION_GFX2, 0, &tilelayout, 0, 256*16 }, // text
{ REGION_GFX3, 0, &dunk_spritelayout, 0, 256*16 }, // sprite
{ -1 } /* end of array */
};
/******************************************************************************
@@ -435,6 +580,62 @@ static MACHINE_DRIVER_START( inufuku )
MACHINE_DRIVER_END
static INTERRUPT_GEN( dunk_interrupt )
{
/* Latch the completed list before the IRQ lets the main CPU rewrite it. */
dunk_buffer_sprites();
irq1_line_hold();
}
static struct YM2610interface dunk_ym2610_interface =
{
1,
32000000/4, /* 8.00 MHz */
{ 50 },
{ 0 },
{ 0 },
{ 0 },
{ 0 },
{ irqhandler },
{ REGION_SOUND2 },
{ REGION_SOUND1 },
{ YM3012_VOL(25, MIXER_PAN_CENTER, 25, MIXER_PAN_CENTER) }
};
static MACHINE_DRIVER_START( dunk )
/* basic machine hardware */
MDRV_CPU_ADD(M68000, 32000000/2) /* 16.00 MHz */
MDRV_CPU_MEMORY(dunk_readmem, dunk_writemem)
MDRV_CPU_VBLANK_INT(dunk_interrupt, 1)
MDRV_CPU_ADD(Z80, 32000000/4) /* 8.00 MHz */
MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
MDRV_CPU_MEMORY(inufuku_readmem_sound, inufuku_writemem_sound)
MDRV_CPU_PORTS(inufuku_readport_sound, inufuku_writeport_sound)
/* IRQs are triggered by the YM2610 */
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION(2300)
MDRV_MACHINE_INIT(inufuku)
MDRV_NVRAM_HANDLER(93C46)
/* video hardware */
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
MDRV_SCREEN_SIZE(2048, 256)
MDRV_VISIBLE_AREA(0, 319, 0, 223)
MDRV_GFXDECODE(dunk_gfxdecodeinfo)
MDRV_PALETTE_LENGTH(4096)
MDRV_VIDEO_START(inufuku)
MDRV_VIDEO_UPDATE(inufuku)
/* sound hardware */
MDRV_SOUND_ADD(YM2610, dunk_ym2610_interface)
MACHINE_DRIVER_END
/******************************************************************************
ROM definitions
@@ -466,6 +667,36 @@ ROM_START( inufuku )
ROM_LOAD( "lhmn5ku6.u53", 0x0000000, 0x400000, CRC(b320c5c9) SHA1(7c99da2d85597a3c008ed61a3aa5f47ad36186ec) )
ROM_END
ROM_START( 3on3dunk )
ROM_REGION( 0x0c00000, REGION_CPU1, 0 )
ROM_LOAD16_WORD_SWAP( "prog0_2_4_usa.u147", 0x0000000, 0x080000, CRC(957924ab) SHA1(6fe8ca711d11239310d58188e9d6d28cd27bc5af) )
ROM_LOAD16_WORD_SWAP( "prog1_2_4_usa.u146", 0x0080000, 0x080000, CRC(2479e236) SHA1(729e6c85d34d6925c8d6557b138e2bed43e1de6a) )
ROM_LOAD16_WORD_SWAP( "lh535l5y.u148", 0x0800000, 0x400000, CRC(aa33e02a) SHA1(86381ecf18fba9065cbc02112751c435bbf8b8b4) )
ROM_REGION( 0x0030000, REGION_CPU2, 0 )
ROM_LOAD( "sound_prog_97_1_13.u107", 0x0000000, 0x020000, CRC(d9d42805) SHA1(ab5cb7c141d9c9ed5121ba4dbc1d0fa187bd9f68) )
ROM_RELOAD( 0x010000, 0x020000 )
ROM_REGION( 0x0400000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD16_WORD_SWAP( "lh525kwy.u40", 0x0000000, 0x400000, CRC(aaa426d1) SHA1(2f9a2981f336caf3188baec9a34f61452dee2203) )
ROM_REGION( 0x0400000, REGION_GFX2, ROMREGION_DISPOSE )
ROM_LOAD16_WORD_SWAP( "lh537nn4.u8", 0x0000000, 0x200000, CRC(2b7be1d8) SHA1(aac274a8f4028db7429478601a1761e61ab4f9a2) )
ROM_REGION( 0x2000000, REGION_GFX3, ROMREGION_DISPOSE )
ROM_LOAD( "lh535kwz.u34", 0x0000000, 0x400000, CRC(7372ce78) SHA1(ed2a861986357fad7ef983750cd906c3d722b862) )
ROM_LOAD( "lh535kv0.u36", 0x0400000, 0x400000, CRC(247e5741) SHA1(8d71d964791fb4b86e390bcdf7744f616d6357b1) )
ROM_LOAD( "lh535kv2.u38", 0x0800000, 0x400000, CRC(76449b1e) SHA1(b63d50c6f0dc91dc94dbcdda9842598529c1c26e) )
ROM_LOAD( "lh537nn5.u20", 0x0c00000, 0x200000, CRC(f457cd3b) SHA1(cc13f5dc44e4675c1074a365b10f34e684817d81) )
ROM_LOAD( "lh536pnm.u32", 0x1000000, 0x400000, CRC(bc39e449) SHA1(5aea90b66ee03c70797ddc42dbcb064d83ce8cc7) )
ROM_REGION( 0x0400000, REGION_SOUND1, 0 )
ROM_LOAD( "lh5388r1.u53", 0x0000000, 0x100000, CRC(765d892f) SHA1(9b078c879d0437d1669bf4301fd52a768aa4d293) )
ROM_REGION( 0x0400000, REGION_SOUND2, 0 )
ROM_LOAD( "lh536pkl.u51", 0x0000000, 0x300000, CRC(e4919abf) SHA1(d6af4b9c6ff62f92216c9927027d3b2376416bae) )
ROM_END
/******************************************************************************
@@ -473,4 +704,5 @@ ROM_END
******************************************************************************/
GAMEX( 1998, inufuku, 0, inufuku, inufuku, inufuku, ROT0, "Video System Co.", "Quiz and Variety Sukusuku Inufuku (Japan)", GAME_NO_COCKTAIL )
GAMEX( 1998, inufuku, 0, inufuku, inufuku, inufuku, ROT0, "Video System Co.", "Quiz and Variety Sukusuku Inufuku (Japan)", GAME_NO_COCKTAIL )
GAMEX( 1996, 3on3dunk, 0, dunk, dunk, dunk, ROT0, "Video System Co.", "3 On 3 Dunk Madness (US, prototype? 1997/02/04)", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
src/drivers/megadriv_acbl.c
+1715
View File
File diff suppressed because it is too large. Load diff
src/drivers/megadriv_sunmix.c
+216
View File
@@ -0,0 +1,216 @@
/***************************************************************************
Sun Mixing boards based on the Mega Drive, as in current MAME
(megadriv_sunmix.cpp). Super Bubble Bobble moved here from
drivers/segac2.c.
Supported:
Top Shooter (1995)
Super Bubble Bobble (1996)
Hacked up Mega Drive clones (Top Shooter: an original cartridge based
board with an external ROM board and a JAMMA connector). An AT89C51
MCU reads the inputs and puts them in a shared RAM at 0x200000; it is
not emulated (as in MAME, the dump of Super Bubble Bobble is missing):
the inputs are mapped straight into that RAM.
***************************************************************************/
#include "driver.h"
#include "megadriv.h"
/******************************************************************************
Memory maps
******************************************************************************/
static READ16_HANDLER( topshoot_200051_r )
{
return -0x5b;
}
/* needed to boot, some kind of hardware ident? */
static READ16_HANDLER( sbubsm_400000_r )
{
return 0x5500;
}
static READ16_HANDLER( sbubsm_400002_r )
{
return 0x0f00;
}
static MEMORY_READ16_START( topshoot_readmem )
{ 0x000000, 0x1fffff, MRA16_ROM }, /* Cartridge Program Rom */
{ 0x200042, 0x200043, input_port_0_word_r }, /* shared RAM: the MCU puts the inputs here */
{ 0x200044, 0x200045, input_port_1_word_r },
{ 0x200046, 0x200047, input_port_2_word_r },
{ 0x200048, 0x200049, input_port_3_word_r },
{ 0x200050, 0x200051, topshoot_200051_r },
{ 0x200000, 0x2023ff, MRA16_RAM },
{ 0xa10000, 0xa1001f, genesis_68000_io_r }, /* Genesis Input */
{ 0xa11000, 0xa11203, genesis_ctrl_r },
{ 0xa00000, 0xa0ffff, genesis_68k_to_z80_r },
{ 0xc00000, 0xc0001f, segavdp_r }, /* VDP Access */
{ 0xe00000, 0xe1ffff, MRA16_BANK3 },
{ 0xfe0000, 0xfeffff, MRA16_BANK4 },
{ 0xff0000, 0xffffff, MRA16_RAM }, /* Main Ram */
MEMORY_END
static MEMORY_READ16_START( sbubsm_readmem )
{ 0x000000, 0x1fffff, MRA16_ROM }, /* Cartridge Program Rom */
{ 0x200042, 0x200043, input_port_0_word_r }, /* shared RAM: the MCU puts the inputs here */
{ 0x200044, 0x200045, input_port_1_word_r },
{ 0x200046, 0x200047, input_port_2_word_r },
{ 0x200048, 0x200049, input_port_3_word_r },
{ 0x200050, 0x200051, topshoot_200051_r },
{ 0x20007e, 0x20007f, input_port_4_word_r },
{ 0x200000, 0x2023ff, MRA16_RAM },
{ 0x400000, 0x400001, sbubsm_400000_r },
{ 0x400002, 0x400003, sbubsm_400002_r },
{ 0xa10000, 0xa1001f, genesis_68000_io_r }, /* Genesis Input */
{ 0xa11000, 0xa11203, genesis_ctrl_r },
{ 0xa00000, 0xa0ffff, genesis_68k_to_z80_r },
{ 0xc00000, 0xc0001f, segavdp_r }, /* VDP Access */
{ 0xe00000, 0xe1ffff, MRA16_BANK3 },
{ 0xfe0000, 0xfeffff, MRA16_BANK4 },
{ 0xff0000, 0xffffff, MRA16_RAM }, /* Main Ram */
MEMORY_END
static MEMORY_WRITE16_START( topshoot_writemem )
{ 0x000000, 0x1fffff, MWA16_ROM }, /* Cartridge Program Rom */
{ 0x200000, 0x2023ff, MWA16_RAM }, /* tested */
{ 0xa10000, 0xa1001f, genesis_68000_io_w, &genesis_io_ram }, /* Genesis Input */
{ 0xa11000, 0xa11203, genesis_ctrl_w },
{ 0xa00000, 0xa0ffff, genesis_68k_to_z80_w },
{ 0xc00000, 0xc0000f, segavdp_w }, /* VDP Access */
{ 0xc00010, 0xc00017, sn76489_w }, /* SN76489 Access */
{ 0xfe0000, 0xfeffff, MWA16_BANK4 },
{ 0xff0000, 0xffffff, MWA16_RAM, &genesis_68k_ram }, /* Main Ram */
MEMORY_END
/******************************************************************************
Input ports
******************************************************************************/
INPUT_PORTS_START( topshoot ) /* Top Shooter Input Ports */
PORT_START /* IN0 */
PORT_BIT( 0x4f, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT_IMPULSE( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2, 1 ) /* Bet */
PORT_BIT_IMPULSE( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3, 1 ) /* Start */
PORT_BIT_IMPULSE( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1, 1 ) /* Fire */
PORT_START /* IN1 */
PORT_BIT( 0xe7, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BITX( 0x08, IP_ACTIVE_LOW, IPT_SERVICE, DEF_STR( Service_Mode ), KEYCODE_F2, IP_JOY_NONE )
PORT_BIT_IMPULSE( 0x10, IP_ACTIVE_LOW, IPT_BUTTON4, 1 ) /* Test mode down */
PORT_START /* IN2 */
PORT_BIT( 0xfd, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_LOW, IPT_COIN1, 1 )
PORT_START /* IN3 */
PORT_BIT_IMPULSE( 0x01, IP_ACTIVE_LOW, IPT_COIN2, 1 )
PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
INPUT_PORTS_START( sbubsm )
/* the bit ordering in the ports is strange here because this is being read through shared RAM, the MCU presumably reads the real inputs then scrambles them in RAM for the 68k to sort out */
PORT_START /* IN0 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
PORT_START /* IN1 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START /* IN2 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_LOW, IPT_COIN1, 1 )
PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START /* IN3 */
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START /* IN4 */
PORT_BIT( 0x07, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
/* no service mode here? */
INPUT_PORTS_END
/******************************************************************************
Machine drivers
******************************************************************************/
static MACHINE_DRIVER_START( topshoot )
MDRV_IMPORT_FROM( genesis )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(topshoot_readmem, topshoot_writemem)
MDRV_VISIBLE_AREA(0, 319, 0, 223)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( sbubsm )
MDRV_IMPORT_FROM( genesis )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(sbubsm_readmem, topshoot_writemem)
MDRV_VISIBLE_AREA(0, 319, 0, 223)
MACHINE_DRIVER_END
/******************************************************************************
ROM definitions
******************************************************************************/
ROM_START( topshoot ) /* Top Shooter (c)1995 Sun Mixing */
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* 68000 Code */
ROM_LOAD16_BYTE( "tc574000ad_u11_2.bin", 0x000000, 0x080000, CRC(b235c4d9) SHA1(fbb308a5f6e769f3277824cb6a3b50c308969ac2) )
ROM_LOAD16_BYTE( "tc574000ad_u12_1.bin", 0x000001, 0x080000, CRC(e826f6ad) SHA1(23ec8bb608f954d3b915f061e7076c0c63b8259e) )
ROM_REGION( 0x1000, REGION_USER1, 0 ) /* AT89C51, not hooked up yet (as in MAME) */
ROM_LOAD( "89c51.bin", 0x0000, 0x1000, CRC(595475c8) SHA1(8313819ba06cc92b54f88c1ca9f34be8d1ec94d0) )
ROM_END
ROM_START( sbubsm )
ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* 68000 Code */
ROM_LOAD16_BYTE( "u11.bin", 0x000000, 0x080000, CRC(4f9337ea) SHA1(b245eb615f80afd25e29b2efdddb7f61c1deff6b) )
ROM_LOAD16_BYTE( "u12.bin", 0x000001, 0x080000, CRC(f5374835) SHA1(3a97910f5f7327ec7ad6425dfdfa72c86196ed33) )
/* the AT89C51 (89c51.bin) is not dumped; could be the same as topshoot (same PCB) */
ROM_END
/******************************************************************************
Driver inits
******************************************************************************/
static DRIVER_INIT( topshoot )
{
cpu_setbank(3, memory_region(REGION_CPU1));
cpu_setbank(4, &genesis_68k_ram[0]);
}
/******************************************************************************
Game drivers
******************************************************************************/
GAME( 1995, topshoot, 0, topshoot, topshoot, topshoot, ROT0, "Sun Mixing", "Top Shooter" )
GAME( 1996, sbubsm, 0, sbubsm, sbubsm, topshoot, ROT0, "Sun Mixing", "Super Bubble Bobble (Sun Mixing, Mega Drive clone hardware)" )
src/drivers/megadriv_ybox.c
+693
View File
@@ -0,0 +1,693 @@
/***************************************************************************
Puckman Pockimon and the other games on the Genie / Y-BOX hardware,
as in current MAME (megadriv_ybox.cpp). Moved here from drivers/segac2.c.
A Mega Drive with no real Sega parts (as MAME, emulated as a Mega Drive:
68000, Z80, YM3438, the PSG and the 315-5313 VDP of vidhrdw/segavdp.c)
plus an OKI M6295. The inputs and DIP switches are at 0x700010, the
pads are not used.
Supported:
Puckman Pockimon Genie 2000 (and its bootleg, the old puckpkmn set)
Jingling Jiazu Genie 2000
Juezhan Tianhuang
Songjiangyanyi Final
Shuihu Feng Yun Zhuan
The ROM data lines are scrambled (DRIVER_INIT( puckpkmn )).
Songjiangyanyi and Shuihu Feng Yun Zhuan read back values they write at
0x400000 (two latches), and Shuihu Feng Yun Zhuan remaps the ROM while
a value is written at 0x600000: it calls a routine with some address
lines changed (see sj_rom_ovl_w).
Not included (no ROMs): xmvsfmb, the X-Men vs. Street Fighter bootleg of
MAME on the same board (not working there).
***************************************************************************/
/***************************************************************************
Puckman Pokemon Genie 2000
(c) 2000? Manufacturer ?
Hardware looks bootleg-ish, but is newly manufactured.
CPU: ? (one of the SMD chips)
SND: OKI6295, U6612 (probably YM3812), U6614B (Probably YM3014B)
XTAL: 3.579545MHz, 4.0000MHz
OSC: 53.693175MHz
Other Chips: Possible CPU: TA-06SD 9933 B816453 128 pin square SMD
GFX support chips: Y-BOX TA891945 100 pin SMD
TV16B 0010 ME251271 160 pin SMD
There are 13 PAL's on the PCB !
RAM: 62256 x 3, D41264 x 2 (ZIP Ram)
DIPS: 2 x 8 position
SW1:
1 2 3 4 5 6 7 8
coins 1coin 1 Cred. off off off
2c 1c on off off
3c 1c off on off
4c 1c on on off
5c 1c off off on
1c 2c on off on
1c 3c off on on
1c 4c on on on
players 1 off off off
2 on off off
3 off on off
4 on on off
5 off off on
6 on off on
7 off on on
8 on on on
diffic-
ulty v.easy off off
normal on off
diffic. off on
v. diffic. on on
SW2
note position 3-8 not used
1 2 3 4 5 6 7 8
test mode no off
yes on
demo sound yes off
no on
ROMS:
PUCKPOKE.U3 M5M27C201 Sound
PUCKPOKE.U4 27C040--\
PUCKPOKE.U5 27C040---\
PUCKPOKE.U7 27C040----- Main program & GFX
PUCKPOKE.U8 27C4001---/
ROM sockets U63 & U64 empty
Hi-res PCB scan available on request.
Screenshots available on my site at http://unemulated.emuunlim.com (under PCB Shop Raid #2)
****************************************************************************/
#include "driver.h"
#include "state.h"
#include "megadriv.h"
/******************************************************************************
The Mega Drive part (as MAME's md_ntsc: 68000, Z80, YM2612, PSG, VDP)
*******************************************************************************
The board is a Mega Drive: the 68000 drives the YM3438 at 0xa04000
through the Z80 bus (genesis_68k_to_z80_r/w), and songjang and shuifeng
run a Z80 program. The pads are not used (ybox_io_r): the inputs and
DIP switches are at 0x700010. Version register: Japan (init_megadrij).
******************************************************************************/
static READ16_HANDLER( ybox_io_r )
{
switch (offset)
{
case 0x00:
return 0x2020;
case 0x01:
case 0x02:
{
/* no pad: the lines read high, TH as written */
int ctrl = genesis_io_ram[0x03 + offset];
int data = 0x3f | (genesis_io_ram[offset] & 0x40);
data = (data & ((ctrl ^ 0xff) & 0x7f)) | (genesis_io_ram[offset] & (ctrl | 0x80));
return data | (data << 8);
}
}
return genesis_68000_io_r(offset, mem_mask);
}
/* the main RAM is mirrored in 0xe00000-0xffffff */
static READ16_HANDLER( ybox_ram_r )
{
return genesis_68k_ram[offset & 0x7fff];
}
static WRITE16_HANDLER( ybox_ram_w )
{
COMBINE_DATA(&genesis_68k_ram[offset & 0x7fff]);
}
static struct OKIM6295interface ybox_m6295_intf =
{
1,
{ 8000 }, /* 1MHz / 132 */
{ REGION_SOUND1 },
{ 50 }
};
/* the base map of the board (MAME's puckpkmn_base_map) */
#define YBOX_READ_BASE \
{ 0x000000, 0x3fffff, MRA16_ROM }, /* Main 68k Program Roms */ \
{ 0x700010, 0x700011, input_port_0_word_r }, /* Input (P2) */ \
{ 0x700012, 0x700013, input_port_1_word_r }, /* Input (P1) */ \
{ 0x700014, 0x700015, input_port_2_word_r }, /* Input (?) */ \
{ 0x700016, 0x700017, input_port_3_word_r }, /* Input (DSW1) */ \
{ 0x700018, 0x700019, input_port_4_word_r }, /* Input (DSW2) */ \
{ 0x700022, 0x700023, OKIM6295_status_0_lsb_r }, /* M6295 */ \
{ 0xa00000, 0xa0ffff, genesis_68k_to_z80_r }, /* Z80 bus: RAM, YM3438 */ \
{ 0xa10000, 0xa1001f, ybox_io_r }, /* Mega Drive I/O (no pads) */ \
{ 0xa11000, 0xa11203, genesis_ctrl_r }, /* Z80 bus request / reset */ \
{ 0xc00000, 0xc0001f, segavdp_r }, /* VDP Access */ \
{ 0xe00000, 0xfeffff, ybox_ram_r }, /* Main Ram mirrors */ \
{ 0xff0000, 0xffffff, MRA16_RAM }, /* Main Ram */
#define YBOX_WRITE_BASE \
{ 0x000000, 0x3fffff, MWA16_ROM }, /* Main 68k Program Roms */ \
{ 0x700022, 0x700023, OKIM6295_data_0_lsb_w }, /* M6295 */ \
{ 0xa00000, 0xa0ffff, genesis_68k_to_z80_w }, /* Z80 bus: RAM, YM3438 */ \
{ 0xa10000, 0xa1001f, genesis_68000_io_w, &genesis_io_ram }, /* Mega Drive I/O */ \
{ 0xa11000, 0xa11203, genesis_ctrl_w }, /* Z80 bus request / reset */ \
{ 0xc00000, 0xc0000f, segavdp_w }, /* VDP Access */ \
{ 0xc00010, 0xc00017, sn76489_w }, /* SN76489 Access */ \
{ 0xe00000, 0xfeffff, ybox_ram_w }, /* Main Ram mirrors */ \
{ 0xff0000, 0xffffff, MWA16_RAM, &genesis_68k_ram }, /* Main Ram */
/******************************************************************************
Puckman Pockimon, Jingling Jiazu
******************************************************************************/
/* the ID the game checks at boot */
static READ16_HANDLER( puckpkmn_4b2476_r ) { return 0x3100; }
static READ16_HANDLER( jingling_4b2476_r ) { return 0x3400; }
static READ16_HANDLER( ybox_70001c_0e_r ) { return 0x000e; }
/* the bootleg set: the unknown accesses of MAME's puckpkmnb_map (the Z80
is held in reset, its RAM is not written) */
#define PUCKPKMNB_READ \
{ 0xa10002, 0xa10005, MRA16_NOP }, /* ? alternative way of reading inputs ? */ \
{ 0xa11100, 0xa11101, MRA16_NOP }, /* ? */
static MEMORY_READ16_START( puckpkmnb_readmem )
PUCKPKMNB_READ
YBOX_READ_BASE
MEMORY_END
static MEMORY_WRITE16_START( puckpkmnb_writemem )
{ 0xa00000, 0xa00551, MWA16_NOP }, /* ? */
{ 0xa10002, 0xa10005, MWA16_NOP }, /* ? alternative way of reading inputs ? */
{ 0xa11100, 0xa11101, MWA16_NOP }, /* ? */
{ 0xa11200, 0xa11201, MWA16_NOP }, /* ? */
YBOX_WRITE_BASE
MEMORY_END
static MEMORY_READ16_START( puckpkmn_readmem )
{ 0x4b2476, 0x4b2477, puckpkmn_4b2476_r },
{ 0x70001c, 0x70001d, ybox_70001c_0e_r },
PUCKPKMNB_READ
YBOX_READ_BASE
MEMORY_END
static MEMORY_READ16_START( jingling_readmem )
{ 0x4b2476, 0x4b2477, jingling_4b2476_r },
{ 0x70001c, 0x70001d, ybox_70001c_0e_r },
PUCKPKMNB_READ
YBOX_READ_BASE
MEMORY_END
/******************************************************************************
Juezhan Tianhuang
******************************************************************************/
/* protection: the value is read from 0x710000 after a series of writes and
stored at 0xff0007; without it the game erases the VDP address */
static int jzth_protcount;
static WRITE16_HANDLER( jzth_710000_w )
{
jzth_protcount++;
}
static READ16_HANDLER( jzth_710000_r )
{
UINT16 ret;
switch (jzth_protcount)
{
case 4: ret = 0x4; break;
case 5: ret = 0x5; break;
case 6: ret = 0xe; break;
default: ret = 0xf; break;
}
jzth_protcount = 0;
return ret;
}
static MEMORY_READ16_START( jzth_readmem )
{ 0x710000, 0x710001, jzth_710000_r }, /* protection */
YBOX_READ_BASE
MEMORY_END
static MEMORY_WRITE16_START( jzth_writemem )
{ 0x710000, 0x710001, jzth_710000_w }, /* protection */
YBOX_WRITE_BASE
MEMORY_END
/******************************************************************************
Songjiangyanyi, Shuihu Feng Yun Zhuan
*******************************************************************************
Protection read back, as in current MAME: the games only use byte
accesses on D8-D15, writing with A1 = 1 and reading with A1 = 0; A2
selects one of two latches, which is consistent with every write / read
back pair the games use.
ROM address remapping: shuifeng (and xmvsfmb in MAME) copies a routine
to RAM, masks the interrupts, writes a byte to 0x6xxxxx, jsrs into ROM
and writes 0 to 0x6xxxxx. The code it needs is elsewhere in ROM, at the
call target with some address lines changed; it is modelled as an
address XOR per value (the only one the game uses):
shuifeng 0xfc: 0x25000 -> 0x65000
While a value is latched the ROM is read through sj_rom_ovl_r and the
opcodes are fetched through sj_opbase (OP_ROM moved by the XOR, a 4K page
at a time).
******************************************************************************/
static UINT8 sj_prot_latch[2];
static UINT8 sj_rom_ovl;
static UINT32 sj_rom_ovl_xor;
static UINT16 sj_70001c; /* the value the board returns at 0x70001c */
static UINT32 (*sj_ovl_xor)(UINT8 value);
static UINT32 sj_no_ovl_xor(UINT8 value) { return 0; }
static UINT32 shuifeng_ovl_xor(UINT8 value)
{
switch (value)
{
case 0xfc: return 0x40000; /* 0x12b2 -> jsr 0x25000 */
default: return 0;
}
}
static READ16_HANDLER( sj_prot_r )
{
return sj_prot_latch[(offset >> 1) & 1] << 8;
}
static WRITE16_HANDLER( sj_prot_w )
{
if (ACCESSING_MSB)
sj_prot_latch[(offset >> 1) & 1] = data >> 8;
}
static READ16_HANDLER( sj_rom_ovl_r )
{
const UINT16 *rom = (const UINT16 *)memory_region(REGION_CPU1);
UINT32 mask = memory_region_length(REGION_CPU1) / 2 - 1;
return rom[(offset ^ (sj_rom_ovl_xor >> 1)) & mask];
}
static OPBASE_HANDLER( sj_opbase )
{
UINT8 *rom = memory_region(REGION_CPU1);
if (!sj_rom_ovl_xor || address > 0x3fffff)
return address;
/* the ROM seen with the address lines changed, a 4K page at a time (the
XOR value only changes bits above it); every branch comes back here */
OP_ROM = OP_RAM = rom + ((address ^ sj_rom_ovl_xor) & ~0xfff) - (address & ~0xfff);
OP_MEM_MIN = address & ~0xfff;
OP_MEM_MAX = address | 0xfff;
catch_nextBranch();
return ~0;
}
static void sj_rom_ovl_select(void)
{
if (sj_rom_ovl_xor)
install_mem_read16_handler(0, 0x000000, 0x3fffff, sj_rom_ovl_r);
else
install_mem_read16_handler(0, 0x000000, 0x3fffff, MRA16_ROM);
}
static WRITE16_HANDLER( sj_rom_ovl_w )
{
if (ACCESSING_MSB)
{
UINT32 old = sj_rom_ovl_xor;
sj_rom_ovl = data >> 8;
sj_rom_ovl_xor = sj_rom_ovl ? (*sj_ovl_xor)(sj_rom_ovl) : 0;
if (sj_rom_ovl_xor != old)
{
sj_rom_ovl_select();
catch_nextBranch();
}
}
}
static READ16_HANDLER( sj_70001c_r )
{
return sj_70001c;
}
static void sj_postload(void)
{
sj_rom_ovl_select();
}
static MEMORY_READ16_START( songjang_readmem )
{ 0x400000, 0x4fffff, sj_prot_r }, /* protection read back */
{ 0x70001c, 0x70001d, sj_70001c_r },
YBOX_READ_BASE /* the ROM: see sj_rom_ovl_w */
MEMORY_END
static MEMORY_WRITE16_START( songjang_writemem )
{ 0x01c000, 0x01cfff, MWA16_NOP }, /* writes to the ROM area, buggy code? */
{ 0x400000, 0x4fffff, sj_prot_w }, /* protection read back */
{ 0x600000, 0x6fffff, sj_rom_ovl_w }, /* ROM address remapping */
{ 0x70001a, 0x70001d, MWA16_NOP }, /* written once at boot */
YBOX_WRITE_BASE
MEMORY_END
/******************************************************************************
Input ports
******************************************************************************/
#define YBOX_PLAYER(player, start, button) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, start ) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | player ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | player ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | player ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | player ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, button | player )
#define YBOX_DSW1 \
PORT_START /* DSW 1 ($700017.b) */ \
PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) \
PORT_DIPSETTING( 0x03, DEF_STR( 5C_1C ) ) \
PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) ) \
PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) ) \
PORT_DIPSETTING( 0x06, DEF_STR( 2C_1C ) ) \
PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) ) \
PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) ) \
PORT_DIPSETTING( 0x01, DEF_STR( 1C_3C ) ) \
PORT_DIPSETTING( 0x00, DEF_STR( 1C_4C ) ) \
PORT_DIPNAME( 0x38, 0x28, DEF_STR( Lives ) ) \
PORT_DIPSETTING( 0x38, "1" ) \
PORT_DIPSETTING( 0x30, "2" ) \
PORT_DIPSETTING( 0x28, "3" ) \
PORT_DIPSETTING( 0x20, "4" ) \
PORT_DIPSETTING( 0x18, "5" ) \
PORT_DIPSETTING( 0x10, "6" ) \
PORT_DIPSETTING( 0x08, "7" ) \
PORT_DIPSETTING( 0x00, "8" ) \
PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Difficulty ) ) \
PORT_DIPSETTING( 0xc0, "Easy" ) \
PORT_DIPSETTING( 0x80, "Normal" ) \
PORT_DIPSETTING( 0x40, "Hard" ) \
PORT_DIPSETTING( 0x00, "Hardest" )
#define YBOX_DIP_UNUSED(mask) \
PORT_DIPNAME( mask, mask, DEF_STR( Unused ) ) \
PORT_DIPSETTING( mask, DEF_STR( Off ) ) \
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
#define YBOX_DSW2(demo_sounds) \
PORT_START /* DSW 2 ($700019.b) */ \
PORT_SERVICE( 0x01, IP_ACTIVE_LOW ) \
demo_sounds \
YBOX_DIP_UNUSED( 0x04 ) \
YBOX_DIP_UNUSED( 0x08 ) \
YBOX_DIP_UNUSED( 0x10 ) \
YBOX_DIP_UNUSED( 0x20 ) \
YBOX_DIP_UNUSED( 0x40 ) \
YBOX_DIP_UNUSED( 0x80 )
#define YBOX_DEMO_SOUNDS \
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Demo_Sounds ) ) \
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) \
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
INPUT_PORTS_START( puckpkmn ) /* Puckman Pockimon Input Ports */
PORT_START /* Player 2 Controls ($700011.b) */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
YBOX_PLAYER( IPF_PLAYER2, IPT_START2, IPT_BUTTON1 )
PORT_START /* Player 1 Controls ($700013.b) */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_LOW, IPT_COIN1, 10 )
YBOX_PLAYER( IPF_PLAYER1, IPT_START1, IPT_BUTTON1 )
PORT_START /* ? ($700015.b) */
YBOX_DSW1
YBOX_DSW2( YBOX_DEMO_SOUNDS )
INPUT_PORTS_END
/* the 2nd and 3rd buttons of each player at $700015.b: P2 in bits 0-1 and
P1 in bits 4-5 (jzth, shuifeng), or the other way round */
#define YBOX_BUTTONS_12(lo_player, hi_player) \
PORT_START /* $700015.b */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | lo_player ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | lo_player ) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | hi_player ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | hi_player ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
#define YBOX_PLAYERS_3B \
PORT_START /* Player 2 Controls ($700011.b) */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
YBOX_PLAYER( IPF_PLAYER2, IPT_START2, IPT_BUTTON3 ) \
\
PORT_START /* Player 1 Controls ($700013.b) */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_LOW, IPT_COIN1, 10 ) \
YBOX_PLAYER( IPF_PLAYER1, IPT_START1, IPT_BUTTON3 )
INPUT_PORTS_START( jzth )
YBOX_PLAYERS_3B
YBOX_BUTTONS_12( IPF_PLAYER2, IPF_PLAYER1 )
YBOX_DSW1
YBOX_DSW2( YBOX_DEMO_SOUNDS )
INPUT_PORTS_END
INPUT_PORTS_START( songjang )
YBOX_PLAYERS_3B
YBOX_BUTTONS_12( IPF_PLAYER1, IPF_PLAYER2 )
YBOX_DSW1
YBOX_DSW2( YBOX_DIP_UNUSED( 0x02 ) ) /* no Demo Sounds dip on this one */
INPUT_PORTS_END
/******************************************************************************
Machine drivers
******************************************************************************/
/* V-INT / H-INT through the VDP interrupt enables and the HBLANK status
bit over the whole blanking, as on the real hardware (songjang waits on
HBLANK to write the scroll of each line) */
static MACHINE_INIT( ybox )
{
machine_init_genesis();
genesis_enable_iack();
}
static MACHINE_DRIVER_START( puckpkmnb )
/* basic machine hardware: a Mega Drive */
MDRV_IMPORT_FROM( genesis )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(puckpkmnb_readmem, puckpkmnb_writemem)
MDRV_MACHINE_INIT(ybox)
/* sound hardware */
MDRV_SOUND_ADD(OKIM6295, ybox_m6295_intf)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( puckpkmn )
MDRV_IMPORT_FROM( puckpkmnb )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(puckpkmn_readmem, puckpkmnb_writemem)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( jingling )
MDRV_IMPORT_FROM( puckpkmnb )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(jingling_readmem, puckpkmnb_writemem)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( jzth )
MDRV_IMPORT_FROM( puckpkmnb )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(jzth_readmem, jzth_writemem)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( songjang )
MDRV_IMPORT_FROM( puckpkmnb )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(songjang_readmem, songjang_writemem)
MACHINE_DRIVER_END
/******************************************************************************
ROM definitions
******************************************************************************/
/* Puckman Pockimon (c)2000 Sun Mixing */
ROM_START( puckpkmn )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "200061.u5", 0x000000, 0x080000, CRC(502a5093) SHA1(6dc1c79d52ebb653cb2e4388f74fd975ec323566) )
ROM_LOAD16_BYTE( "200060.u4", 0x000001, 0x080000, CRC(5f160c18) SHA1(5a5ce1b9a81afe836e435e9d6f16cf57b63cbd31) )
ROM_LOAD16_BYTE( "200063.u8", 0x100000, 0x080000, CRC(0c29781e) SHA1(db442f9b588608b2ac04d65fd830103296599a6a) )
ROM_LOAD16_BYTE( "200062.u7", 0x100001, 0x080000, CRC(00bbf9a9) SHA1(924c1ed85090c497ce89528082c15d1548a854a0) )
ROM_REGION( 0x40000, REGION_SOUND1, 0 )
ROM_LOAD( "206295.u3", 0x00000, 0x40000, CRC(7b066bac) SHA1(429616e21c672b07e0705bc63234249cac3af56f) )
ROM_END
ROM_START( jingling )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "b2.u59", 0x000000, 0x080000, CRC(3fbea2c7) SHA1(89f3770ae92c62714f0795ddd2f311a9532eb25a) ) /* FIRST AND SECOND HALF IDENTICAL */
ROM_IGNORE( 0x080000 )
ROM_LOAD16_BYTE( "b1.u59", 0x000001, 0x080000, CRC(dc7b4254) SHA1(8ba5c5e8123e62e9af091971d0d0401d2df49350) ) /* FIRST AND SECOND HALF IDENTICAL */
ROM_IGNORE( 0x080000 )
ROM_LOAD16_BYTE( "b4.u59", 0x100000, 0x080000, CRC(375c9f80) SHA1(9b0eb729e95c22355e4117eec596f90e10282492) ) /* FIRST AND SECOND HALF IDENTICAL */
ROM_IGNORE( 0x080000 )
ROM_LOAD16_BYTE( "b3.u59", 0x100001, 0x080000, CRC(d5487df6) SHA1(d1d3d717e184a4e8e067665bbbe94e7cf45db478) ) /* FIRST AND SECOND HALF IDENTICAL */
ROM_IGNORE( 0x080000 )
ROM_REGION( 0x80000, REGION_SOUND1, 0 )
ROM_LOAD( "a.u3", 0x00000, 0x80000, CRC(77891c9b) SHA1(66f28b418a480a89ddb3fae3a7c2fe702c62364c) )
ROM_END
/* the old puckpkmn set */
ROM_START( puckpkmnb )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "puckpoke.u5", 0x000000, 0x080000, CRC(fd334b91) SHA1(cf8bf6645a4082ea4392937e169b1686c9c7e246) )
ROM_LOAD16_BYTE( "puckpoke.u4", 0x000001, 0x080000, CRC(839cc76b) SHA1(e15662a7175db7a8e222dda176a8ed92e0d56e9d) )
ROM_LOAD16_BYTE( "puckpoke.u8", 0x100000, 0x080000, CRC(7936bec8) SHA1(4b350105abe514fbfeabae1c6f3aeee695c3d07a) )
ROM_LOAD16_BYTE( "puckpoke.u7", 0x100001, 0x080000, CRC(96b66bdf) SHA1(3cc2861ad9bc232cbe683e01b58090f832d03db5) )
ROM_REGION( 0x40000, REGION_SOUND1, 0 )
ROM_LOAD( "puckpoke.u3", 0x00000, 0x40000, CRC(7b066bac) SHA1(429616e21c672b07e0705bc63234249cac3af56f) )
ROM_END
ROM_START( jzth )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "s.y.u5", 0x000000, 0x080000, CRC(a4a526b5) SHA1(85d0299caf91ff50b6870f845b9aacbd358ed81f) )
ROM_LOAD16_BYTE( "s.y.u4", 0x000001, 0x080000, CRC(c16654eb) SHA1(dca4b772a3b9caa7be3fa01511c401b591c2e6f3) )
ROM_LOAD16_BYTE( "s.y.u8", 0x100000, 0x080000, CRC(b62e1068) SHA1(2484ae49a4a2a2c551b3b84bbc0b4e40e5d281e7) )
ROM_LOAD16_BYTE( "s.y.u7", 0x100001, 0x080000, CRC(27fe424c) SHA1(14bee8c16aac3d5b04123c994167531f817634fd) )
ROM_LOAD16_BYTE( "s.y.u64", 0x200000, 0x080000, CRC(62f52886) SHA1(07fc9765274c03eff4a09f48a0b1b2b2afc6078e) )
ROM_LOAD16_BYTE( "s.y.u63", 0x200001, 0x080000, CRC(a6a32c8c) SHA1(d0c779751e4af459e9bf63e55c5e2b19a243b70d) )
ROM_LOAD16_BYTE( "s.y.u66", 0x300000, 0x080000, CRC(fa4a09f5) SHA1(67d77c91a994ecb8b29e7661c3a12e84a64eb837))
ROM_LOAD16_BYTE( "s.y.u65", 0x300001, 0x080000, CRC(de64e526) SHA1(e3b3e5c95b8ae36c0c57f8c9a6f55084464c4c05) )
ROM_REGION( 0x80000, REGION_SOUND1, 0 ) /* there are 2 banks in here, so find bank switch */
ROM_LOAD( "s.y.u3", 0x00000, 0x40000, CRC(38eef2f2) SHA1(2f750dbf71fea0622e8493f0a8be7c43555ed5cf) )
ROM_CONTINUE( 0x40000, 0x40000 )
ROM_END
ROM_START( songjang )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "rom.u5", 0x000000, 0x080000, CRC(3de4aea5) SHA1(a4fd0799a6fd86ba3f0c4b4277190f4c332e48d6) )
ROM_LOAD16_BYTE( "rom.u4", 0x000001, 0x080000, CRC(dc6cfc29) SHA1(e15d6e2187befbbd791c5046cb6d156801095203) )
ROM_LOAD16_BYTE( "rom.u8", 0x100000, 0x080000, CRC(d4d2b262) SHA1(2023128b187a8cd1a3f021861da559b5ad48e984) )
ROM_LOAD16_BYTE( "rom.u7", 0x100001, 0x080000, CRC(1e24f2c9) SHA1(562249b08a8fe317a606c16ce07a8009a0c5418a) )
ROM_REGION( 0x80000, REGION_SOUND1, 0 ) /* only one bank (2nd half is blank) */
ROM_LOAD( "rom.u3", 0x00000, 0x80000, CRC(44287ab4) SHA1(42de2010e73c036a2a0e01c9dd3c1c8aef1a54a1) )
ROM_END
ROM_START( shuifeng )
ROM_REGION( 0x400000, REGION_CPU1, 0 )
ROM_LOAD16_BYTE( "shuihufengyunzhuan.u5", 0x000000, 0x080000, CRC(73208a1a) SHA1(1eff253fe48f9e553a238c4cfd41cc5e5839393f) )
ROM_LOAD16_BYTE( "shuihufengyunzhuan.u4", 0x000001, 0x080000, CRC(e633c02c) SHA1(7ff1091a5b2e7d5e0e616509854fa0058d3cdcf7) )
ROM_LOAD16_BYTE( "shuihufengyunzhuan.u8", 0x100000, 0x080000, CRC(31814eb0) SHA1(3a6b13931d02a0c3b8bd97dc51ac5771a97bd092) )
ROM_LOAD16_BYTE( "shuihufengyunzhuan.u7", 0x100001, 0x080000, CRC(51caef9f) SHA1(252dbb29ae878aaf28cb4586e02d823296eaf378) )
ROM_REGION( 0x80000, REGION_SOUND1, 0 ) /* only one bank (2nd half is blank) */
ROM_LOAD( "shuihufengyunzhuan-oki.u3", 0x00000, 0x80000, CRC(44287ab4) SHA1(42de2010e73c036a2a0e01c9dd3c1c8aef1a54a1) )
ROM_END
/******************************************************************************
Driver inits
******************************************************************************/
static DRIVER_INIT( puckpkmn )
{
data8_t *rom = memory_region(REGION_CPU1);
size_t len = memory_region_length(REGION_CPU1);
size_t i;
/* the data lines are scrambled: a byte permutation, endian neutral */
for (i = 0; i < len; i++)
rom[i] = BITSWAP8(rom[i], 1, 4, 2, 0, 7, 5, 3, 6);
}
static DRIVER_INIT( jzth )
{
jzth_protcount = 0;
state_save_register_int("ybox", 0, "jzth protcount", &jzth_protcount);
init_puckpkmn();
}
static void sj_init(UINT16 value_70001c, UINT32 (*ovl_xor)(UINT8))
{
sj_70001c = value_70001c;
sj_ovl_xor = ovl_xor;
sj_prot_latch[0] = sj_prot_latch[1] = 0;
sj_rom_ovl = 0;
sj_rom_ovl_xor = 0;
memory_set_opbase_handler(0, sj_opbase);
state_save_register_UINT8("ybox", 0, "prot latch", sj_prot_latch, 2);
state_save_register_UINT8("ybox", 0, "rom ovl", &sj_rom_ovl, 1);
state_save_register_UINT32("ybox", 0, "rom ovl xor", &sj_rom_ovl_xor, 1);
state_save_register_func_postload(sj_postload);
init_puckpkmn();
}
static DRIVER_INIT( songjang ) { sj_init(0x0002, sj_no_ovl_xor); }
static DRIVER_INIT( shuifeng ) { sj_init(0x0031, shuifeng_ovl_xor); }
/******************************************************************************
Game drivers
******************************************************************************/
/* Genie Hardware (uses Genesis VDP) also has 'Sun Mixing Co' put into tile RAM */
GAME ( 2000, puckpkmn, 0, puckpkmn, puckpkmn, puckpkmn, ROT0, "Sun Mixing", "Puckman Pockimon Genie 2000" )
GAME ( 2000, jingling, puckpkmn, jingling, puckpkmn, puckpkmn, ROT0, "IBS Co. Ltd", "Jingling Jiazu Genie 2000" )
GAME ( 2000, puckpkmnb, puckpkmn, puckpkmnb, puckpkmn, puckpkmn, ROT0, "bootleg", "Puckman Pockimon Genie 2000 (bootleg)" )
GAMEX( 2000, jzth, 0, jzth, jzth, jzth, ROT0, "<unknown>", "Juezhan Tianhuang", GAME_IMPERFECT_SOUND )
GAMEX( 2000, songjang, 0, songjang, songjang, songjang, ROT0, "WAH LAP", "Songjiangyanyi Final", GAME_IMPERFECT_GRAPHICS ) /* some corruption on the cutscenes between levels (as in MAME) */
GAMEX( 1999, shuifeng, 0, songjang, jzth, shuifeng, ROT0, "WAH LAP", "Shuihu Feng Yun Zhuan", GAME_IMPERFECT_GRAPHICS )
src/drivers/megaplay.c
+1223
View File
File diff suppressed because it is too large. Load diff
src/drivers/megatech.c
+1652
View File
File diff suppressed because it is too large. Load diff
src/drivers/model2.c
+49 -8
View File
@@ -37,6 +37,42 @@ data32_t *model2_bufferram;
static data32_t *model2_backup1;
data32_t *model2_textureram0;
data32_t *model2_textureram1;
UINT8 *model2_texdec0;
UINT8 *model2_texdec1;
/*
The texture sheets taken apart, one byte per texel, for the renderer
(fetch_bilinear_texel): a 32-bit word of texture RAM holds two 2x2
blocks of 4-bit texels. Its texels are at x = xbase + 0..3 and
y = ybase + 0..1 of the 2048x1024 sheet, the rows of the columns past
1024 being folded into the upper half of the RAM; within the word, bit 1
of x picks the block and the parity of x and y the texel. The byte array
is indexed y * 2048 + x and is rebuilt with every write.
*/
static void model2_tex_decode( UINT8 *dec, UINT32 index, UINT32 word )
{
UINT32 r = ( index >> 8 ) & 0x3ff, xa = index & 0xff;
UINT32 xbase = ( r < 512 ) ? xa * 4 : 1024 + xa * 4;
UINT32 ybase = ( r < 512 ) ? r * 2 : r * 2 - 1024;
int j, k;
for( j = 0; j < 2; j++ )
for( k = 0; k < 4; k++ )
{
UINT32 x = xbase + k, y = ybase + j;
UINT32 shift = ( ( x & 2 ) << 3 ) | ( ( ~x & 1 ) << 2 ) | ( ( ~y & 1 ) << 3 );
dec[ y * 2048 + x ] = ( word >> shift ) & 0x0f;
}
}
static void model2_tex_decode_all( void )
{
UINT32 i;
for( i = 0; i < 0x40000; i++ )
{
model2_tex_decode( model2_texdec0, i, model2_textureram0[ i ] );
model2_tex_decode( model2_texdec1, i, model2_textureram1[ i ] );
}
}
data16_t *model2_palram;
data16_t *model2_colorxlat;
UINT8 *model2_lumaram;
@@ -637,6 +673,7 @@ static WRITE32_HANDLER( tex0_w )
model2_textureram0[ offset >> 1 ] = ( model2_textureram0[ offset >> 1 ] & 0xffff0000 ) | ( data & 0xffff );
else
model2_textureram0[ offset >> 1 ] = ( model2_textureram0[ offset >> 1 ] & 0x0000ffff ) | ( ( data & 0xffff ) << 16 );
model2_tex_decode( model2_texdec0, offset >> 1, model2_textureram0[ offset >> 1 ] );
}
static WRITE32_HANDLER( tex1_w )
@@ -646,6 +683,7 @@ static WRITE32_HANDLER( tex1_w )
model2_textureram1[ offset >> 1 ] = ( model2_textureram1[ offset >> 1 ] & 0xffff0000 ) | ( data & 0xffff );
else
model2_textureram1[ offset >> 1 ] = ( model2_textureram1[ offset >> 1 ] & 0x0000ffff ) | ( ( data & 0xffff ) << 16 );
model2_tex_decode( model2_texdec1, offset >> 1, model2_textureram1[ offset >> 1 ] );
}
static READ32_HANDLER( tex0_r )
@@ -672,6 +710,7 @@ static WRITE32_HANDLER( tex2b_w )
{
data32_t *ram = ( offset & 0x80000 ) ? model2_textureram1 : model2_textureram0;
COMBINE_DATA( &ram[ offset & 0x3ffff ] );
model2_tex_decode( ( offset & 0x80000 ) ? model2_texdec1 : model2_texdec0, offset & 0x3ffff, ram[ offset & 0x3ffff ] );
}
static READ32_HANDLER( luma2b_r )
@@ -918,17 +957,14 @@ static MEMORY_WRITE16_START( model2_snd_writemem )
{ 0x400000, 0x400001, model2snd_ctrl_w },
MEMORY_END
static int scsp_last_line = 0;
/* the SCSP raises and drops each level on its own (a negative level drops it,
0 means nothing to do here) */
static void scsp_irq( int irq )
{
if( irq )
{
scsp_last_line = irq;
if( irq > 0 )
cpu_set_irq_line( 2, irq, ASSERT_LINE );
}
else
cpu_set_irq_line( 2, scsp_last_line, CLEAR_LINE );
else if( irq < 0 )
cpu_set_irq_line( 2, -irq, CLEAR_LINE );
}
static struct SCSPinterface scsp_interface =
@@ -1753,6 +1789,7 @@ static void model2_postload( void )
{
int i;
model2_sound_postload();
model2_tex_decode_all();
m_palette_dirty = 1;
model2_palette_refresh();
for( i = 0; i < 4; i++ )
@@ -1782,6 +1819,8 @@ static DRIVER_INIT( model2a )
model2_backup1 = auto_malloc( 0x4000 );
model2_textureram0 = auto_malloc( 0x100000 );
model2_textureram1 = auto_malloc( 0x100000 );
model2_texdec0 = auto_malloc( 2048 * 1024 );
model2_texdec1 = auto_malloc( 2048 * 1024 );
model2_palram = auto_malloc( 0x4000 );
model2_colorxlat = auto_malloc( 0xc000 );
model2_lumaram = auto_malloc( 0x8000 );
@@ -1789,6 +1828,8 @@ static DRIVER_INIT( model2a )
memset( model2_ram2, 0, 0x40000 );
memset( model2_textureram0, 0, 0x100000 );
memset( model2_textureram1, 0, 0x100000 );
memset( model2_texdec0, 0, 2048 * 1024 );
memset( model2_texdec1, 0, 2048 * 1024 );
memset( model2_palram, 0, 0x4000 );
memset( model2_colorxlat, 0, 0xc000 );
memset( model2_lumaram, 0, 0x8000 );
src/drivers/namcos22.c
+3624 -2393
View File
File diff suppressed because it is too large. Load diff
src/drivers/outrun.c
+732 -308
View File
File diff suppressed because it is too large. Load diff
src/drivers/scobra.c
+1 -1
View File
@@ -212,7 +212,7 @@ MEMORY_END
MEMORY_WRITE_START( scobra_sound_writemem )
{ 0x0000, 0x2fff, MWA_ROM },
{ 0x8000, 0x8fff, scobra_soundram_w },
{ 0x8000, 0x8fff, scobra_soundram_w, &scobra_soundram }, /* the base puts the RAM in the save states */
{ 0x8000, 0x83ff, MWA_NOP, &scobra_soundram }, /* only here to initialize pointer */
{ 0x9000, 0x9fff, scramble_filter_w },
MEMORY_END
src/drivers/scramble.c
+123 -4
View File
@@ -719,6 +719,49 @@ INPUT_PORTS_START( triplep )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
INPUT_PORTS_END
/* as Triple Punch, with 1 to 3 lives */
INPUT_PORTS_START( knockoutb )
PORT_START /* IN0 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY | IPF_COCKTAIL )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_START /* IN1 */
PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x00, "1" )
PORT_DIPSETTING( 0x01, "2" )
PORT_DIPSETTING( 0x02, "3" )
PORT_BITX( 0, 0x03, IPT_DIPSWITCH_SETTING | IPF_CHEAT, "256", IP_KEY_NONE, IP_JOY_NONE )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY | IPF_COCKTAIL )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY | IPF_COCKTAIL )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
PORT_START /* IN2 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY | IPF_COCKTAIL )
PORT_DIPNAME( 0x06, 0x00, DEF_STR( Coinage ) )
PORT_DIPSETTING( 0x02, "A 1/2 B 1/1 C 1/2" )
PORT_DIPSETTING( 0x04, "A 1/3 B 3/1 C 1/3" )
PORT_DIPSETTING( 0x00, "A 1/1 B 2/1 C 1/1" )
PORT_DIPSETTING( 0x06, "A 1/4 B 4/1 C 1/4" )
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x08, DEF_STR( Cocktail ) )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY )
PORT_SERVICE( 0x20, IP_ACTIVE_HIGH )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY )
PORT_BITX( 0x80, 0x00, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Rack Test", KEYCODE_F1, IP_JOY_NONE )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
INPUT_PORTS_END
INPUT_PORTS_START( ckongs )
PORT_START /* IN0 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY | IPF_COCKTAIL )
@@ -1314,7 +1357,7 @@ struct GfxDecodeInfo sfx_gfxdecodeinfo[] =
static struct AY8910interface triplep_ay8910_interface =
{
1, /* 1 chip */
14318000/8, /* 1.78975 MHz */
18432000/12, /* 1.536 MHz, from the main CPU crystal (verified on Triple Punch / Knock Out hardware, as current MAME) */
{ 50 },
{ 0 },
{ 0 },
@@ -1830,6 +1873,21 @@ ROM_START( triplep )
ROM_LOAD( "tripprom.6e", 0x0000, 0x0020, CRC(624f75df) SHA1(0e9a7c48dd976af1dca1d5351236d4d5bf7a9dc8) )
ROM_END
ROM_START( triplepa )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "td4.2h", 0x0000, 0x1000, CRC(15a6d46a) SHA1(a76d97876268d303bc18bf6f18f05227a6689b9d) )
ROM_LOAD( "tc3.2k", 0x1000, 0x1000, CRC(bc26d2c0) SHA1(b9934ddb2918f6c4123dafd07cc39ae31d7e28e9) )
ROM_LOAD( "te2.2l", 0x2000, 0x1000, CRC(02025c10) SHA1(16ffc7681d949172034b8c85dc72c1a528309abf) )
ROM_LOAD( "td1.2m", 0x3000, 0x1000, CRC(e9abc42b) SHA1(93b9c55a76e273b4709ee65870c0848a0d3db7cc) )
ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "ta6.5f", 0x0000, 0x0800, CRC(d51cbd6f) SHA1(c3766a69a4599e54b8d7fb893e45802ec8bf6713) )
ROM_LOAD( "ta7.5h", 0x0800, 0x0800, CRC(f21c0059) SHA1(b1ba87f13908e3e662de8bf444f59bd5c2009720) )
ROM_REGION( 0x0020, REGION_PROMS, 0 )
ROM_LOAD( "ta.6e", 0x0000, 0x0020, CRC(624f75df) SHA1(0e9a7c48dd976af1dca1d5351236d4d5bf7a9dc8) )
ROM_END
ROM_START( knockout )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "knockout.2h", 0x0000, 0x1000, CRC(eaaa848e) SHA1(661026567db87206200ee610c3d5f5eb725aeec9) )
@@ -1845,6 +1903,40 @@ ROM_START( knockout )
ROM_LOAD( "tripprom.6e", 0x0000, 0x0020, CRC(624f75df) SHA1(0e9a7c48dd976af1dca1d5351236d4d5bf7a9dc8) )
ROM_END
ROM_START( knockoutb )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "k1-2h.bin", 0x0000, 0x1000, CRC(f16bdd40) SHA1(e14aad2f2820f643f32e1ee4dbb78cd469367498) )
ROM_LOAD( "k2-2k.bin", 0x1000, 0x1000, CRC(fa6214ef) SHA1(5e569b2a4eaf5e4f033cf2375d607c54fb96b1f8) )
ROM_LOAD( "k3-2l.bin", 0x2000, 0x1000, CRC(9f734d29) SHA1(430c53b9c3fa888fe45f9feeb4ad8f92011adc05) )
ROM_LOAD( "k4-2m.bin", 0x3000, 0x1000, CRC(1809ec77) SHA1(97d575f47f861a572a483559790e271c21775ac5) )
ROM_LOAD( "k5-2p.bin", 0x6000, 0x0800, CRC(60c1aa52) SHA1(f0598be70cfca8651edb7bb3c58f01368d6965ce) )
ROM_CONTINUE( 0x5800, 0x0800 )
ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "ta6.5f", 0x0000, 0x0800, CRC(d51cbd6f) SHA1(c3766a69a4599e54b8d7fb893e45802ec8bf6713) )
ROM_LOAD( "ta7.5h", 0x0800, 0x0800, CRC(f21c0059) SHA1(b1ba87f13908e3e662de8bf444f59bd5c2009720) )
ROM_REGION( 0x0020, REGION_PROMS, 0 )
ROM_LOAD( "ta.6e", 0x0000, 0x0020, CRC(624f75df) SHA1(0e9a7c48dd976af1dca1d5351236d4d5bf7a9dc8) )
ROM_END
ROM_START( knockoutc )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "1.bin", 0x0000, 0x1000, CRC(7c386d1e) SHA1(e846a70bebd41b240758ffb2c7801fa7260b314e) )
ROM_LOAD( "2.bin", 0x1000, 0x1000, CRC(85dc1d78) SHA1(61e82cfb5b0f0da6413713293c382ea57074e801) )
ROM_LOAD( "3.bin", 0x2000, 0x1000, CRC(9f734d29) SHA1(430c53b9c3fa888fe45f9feeb4ad8f92011adc05) )
ROM_LOAD( "4.bin", 0x3000, 0x1000, CRC(48e2d6cd) SHA1(7eea464b8cfef84dbad66e33dffaba9515605da6) )
ROM_LOAD( "5.bin", 0x6000, 0x0800, CRC(26ac55ba) SHA1(876b8bf2ddb0ffb6256d1447408c8b7f7d048d9f) )
ROM_CONTINUE( 0x5800, 0x0800 )
ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "6.bin", 0x0000, 0x0800, CRC(d51cbd6f) SHA1(c3766a69a4599e54b8d7fb893e45802ec8bf6713) )
ROM_LOAD( "7.bin", 0x0800, 0x0800, CRC(f21c0059) SHA1(b1ba87f13908e3e662de8bf444f59bd5c2009720) )
ROM_REGION( 0x0020, REGION_PROMS, 0 )
ROM_LOAD( "ta.6e", 0x0000, 0x0020, CRC(624f75df) SHA1(0e9a7c48dd976af1dca1d5351236d4d5bf7a9dc8) )
ROM_END
ROM_START( mariner )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for main CPU */
ROM_LOAD( "tp1.2h", 0x0000, 0x1000, CRC(dac1dfd0) SHA1(57b9106bb7452640544ba0ab2d2ba290cccb45f0) )
@@ -1891,6 +1983,29 @@ ROM_START( 800fath )
ROM_LOAD( "t5.7p", 0x0000, 0x0020, CRC(1bd88cff) SHA1(8d1620386ef654d99c51e489c822eeb2e8a4fe76) ) /* char banking and star placement */
ROM_END
ROM_START( 800fatha )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for main CPU */
ROM_LOAD( "tq1.2h", 0x0000, 0x1000, CRC(d858c242) SHA1(3f236ae6ac60067eec4f5df0746435e6dfde0401) ) /* older based on letter revision, Q vs U */
ROM_LOAD( "tm2.2k", 0x1000, 0x1000, CRC(efe7ca28) SHA1(496f8eb2ebc9edeed5b19d87f437f23bbeb2a007) )
ROM_LOAD( "tm3.2l", 0x2000, 0x1000, CRC(027881a6) SHA1(47953aa5140a157ade484341609d477510e8342b) )
ROM_LOAD( "tm4.2m", 0x3000, 0x1000, CRC(a0fde7dc) SHA1(ea6700520b1bd31e6c6bfac6f067bbf652676eef) )
ROM_LOAD( "tm5.2p", 0x6000, 0x0800, CRC(d7ebcb8e) SHA1(bddefdc5f04c2f940e08a6968fbd6f930d16b8e4) )
ROM_CONTINUE( 0x5800, 0x0800 )
ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "tm8.5f", 0x0000, 0x1000, CRC(70ae611f) SHA1(2686dc6d3910bd58b290d6296f30c552686709f5) )
ROM_LOAD( "tm9.5h", 0x1000, 0x1000, CRC(8e4e999e) SHA1(195e6896ca2f3175137d8c92777ba32c41e835d3) )
ROM_REGION( 0x0020, REGION_PROMS, 0 )
ROM_LOAD( "t4.6e", 0x0000, 0x0020, CRC(ca42b6dd) SHA1(d1e224e788e3dcf57249e72f03f9fe3fd71e6c12) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "t6.6p", 0x0000, 0x0100, CRC(ad208ccc) SHA1(66a4122e46467344a7f3ddcc953a5f7f451411fa) ) /* background color prom */
ROM_REGION( 0x0020, REGION_USER2, 0 )
ROM_LOAD( "t5.7p", 0x0000, 0x0020, CRC(1bd88cff) SHA1(8d1620386ef654d99c51e489c822eeb2e8a4fe76) ) /* char banking and star placement */
ROM_END
ROM_START( ckongs )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "vid_2c.bin", 0x0000, 0x1000, CRC(49a8c234) SHA1(91d8da03a76094b6fed4bf1d9a3943dee72bf039) )
@@ -2161,10 +2276,14 @@ GAME( 1980, theend, 0, theend, theend, theend, ROT90, "Konami
GAME( 1980, theends, theend, theend, theend, theend, ROT90, "[Konami] (Stern license)", "The End (Stern)" )
GAME( 1981, froggers, frogger, froggers, froggers, froggers, ROT90, "bootleg", "Frog" )
GAME( 1982, amidars, amidar, scramble, amidars, atlantis, ROT90, "Konami", "Amidar (Scramble hardware)" )
GAME( 1982, triplep, 0, triplep, triplep, scramble_ppi, ROT90, "KKI", "Triple Punch" )
GAME( 1982, knockout, triplep, triplep, triplep, scramble_ppi, ROT90, "KKK", "Knock Out!!" )
GAME( 1982, triplep, 0, triplep, triplep, scramble_ppi, ROT90, "K.K. International", "Triple Punch (set 1)" )
GAME( 1982, triplepa, triplep, triplep, triplep, scramble_ppi, ROT90, "K.K. International", "Triple Punch (set 2)" )
GAME( 1982, knockout, triplep, triplep, triplep, scramble_ppi, ROT90, "bootleg? (KKK)", "Knock Out!! (bootleg, set 1)" )
GAME( 1982, knockoutb,triplep, triplep, knockoutb,knockoutb, ROT90, "bootleg", "Knock Out!! (bootleg, set 2)" )
GAME( 1982, knockoutc,triplep, triplep, knockoutb,knockoutb, ROT90, "bootleg (ESG)", "Knock Out!! (bootleg, set 3)" ) /* ESG = Elektronik Spiel Gerate */
GAMEX(1981, mariner, 0, mariner, scramble, mariner, ROT90, "Amenip", "Mariner", GAME_IMPERFECT_SOUND )
GAME( 1981, 800fath, mariner, mariner, scramble, mariner, ROT90, "Amenip (US Billiards Inc. license)", "800 Fathoms" )
GAMEX(1981, 800fath, mariner, mariner, scramble, mariner, ROT90, "Amenip (US Billiards Inc. license)", "800 Fathoms", GAME_IMPERFECT_SOUND )
GAMEX(1981, 800fatha, mariner, mariner, scramble, mariner, ROT90, "Amenip (US Billiards Inc. license)", "800 Fathoms (older)", GAME_IMPERFECT_SOUND )
GAME( 1981, ckongs, ckong, ckongs, ckongs, ckongs, ROT90, "bootleg", "Crazy Kong (Scramble hardware)" )
GAME( 1981, mars, 0, mars, mars, mars, ROT90, "Artic", "Mars" )
GAME( 1982, devilfsh, 0, devilfsh, devilfsh, devilfsh, ROT90, "Artic", "Devil Fish" )
src/drivers/segac2.c
+2330 -5973
View File
File diff suppressed because it is too large. Load diff
src/drivers/segas16b.c
+352 -3
View File
@@ -3,6 +3,8 @@
#include "cpu/i8039/i8039.h"
#include "vidhrdw/segaic16.h"
#include "machine/fd1089.h"
#include "machine/fd1094.h"
#include "state.h"
#include "sound/dac.h"
WRITE_HANDLER( dac_data_w );
WRITE_HANDLER( dfjail_sound_control_w);
@@ -124,6 +126,28 @@ static PORT_WRITE_START( sound_writeport_dfjail )
{ 0x80, 0x83, dac_data_w },
PORT_END
/* the sound CPU ROM bank at 0x8000, relative to REGION_CPU2 + 0x10000 */
static UINT32 sound_bank_offset;
static void set_sound_bank(UINT32 offset)
{
sound_bank_offset = offset;
cpu_setbank(1, memory_region(REGION_CPU2) + 0x10000 + offset);
}
static void sound_bank_postload(void)
{
if (memory_region_length(REGION_CPU2) > 0x10000)
cpu_setbank(1, memory_region(REGION_CPU2) + 0x10000 + sound_bank_offset);
}
static void segas16b_state_register(void)
{
state_save_register_UINT32("segas16b", 0, "sound_bank", &sound_bank_offset, 1);
state_save_register_UINT8 ("segas16b", 0, "nmi_enable", &nmi_enable, 1);
state_save_register_func_postload(sound_bank_postload);
}
WRITE_HANDLER( UPD7759_bank_w )
{
int bankoffs=0;
@@ -187,7 +211,7 @@ WRITE_HANDLER( UPD7759_bank_w )
bankoffs += (data & 0x07) * 0x04000;
break;
}
cpu_setbank(1, memory_region(REGION_CPU2) + 0x10000 + (bankoffs % size));
set_sound_bank(bankoffs % size);
}
}
@@ -250,7 +274,7 @@ WRITE_HANDLER( dfjail_sound_control_w)
bankoffs += (data & 0x07) * 0x4000;
// set the final bank
cpu_setbank(1, memory_region(REGION_CPU2) + 0x10000 + (bankoffs % size));
set_sound_bank(bankoffs % size);
}
struct upd7759_interface sys16b_upd7759_interface =
@@ -1534,6 +1558,182 @@ ROM_START( bulletd )
ROM_LOAD( "epr10998.a8", 0x10000, 0x8000, CRC(f971a817) SHA1(502c95638e4fd5f87e5fc837cb44b39a5d62f4e4) )
ROM_END
ROM_START( cotton )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "epr-13921a.a7", 0x000000, 0x20000, CRC(f047a037) SHA1(e4a9eeb1f2cf6b5ee3b2fcf74be917ffd3e6ca0e) )
ROM_LOAD16_BYTE( "epr-13919a.a5", 0x000001, 0x20000, CRC(651108b1) SHA1(1ab32085ca1a8cb3d464059b0abb10253decd423) )
ROM_LOAD16_BYTE( "epr-13922a.a8", 0x080000, 0x20000, CRC(1ca248c5) SHA1(f7df2ccf54a3f1f09334c3b3df3dcd2ec33f99d1) )
ROM_LOAD16_BYTE( "epr-13920a.a6", 0x080001, 0x20000, CRC(fa3610f9) SHA1(6127496bf7cd47d4343291fc2e11673d77ccc550) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* decryption key */
ROM_LOAD( "317-0181a.key", 0x0000, 0x2000, CRC(5c419b36) SHA1(df43153fc0420c42ca1559fb318bb21101e10f17) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13894.b12",0x180000, 0x20000, CRC(e3d0bee2) SHA1(503a78123ca9d6f3405972bca281dcdaba929c99) )
ROM_LOAD16_BYTE( "opr-13891.a3", 0x180001, 0x20000, CRC(c6b3c414) SHA1(0f0d936e77eb483be8865e8d968d78260e88ca99) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13892.a10", 0x00000, 0x08000, CRC(fdfbe6ad) SHA1(9ebb94889c0e96e6af9cdced084804ca98612d61) )
ROM_LOAD( "opr-13893.a11", 0x10000, 0x20000, CRC(384233df) SHA1(dfdf94697587a5ee45e97700f3741be54b90742b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonu )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "cotton.a7", 0x000000, 0x20000, CRC(e7ef7d10) SHA1(de70ebf04d78e938bf568df158a47b377ddb3dc5) )
ROM_LOAD16_BYTE( "cotton.a5", 0x000001, 0x20000, CRC(abe4f83e) SHA1(128f1815ecb27ee2a93e9d0708fdf6733dd1ab46) )
ROM_LOAD16_BYTE( "cotton.a8", 0x080000, 0x20000, CRC(fc0f4401) SHA1(e20fd6a3906b484c48abd9139744f7f960d751e1) )
ROM_LOAD16_BYTE( "cotton.a6", 0x080001, 0x20000, CRC(f50f1ea2) SHA1(b53a18a71de4d0c7cba8bfcc156818712af9e2d5) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* decryption key */
ROM_LOAD( "317-0180.key", 0x0000, 0x2000, CRC(a236b915) SHA1(374f2b23f0822891aadb86b779434ae2a1194932) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13894.b12",0x180000, 0x20000, CRC(e3d0bee2) SHA1(503a78123ca9d6f3405972bca281dcdaba929c99) )
ROM_LOAD16_BYTE( "opr-13891.a3", 0x180001, 0x20000, CRC(c6b3c414) SHA1(0f0d936e77eb483be8865e8d968d78260e88ca99) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13892.a10", 0x00000, 0x08000, CRC(fdfbe6ad) SHA1(9ebb94889c0e96e6af9cdced084804ca98612d61) )
ROM_LOAD( "opr-13893.a11", 0x10000, 0x20000, CRC(384233df) SHA1(dfdf94697587a5ee45e97700f3741be54b90742b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonj )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "epr-13858b.a7", 0x000000, 0x20000, CRC(2d113dac) SHA1(6a3c3743904ddfcce45faa0642d895463eb8f00f) )
ROM_LOAD16_BYTE( "epr-13856b.a5", 0x000001, 0x20000, CRC(5aab2ac4) SHA1(5a2802bef27581cd31626c0019a7a00fe631d21d) )
ROM_LOAD16_BYTE( "epr-13859b.a8", 0x080000, 0x20000, CRC(2e67367d) SHA1(03068c0d596b459d293947be8db179eb4b8bfd33) )
ROM_LOAD16_BYTE( "epr-13857b.a6", 0x080001, 0x20000, CRC(20361f02) SHA1(44d94e9b40f38d9212f0d254e843f2268dc6b13e) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* decryption key */
ROM_LOAD( "317-0179b.key", 0x0000, 0x2000, CRC(488096d3) SHA1(5ffe81c141e1016f6a46f8fcee3e6d79c60151c0) ) /* Same key data, but labeled as REV B */
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13875.b12",0x180000, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "opr-13854.a3", 0x180001, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13860.a10", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "opr-13061.a11", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonja )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "epr-13858a.a7", 0x000000, 0x20000, CRC(276f42fe) SHA1(47d2f910f6f101628cb0c660e5fd12c0e331bd99) )
ROM_LOAD16_BYTE( "epr-13856a.a5", 0x000001, 0x20000, CRC(14e6b5e7) SHA1(708c69cddd1c60e729a74f539d40e67b2a6d9d6f) )
ROM_LOAD16_BYTE( "epr-13859a.a8", 0x080000, 0x20000, CRC(4703ef9d) SHA1(8b03a71736a599c337ad5d95cbc812ea38b0cc43) )
ROM_LOAD16_BYTE( "epr-13857a.a6", 0x080001, 0x20000, CRC(de37e527) SHA1(124ce7c7eef1199c89735556cebf71255573a155) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* decryption key */
ROM_LOAD( "317-0179a.key", 0x0000, 0x2000, CRC(488096d3) SHA1(5ffe81c141e1016f6a46f8fcee3e6d79c60151c0) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13875.b12",0x180000, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "opr-13854.a3", 0x180001, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13860.a10", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "opr-13061.a11", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottond )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "bootleg_epr-13921a.a7", 0x000000, 0x20000, CRC(92947867) SHA1(6d5f1be45690bacac7093b442ed99c4de56d73a4) )
@@ -1575,6 +1775,129 @@ ROM_START( cottond )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonud )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "bootleg_cotton.a7", 0x000000, 0x20000, CRC(f6b585ca) SHA1(9ed3641f0a8112dfc34394ad78fc9981a1d16fe3) )
ROM_LOAD16_BYTE( "bootleg_cotton.a5", 0x000001, 0x20000, CRC(6b328522) SHA1(f7284297ef4521c864310f19ca6e147d01a28087) )
ROM_LOAD16_BYTE( "bootleg_cotton.a8", 0x080000, 0x20000, CRC(f9147b71) SHA1(f0604b536c6fcb8a0caf3d7d60add8a754acd9c7) )
ROM_LOAD16_BYTE( "bootleg_cotton.a6", 0x080001, 0x20000, CRC(10365de4) SHA1(5662d0e3c9a05d1c40a27877e7b902adc81eec6f) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13894.b12",0x180000, 0x20000, CRC(e3d0bee2) SHA1(503a78123ca9d6f3405972bca281dcdaba929c99) )
ROM_LOAD16_BYTE( "opr-13891.a3", 0x180001, 0x20000, CRC(c6b3c414) SHA1(0f0d936e77eb483be8865e8d968d78260e88ca99) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13892.a10", 0x00000, 0x08000, CRC(fdfbe6ad) SHA1(9ebb94889c0e96e6af9cdced084804ca98612d61) )
ROM_LOAD( "opr-13893.a11", 0x10000, 0x20000, CRC(384233df) SHA1(dfdf94697587a5ee45e97700f3741be54b90742b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonjd )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "bootleg_epr-13858b.a7", 0x000000, 0x20000, CRC(739acf3b) SHA1(640fa874c9759773ad7b297c5a583ad8859677a6) )
ROM_LOAD16_BYTE( "bootleg_epr-13856b.a5", 0x000001, 0x20000, CRC(19597b1f) SHA1(8569b07a10aeae5a75077111eb4d1b3b7fa17974) )
ROM_LOAD16_BYTE( "bootleg_epr-13859b.a8", 0x080000, 0x20000, CRC(10548c39) SHA1(0d040f360926e4e80b182b978dc2fa99ecbe22fb) )
ROM_LOAD16_BYTE( "bootleg_epr-13857b.a6", 0x080001, 0x20000, CRC(6d289f3e) SHA1(9f5601b18b7edf72a5872fed748f00691fd6af0b) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13875.b12",0x180000, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "opr-13854.a3", 0x180001, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13860.a10", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "opr-13061.a11", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
ROM_START( cottonjad )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
ROM_LOAD16_BYTE( "bootleg_epr-13858a.a7", 0x000000, 0x20000, CRC(f048fba4) SHA1(8e4343dc48012ae90c593f73f096de50a46ee62d) )
ROM_LOAD16_BYTE( "bootleg_epr-13856a.a5", 0x000001, 0x20000, CRC(04f5bbe1) SHA1(77dfb0cb15b8711c7efdd2ca9a6a03613eb83950) )
ROM_LOAD16_BYTE( "bootleg_epr-13859a.a8", 0x080000, 0x20000, CRC(fc259bef) SHA1(078d744b9647d816b0b018de2370a1ed1010103b) )
ROM_LOAD16_BYTE( "bootleg_epr-13857a.a6", 0x080001, 0x20000, CRC(e191e939) SHA1(49d3365940e6a236f816ebf584684fa2617d5858) )
ROM_REGION( 0xc0000, REGION_GFX1, 0 ) /* tiles */
ROM_LOAD( "opr-13862.a14", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "opr-13877.b14", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "opr-13863.a15", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "opr-13878.b15", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "opr-13864.a16", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "opr-13879.b16", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION16_BE( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "opr-13869.b5", 0x000000, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "opr-13865.b1", 0x000001, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "opr-13870.b6", 0x040000, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "opr-13866.b2", 0x040001, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "opr-13871.b7", 0x080000, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "opr-13867.b3", 0x080001, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "opr-13872.b8", 0x0c0000, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "opr-13868.b4", 0x0c0001, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "opr-13873.b10",0x100000, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "opr-13852.a1", 0x100001, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "opr-13874.b11",0x140000, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "opr-13853.a2", 0x140001, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "opr-13875.b12",0x180000, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "opr-13854.a3", 0x180001, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "opr-13876.b13",0x1c0000, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "opr-13855.a4", 0x1c0001, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "epr-13860.a10", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "opr-13061.a11", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_REGION( 0x0100, REGION_USER1, 0 )
ROM_LOAD( "315-5298.b9", 0x0000, 0x00eb, CRC(39b47212) SHA1(432b47aee5ecbf08a8a6dc2f8379c816feb86328) ) /* PLS153 */
ROM_END
/*************************************************************************************************************************
Dunk Shot, Sega System 16B
CPU: FD1089A (317-0022)
@@ -1993,6 +2316,7 @@ static const UINT8 alternate_banklist[] = { 255,255,255,255, 255,255,255,3, 255,
static MACHINE_INIT( generic_5704 )
{
int i;
segas16b_state_register();
segaic16_tilemap_reset(0);
for (i = 0; i < 16; i++)
@@ -2005,6 +2329,7 @@ static MACHINE_INIT( generic_5704 )
static MACHINE_INIT( generic_5358 )
{
int i;
segas16b_state_register();
segaic16_tilemap_reset(0);
for (i = 0; i < 16; i++)
@@ -2018,6 +2343,7 @@ static MACHINE_INIT( generic_5358 )
static MACHINE_INIT( dfjail )
{
int i;
segas16b_state_register();
segaic16_tilemap_reset(0);
for (i = 0; i < 16; i++)
@@ -2028,6 +2354,17 @@ static MACHINE_INIT( dfjail )
segaic16_display_enable = 1;
}
static MACHINE_INIT( cotton_fd1094 )
{
machine_init_generic_5704();
fd1094_machine_init();
}
static DRIVER_INIT( cotton_fd1094 )
{
fd1094_driver_init(0, REGION_USER2);
}
static DRIVER_INIT( FD1089A )
{
fd1089a_decrypt();
@@ -2086,6 +2423,11 @@ static MACHINE_DRIVER_START( cotton )
MDRV_MACHINE_INIT(generic_5704)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( cotton_fd1094 )
MDRV_IMPORT_FROM(cotton)
MDRV_MACHINE_INIT(cotton_fd1094)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( dunkshot )
/* basic machine hardware */
MDRV_IMPORT_FROM(system16_7759)
@@ -2166,7 +2508,14 @@ GAME( 1990, aurail1, aurail, aurail, aurail, FD1089B, ROT0, "Sega /
GAME( 1990, aurail1d, aurail, aurail, aurail, 0, ROT0, "Sega / Westone", "Aurail (set 2, World) (unprotected of FD1089B 317-0168 set)" )
GAME( 1990, aurailj, aurail, aurail, aurail, FD1089A, ROT0, "Sega / Westone", "Aurail (set 1, Japan) (FD1089A 317-0167)" )
GAME( 1990, aurailjd, aurail, aurail, aurail, 0, ROT0, "Sega / Westone", "Aurail (set 1, Japan) (unprotected of FD1089A 317-0167 set)" )
GAME( 1991, cottond, cotton, cotton, cotton, 0, ROT0, "Sega / Success", "Cotton (set 4, World) (unprotected of FD1094 317-0181a set)" )
GAME( 1991, cotton, 0, cotton_fd1094, cotton, cotton_fd1094, ROT0, "Success / Sega", "Cotton (set 4, World) (FD1094 317-0181a)" )
GAME( 1991, cottonu, cotton, cotton_fd1094, cotton, cotton_fd1094, ROT0, "Success / Sega", "Cotton (set 3, US) (FD1094 317-0180)" )
GAME( 1991, cottonj, cotton, cotton_fd1094, cotton, cotton_fd1094, ROT0, "Success / Sega", "Cotton (set 2, Japan, Rev B) (FD1094 317-0179b)" )
GAME( 1991, cottonja, cotton, cotton_fd1094, cotton, cotton_fd1094, ROT0, "Success / Sega", "Cotton (set 1, Japan, Rev A) (FD1094 317-0179a)" )
GAME( 1991, cottond, cotton, cotton, cotton, 0, ROT0, "bootleg", "Cotton (set 4, World) (bootleg of FD1094 317-0181a set)" )
GAME( 1991, cottonud, cotton, cotton, cotton, 0, ROT0, "bootleg", "Cotton (set 3, US) (bootleg of FD1094 317-0180 set)" )
GAME( 1991, cottonjd, cotton, cotton, cotton, 0, ROT0, "bootleg", "Cotton (set 2, Japan, Rev B) (bootleg of FD1094 317-0179b set)" )
GAME( 1991, cottonjad,cotton, cotton, cotton, 0, ROT0, "bootleg", "Cotton (set 1, Japan, Rev A) (bootleg of FD1094 317-0179a set)" )
GAME( 1991, dfjail, 0, dfjail, dfjail, 0, ROT0, "Philko", "The Destroyer From Jail (Korea)" )
GAME( 2008, fantzn2x, 0, fantzn2x, fantzn2x, 0, ROT0, "Sega / M2", "Fantasy Zone II - The Tears of Opa-Opa (System 16C version)" )
src/drivers/segas32.c
+14 -12
View File
@@ -3582,8 +3582,6 @@ static DRIVER_INIT ( f1lap )
install_mem_write16_handler(0, 0x800000, 0x800fff, dual_pcb_comms_w);
install_mem_read16_handler (0, 0x801000, 0x801003, dual_pcb_masterslave);
system32_prot_vblank = f1lap_fd1149_vblank;
f1lap_kludge = true;
}
static DRIVER_INIT ( arf )
@@ -3604,12 +3602,21 @@ static DRIVER_INIT ( sonic )
install_mem_read16_handler (0, 0xc00040, 0xc00055, sonic_track_r);
install_mem_write16_handler(0, 0x20E5C4, 0x20E5C5, sonic_level_load_protection);
opaque_blend = false;
}
static DRIVER_INIT ( sonicp )
{
install_mem_write16_handler(0, 0xc00040, 0xc00055, sonic_track_reset_w);
install_mem_read16_handler (0, 0xc00040, 0xc00055, sonic_track_r);
opaque_blend = false;
}
static DRIVER_INIT ( harddunk )
{
opaque_blend = false;
}
static DRIVER_INIT ( radm )
@@ -3622,15 +3629,13 @@ static DRIVER_INIT ( radr )
{
system32_use_default_eeprom = EEPROM_RADR;
install_io_analog();
opaquey_hack = true;
}
static WRITE16_HANDLER( f1en_comms_echo_w )
{
/* pretend that slave is following master op, enables attract mode video with sound */
/* pretend the slave is following the master by copying the master's reply byte into the slave's. */
if (ACCESSING_LSB)
cpu_writemem24lew( 0x810049, data );
dual_pcb_comms[0x48/2] = (data & 0x00ff) | ((data & 0x00ff) << 8);
}
static DRIVER_INIT ( f1en )
@@ -3638,7 +3643,7 @@ static DRIVER_INIT ( f1en )
install_io_analog();
dual_pcb_comms = auto_malloc(sizeof(UINT16)*(0x1000/2));
memset(dual_pcb_comms, 0xff, 0x1000/2);
memset(dual_pcb_comms, 0, sizeof(UINT16)*(0x1000/2));
install_mem_read16_handler (0, 0x810000, 0x810fff, dual_pcb_comms_r);
install_mem_write16_handler(0, 0x810000, 0x810fff, dual_pcb_comms_w);
@@ -3693,8 +3698,6 @@ static DRIVER_INIT( darkedge )
install_mem_read16_handler (0, 0xa00000, 0xa7ffff, darkedge_protection_r);
install_mem_write16_handler(0, 0xa00000, 0xa7ffff, darkedge_protection_w);
system32_prot_vblank = darkedge_fd1149_vblank;
opaquey_hack = true;
}
static DRIVER_INIT( jleague )
@@ -3712,7 +3715,6 @@ static DRIVER_INIT( titlef )
{
install_port_write_handler(1, 0xb0, 0xbf, scross_bank_w);
titlef_kludge = true;
opaquey_hack = true;
}
static DRIVER_INIT( scross )
@@ -3750,8 +3752,8 @@ GAMEX(1995, slipstrh, slipstrm, system32, slipstrm, slipstrm, ROT0, "Capcom"
/* Multi32 games */
GAMEX(1992, orunners, 0, multi32, orunners, 0, ROT0, "Sega", "Outrunners (US)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1994, harddunk, 0, multi32, harddunk, 0, ROT0, "Sega", "Hard Dunk (World)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1994, harddunj, harddunk, multi32, harddunk, 0, ROT0, "Sega", "Hard Dunk (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1994, harddunk, 0, multi32, harddunk, harddunk, ROT0, "Sega", "Hard Dunk (World)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1994, harddunj, harddunk, multi32, harddunk, harddunk, ROT0, "Sega", "Hard Dunk (Japan)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1992, scross, 0, multi32, scross, scross, ROT0, "Sega", "Stadium Cross (World)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1992, scrossa, scross, multi32, scross, scross, ROT0, "Sega", "Stadium Cross (World, linkable)", GAME_IMPERFECT_GRAPHICS )
GAMEX(1992, scrossu, scross, multi32, scross, scross, ROT0, "Sega", "Stadium Cross (US)", GAME_IMPERFECT_GRAPHICS )
src/drivers/segasyse.c
+305 -59
View File
@@ -3,6 +3,13 @@
********************************************************************************
driver by David Haywood
Updated from current MAME (segae.cpp, sega315_5124):
- MC-8123 key based decryption: Opa Opa (317-0042), Fantasy Zone II (317-0057)
- per VDP status, line counter and frame interrupts (only VDP #1 drives the
CPU interrupt), output levels of the 315-5124, per-line CRAM and scroll
latching, mode 4 sprites (8 per line, overflow, collision)
- Sega PSG noise and clock (10.738635 MHz / 3)
Special Thanks to:
Charles Macdonald - for docmentation of the SMS VDP Chip used on this system,
@@ -164,9 +171,17 @@
static UINT8 segae_8000bank; /* Current VDP Bank Selected for 0x8000 - 0xbfff writes */
static UINT8 port_fa_last; /* Last thing written to port 0xfa (control related) */
static UINT8 hintcount; /* line interrupt counter, decreased each scanline */
UINT8 vintpending; /* vertical interrupt pending flag */
UINT8 hintpending; /* scanline interrupt pending flag */
/* VDP status and interrupts, modelled on the MAME 315-5124 device (at
scanline granularity): each VDP has its own frame interrupt flag, line
counter and line interrupt flag, but only the Front Layer VDP (1) drives
the CPU /INT line, which stays asserted until its status is read.
(vintpending / hintpending above are the ones used by megatech.c and
segac2.c, which share the VDP code in vidhrdw/segasyse_vidhrdw.c) */
UINT8 segae_vdp_status[2]; /* 7: frame int, 6: sprite overflow, 5: collision, 4-0: overflow sprite (0x1f if none) */
static UINT8 segae_vdp_hint[2]; /* line interrupt occurred */
static UINT8 segae_vdp_linecount[2]; /* line counter */
/*- in (vidhrdw/segasyse.c) -*/
extern UINT8 segae_vdp_vrambank[]; /* vdp's vram bank */
@@ -198,6 +213,7 @@ void segae_vdp_ctrl_w ( UINT8 chip, UINT8 data );
void segae_vdp_data_w ( UINT8 chip, UINT8 data );
void segae_drawscanline(int line, int chips, int blank);
void segae_latch_hscroll(void);
/*******************************************************************************
Port & Memory Maps
@@ -216,6 +232,15 @@ static MEMORY_READ_START( segae_readmem )
{ 0xc000, 0xffff, MRA_RAM }, /* Main RAM */
MEMORY_END
/* the MC-8123 games read the fixed ROM through a bank: the memory system maps
ROM reads to the same lookup entry as RAM, so without it the opbase handler
would not be called when the CPU jumps between ROM and code in main RAM */
static MEMORY_READ_START( segae_mc8123_readmem )
{ 0x0000, 0x7fff, MRA_BANK2 }, /* Fixed ROM */
{ 0x8000, 0xbfff, MRA_BANK1 }, /* Banked ROM */
{ 0xc000, 0xffff, MRA_RAM }, /* Main RAM */
MEMORY_END
static MEMORY_WRITE_START( segae_writemem )
{ 0x0000, 0x7fff, MWA_ROM }, /* Fixed ROM */
{ 0x8000, 0xbfff, segae_mem_8000_w }, /* Banked VRAM */
@@ -285,7 +310,15 @@ static WRITE_HANDLER (segae_mem_8000_w)
***************************************/
/* each scanline is split in SEGAE_SLICES CPU slices: the VDP line counters and
interrupts are handled at the start of the line, the line is drawn after
the second slice (hpos 68 of 342, MAME draws it at 63) */
#define SEGAE_SLICES 5
#define SEGAE_SLINE() ((262*SEGAE_SLICES - 1 - cpu_getiloops()) / SEGAE_SLICES)
#define SEGAE_SLICE() ((262*SEGAE_SLICES - 1 - cpu_getiloops()) % SEGAE_SLICES)
UINT8 rombank;
static UINT8 segae_rombank_mask = 0x07; /* 0x0f on the boards with 16 ROM banks */
void segae_bankswitch (void)
{
@@ -294,13 +327,89 @@ void segae_bankswitch (void)
cpu_setbank( 1, &RAM[ 0x10000 + ( rombank * 0x4000 ) ] );
}
/*******************************************************************************
MC-8123 encrypted games (Opa Opa, Fantasy Zone II)
********************************************************************************
The Z80 is replaced by a NEC MC-8123: opcodes and data are decrypted with a
different table, picked from the battery-backed key RAM (317-xxxx.key).
Fantasy Zone II only encrypts the fixed ROM at 0x0000-0x7fff, Opa Opa
encrypts the banked ROMs at 0x8000-0xbfff too. Code run from main RAM is not
encrypted. The decrypted opcodes are kept in a copy of REGION_CPU1 with the
same layout, and the opbase handler points the opcode fetches to it.
*******************************************************************************/
void mc8123_decode(UINT8 *rom, UINT8 *opcodes, const UINT8 *key, int start, int end);
static UINT8 *segae_decrypted; /* decrypted opcodes, same layout as REGION_CPU1 */
static int segae_banked_encrypted; /* banked ROMs are encrypted too */
static OPBASE_HANDLER( segae_mc8123_opbase )
{
UINT8 *rom = memory_region(REGION_CPU1);
if (address < 0x8000)
{
/* fixed ROM */
OP_RAM = rom;
OP_ROM = segae_decrypted;
OP_MEM_MIN = 0x0000;
OP_MEM_MAX = 0x7fff;
}
else if (address < 0xc000)
{
/* banked ROM */
offs_t base = 0x10000 + rombank * 0x4000 - 0x8000;
OP_RAM = rom + base;
OP_ROM = (segae_banked_encrypted ? segae_decrypted : rom) + base;
OP_MEM_MIN = 0x8000;
OP_MEM_MAX = 0xbfff;
}
else
{
/* main RAM, not encrypted */
OP_RAM = OP_ROM = rom;
OP_MEM_MIN = 0xc000;
OP_MEM_MAX = 0xffff;
}
/* the core only calls us again when the PC moves to a region with a
different first level lookup entry */
opcode_entry = readmem_lookup[LEVEL1_INDEX(address & 0xffff, 16, 0)];
return ~0;
}
/* recompute the opcode base from the current PC (after a reset or a state
load, where the bank or the PC may have changed under our feet) */
static void segae_mc8123_refresh(void)
{
cpuintrf_push_context(0);
opcode_entry = 0xff;
activecpu_set_op_base(activecpu_get_pc_byte());
cpuintrf_pop_context();
}
static MACHINE_INIT( segae );
static MACHINE_INIT( segae_mc8123 )
{
machine_init_segae();
cpu_setbank(2, memory_region(REGION_CPU1));
memory_set_opbase_handler(0, segae_mc8123_opbase);
/* make the CPU reset go through the opbase handler */
cpuintrf_push_context(0);
opcode_entry = 0xff;
cpuintrf_pop_context();
}
static WRITE_HANDLER (segae_port_f7_w)
{
segae_vdp_vrambank[0] = (data & 0x80) >> 7; /* Back Layer VDP (0) VRAM Bank */
segae_vdp_vrambank[1] = (data & 0x40) >> 6; /* Front Layer VDP (1) VRAM Bank */
segae_8000bank = (data & 0x20) >> 5; /* 0x8000 Write Select */
rombank = data & 0x07; /* Rom Banking */
rombank = data & segae_rombank_mask; /* Rom Banking */
segae_bankswitch();
}
@@ -315,7 +424,7 @@ static READ_HANDLER (segae_port_7e_7f_r)
switch (offset)
{
case 0: /* port 0x7e, Vert Position (in scanlines) */
sline = 261 - cpu_getiloops();
sline = SEGAE_SLINE();
if (sline > 0xDA) sline -= 6;
temp = sline-1 ;
break;
@@ -328,6 +437,45 @@ static READ_HANDLER (segae_port_7e_7f_r)
/*- VDP Related -*/
/* reading the status clears the frame, sprite overflow, collision and line
interrupt flags (and the /INT line for the Front Layer VDP) and resets the
command byte latch */
static UINT8 segae_vdp_status_r(int chip)
{
extern UINT8 segae_vdp_cmdpart[];
UINT8 result = segae_vdp_status[chip];
segae_vdp_status[chip] = 0x1f;
segae_vdp_hint[chip] = 0;
segae_vdp_cmdpart[chip] = 0;
if (chip == 1)
cpu_set_irq_line(0, 0, CLEAR_LINE);
return result;
}
static MACHINE_INIT( segae )
{
SN76496_set_segapsg(0);
SN76496_set_segapsg(1);
segae_vdp_status[0] = segae_vdp_status[1] = 0x1f;
segae_vdp_hint[0] = segae_vdp_hint[1] = 0;
segae_vdp_linecount[0] = segae_vdp_linecount[1] = 0;
}
/* called by vidhrdw/segasyse_vidhrdw.c after a write to register 0 or 1 of
the Front Layer VDP: enabling an interrupt that already occurred asserts
/INT, disabling it clears /INT (as in MAME) */
void segae_vdp_irq_reg_written(int reg)
{
if ((reg == 0 && segae_vdp_hint[1]) || (reg == 1 && (segae_vdp_status[1] & 0x80)))
{
if ((reg == 0 && !(segae_vdp_regs[1][0] & 0x10)) || (reg == 1 && !(segae_vdp_regs[1][1] & 0x20)))
cpu_set_irq_line(0, 0, CLEAR_LINE);
else
cpu_set_irq_line(0, 0, ASSERT_LINE);
}
}
static READ_HANDLER (segae_port_ba_bb_r)
{
/* These Addresses access the Back Layer VDP (0) */
@@ -338,7 +486,7 @@ static READ_HANDLER (segae_port_ba_bb_r)
case 0: /* port 0xba, VDP 0 DATA Read */
temp = segae_vdp_data_r(0); break;
case 1: /* port 0xbb, VDP 0 CTRL Read */
temp = segae_vdp_ctrl_r(0); break;
temp = segae_vdp_status_r(0); break;
}
return temp;
}
@@ -353,7 +501,7 @@ static READ_HANDLER (segae_port_be_bf_r)
case 0: /* port 0xbe, VDP 1 DATA Read */
temp = segae_vdp_data_r(1); break ;
case 1: /* port 0xbf, VDP 1 CTRL Read */
temp = segae_vdp_ctrl_r(1); break ;
temp = segae_vdp_status_r(1); break ;
}
return temp;
}
@@ -723,6 +871,58 @@ INPUT_PORTS_START( opaopa )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
INPUT_PORTS_END
INPUT_PORTS_START( fantzn2 )
PORT_START /* DSW0 Read from Port 0xf2 */
SEGA_COIN_A
SEGA_COIN_B
PORT_START /* DSW1 Read from Port 0xf3 */
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x00, "2" )
PORT_DIPSETTING( 0x0c, "3" )
PORT_DIPSETTING( 0x08, "4" )
PORT_DIPSETTING( 0x04, "5" )
PORT_DIPNAME( 0x30, 0x30, "Timer" )
PORT_DIPSETTING( 0x20, "90" ) /* 210 seconds */
PORT_DIPSETTING( 0x30, "80" ) /* 180 seconds */
PORT_DIPSETTING( 0x10, "70" ) /* 150 seconds */
PORT_DIPSETTING( 0x00, "60" ) /* 120 seconds */
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0x80, "Easy" )
PORT_DIPSETTING( 0xc0, "Normal" )
PORT_DIPSETTING( 0x40, "Hard" )
PORT_DIPSETTING( 0x00, "Hardest" )
PORT_START /* Read from Port 0xe0 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BITX(0x04, IP_ACTIVE_LOW, IPT_SERVICE, DEF_STR( Service_Mode ), KEYCODE_F2, IP_JOY_NONE )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
PORT_START /* Read from Port 0xe1 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START /* Read from Port 0xe2 */
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
INPUT_PORTS_END
INPUT_PORTS_START( tetrisse )
PORT_START /* Read from Port 0xf2 */
SEGA_COIN_A
@@ -929,45 +1129,45 @@ INPUT_PORTS_END
INTERRUPT_GEN( segae_interrupt )
{
int sline;
sline = 261 - cpu_getiloops();
int sline = SEGAE_SLINE();
int chip;
if (sline ==0) {
hintcount = segae_vdp_regs[1][10];
if (SEGAE_SLICE() == 1)
{
if (sline < 192)
segae_drawscanline(sline,1,1);
return;
}
if (SEGAE_SLICE() != 0)
return;
if (sline <= 192) {
segae_latch_hscroll();
if (sline != 192) segae_drawscanline(sline,1,1);
if (sline == 192)
vintpending = 1;
if (hintcount == 0) {
hintcount = segae_vdp_regs[1][10];
hintpending = 1;
if ((segae_vdp_regs[1][0] & 0x10)) {
cpu_set_irq_line(0, 0, HOLD_LINE);
return;
} else {
cpu_set_irq_line(0, 0, CLEAR_LINE);
for (chip = 0; chip < 2; chip++)
{
/* the line counter runs on the 192 active lines and the first line
of the bottom border, and is reloaded on all the other lines */
if (sline <= 192)
{
if (segae_vdp_linecount[chip] == 0)
{
segae_vdp_linecount[chip] = segae_vdp_regs[chip][10];
segae_vdp_hint[chip] = 1;
if (chip == 1 && (segae_vdp_regs[1][0] & 0x10))
cpu_set_irq_line(0, 0, ASSERT_LINE);
}
} else {
hintcount--;
else
segae_vdp_linecount[chip]--;
}
}
else
segae_vdp_linecount[chip] = segae_vdp_regs[chip][10];
if (sline > 192) {
hintcount = segae_vdp_regs[1][10];
if ( (sline<0xe0) && (vintpending) ) {
if (segae_vdp_regs[1][0x1]&0x20) {
cpu_set_irq_line(0, 0, HOLD_LINE);
} else {
cpu_set_irq_line(0, 0, CLEAR_LINE);
}
/* the frame interrupt fires at the end of the first line of the bottom border */
if (sline == 193)
{
segae_vdp_status[chip] |= 0x80;
if (chip == 1 && (segae_vdp_regs[1][1] & 0x20))
cpu_set_irq_line(0, 0, ASSERT_LINE);
}
}
}
@@ -986,7 +1186,7 @@ INPUT_PORTS_END
static struct SN76496interface sn76489_intf =
{
2, /* 2 chips */
{ 4000000, 4000000 }, /* 4 MHz? (guess) */
{ 10738635/3, 10738635/3 }, /* the PSGs are in the VDPs: VDP clock / 3, as in MAME */
{ 50, 50 }
};
@@ -994,10 +1194,11 @@ static struct SN76496interface sn76489_intf =
static MACHINE_DRIVER_START( segae )
/* basic machine hardware */
MDRV_CPU_ADD(Z80,10738600/2) /* correct for hangonjr, and astroflash/transformer at least */
MDRV_CPU_ADD_TAG("main",Z80,10738600/2) /* correct for hangonjr, and astroflash/transformer at least */
MDRV_CPU_MEMORY(segae_readmem,segae_writemem)
MDRV_CPU_PORTS(segae_readport,segae_writeport)
MDRV_CPU_VBLANK_INT(segae_interrupt,262)
MDRV_CPU_VBLANK_INT(segae_interrupt,262*SEGAE_SLICES)
MDRV_MACHINE_INIT(segae)
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
@@ -1015,13 +1216,21 @@ static MACHINE_DRIVER_START( segae )
MDRV_SOUND_ADD(SN76496, sn76489_intf)
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( segae_mc8123 )
MDRV_IMPORT_FROM( segae )
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(segae_mc8123_readmem,segae_writemem)
MDRV_MACHINE_INIT( segae_mc8123 )
MACHINE_DRIVER_END
static MACHINE_DRIVER_START( megrescu )
/* basic machine hardware */
MDRV_CPU_ADD(Z80,10738600/2) /* correct for hangonjr, and astroflash/transformer at least */
MDRV_CPU_MEMORY(segae_readmem,segae_writemem)
MDRV_CPU_PORTS(segae_readport,segae_writeport)
MDRV_CPU_VBLANK_INT(segae_interrupt,262)
MDRV_CPU_VBLANK_INT(segae_interrupt,262*SEGAE_SLICES)
MDRV_MACHINE_INIT(segae)
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
@@ -1048,8 +1257,9 @@ MACHINE_DRIVER_END
static DRIVER_INIT( segasyse )
{
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "8000 Write Bank", &segae_8000bank, 1);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "Vertical Int Pending", &vintpending, 1);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "Line Int Pending", &hintpending, 1);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "VDP Status", segae_vdp_status, 2);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "VDP Line Int", segae_vdp_hint, 2);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "VDP Line Counter", segae_vdp_linecount, 2);
state_save_register_UINT8 ( "SEGASYSE-MAIN", 0, "Main Rom Bank", &rombank, 1);
state_save_register_func_postload(segae_bankswitch);
}
@@ -1076,9 +1286,46 @@ static DRIVER_INIT( ridleofp )
install_port_read_handler (0, 0xf8, 0xf8, segae_ridleofp_port_f8_r);
install_port_write_handler(0, 0xfa, 0xfa, segae_ridleofp_port_fa_w);
state_save_register_int ( "SEGASYSE-ROP", 0, "port_to_read", &port_to_read);
state_save_register_int ( "SEGASYSE-ROP", 0, "last1", &last1);
state_save_register_int ( "SEGASYSE-ROP", 0, "last2", &last2);
state_save_register_int ( "SEGASYSE-ROP", 0, "diff1", &diff1);
state_save_register_int ( "SEGASYSE-ROP", 0, "diff2", &diff2);
init_segasyse();
}
static void segae_mc8123_init(int banked_encrypted)
{
UINT8 *rom = memory_region(REGION_CPU1);
int length = memory_region_length(REGION_CPU1);
const UINT8 *key = memory_region(REGION_USER1);
segae_decrypted = auto_malloc(length);
memcpy(segae_decrypted, rom, length);
/* fixed ROM, then the banked ROMs (0xc000-0xffff of the region is main RAM) */
mc8123_decode(rom, segae_decrypted, key, 0x0000, 0x8000);
if (banked_encrypted)
mc8123_decode(rom, segae_decrypted, key, 0x10000, length);
segae_banked_encrypted = banked_encrypted;
segae_rombank_mask = 0x0f;
init_segasyse();
state_save_register_func_postload(segae_mc8123_refresh);
}
static DRIVER_INIT( opaopa )
{
segae_mc8123_init(1);
}
static DRIVER_INIT( fantzn2 )
{
segae_mc8123_init(0);
}
static DRIVER_INIT( astrofl )
{
astrofl_decode();
@@ -1095,13 +1342,10 @@ static DRIVER_INIT( astrofl )
ridleofp - Riddle of Pythagoras (Jp.)
transfrm - Transformer
astrofl - Astro Flash (Jp. Version of Transformer) (was encrypted)
opaopa - Opa Opa (Rev A, unprotected)
opaopan - Opa Opa (Rev A, unprotected)
slapshtr - Slap Shooter
NOT DECRYPTED
fantzn2 - Fantasy Zone 2 (set 2) *Rom at IC7 Encrypted*
opaopa - Opa Opa *Roms Encrypted/Bad?*
opaopa - Opa Opa (MC-8123 317-0042, fixed and banked ROMs encrypted)
fantzn2 - Fantasy Zone II (MC-8123 317-0057, fixed ROM at IC7 encrypted)
*******************************************************************************/
ROM_START( hangonjr )
@@ -1192,8 +1436,6 @@ ROM_START( megrescu )
ROM_LOAD( "v10_30ic.2", 0x28000, 0x08000, CRC(5b74c767) SHA1(dbc82a4e046f01130c72bbd7a81190d7f0ca209c) )
ROM_END
/* Not Working */
ROM_START( opaopa )
ROM_REGION( 0x50000, REGION_CPU1, 0 )
ROM_LOAD( "epr-11054.ic7", 0x00000, 0x08000, CRC(024b1244) SHA1(59a522ac3d98982cc4ddb1c81f9584d3da453649) ) /* encrypted */
@@ -1210,11 +1452,16 @@ ROM_END
ROM_START( fantzn2 )
ROM_REGION( 0x50000, REGION_CPU1, 0 )
ROM_LOAD( "fz2_ic7.rom", 0x00000, 0x08000, CRC(76db7b7b) SHA1(d60e2961fc893dcb4445aed5f67515cbd25b610f) )
ROM_LOAD( "fz2_ic5.rom", 0x10000, 0x10000, CRC(57b45681) SHA1(1ae6d0d58352e246a4ec4e1ce02b0417257d5d20) )
ROM_LOAD( "fz2_ic4.rom", 0x20000, 0x10000, CRC(6f7a9f5f) SHA1(b53aa2eded781c80466a79b7d81383b9a875d0be) )
ROM_LOAD( "fz2_ic3.rom", 0x30000, 0x10000, CRC(a231dc85) SHA1(45b94fdbde28c02e88546178ef3e8f9f3a96ab86) )
ROM_LOAD( "fz2_ic2.rom", 0x40000, 0x10000, CRC(b14db5af) SHA1(04c7fb659385438b3d8f9fb66800eb7b6373bda9) )
ROM_LOAD( "epr-11416.ic7", 0x00000, 0x08000, CRC(76db7b7b) SHA1(d60e2961fc893dcb4445aed5f67515cbd25b610f) ) /* encrypted */
/* The following are 16 0x4000 banks that get mapped to reads from 0x8000 - 0xbfff */
ROM_LOAD( "epr-11415.ic5", 0x10000, 0x10000, CRC(57b45681) SHA1(1ae6d0d58352e246a4ec4e1ce02b0417257d5d20) )
ROM_LOAD( "epr-11413.ic3", 0x20000, 0x10000, CRC(a231dc85) SHA1(45b94fdbde28c02e88546178ef3e8f9f3a96ab86) )
ROM_LOAD( "epr-11414.ic4", 0x30000, 0x10000, CRC(6f7a9f5f) SHA1(b53aa2eded781c80466a79b7d81383b9a875d0be) )
ROM_LOAD( "epr-11412.ic2", 0x40000, 0x10000, CRC(b14db5af) SHA1(04c7fb659385438b3d8f9fb66800eb7b6373bda9) )
ROM_REGION( 0x2000, REGION_USER1, 0 ) /* MC8123 key */
ROM_LOAD( "317-0057.key", 0x0000, 0x2000, CRC(ee43d0f0) SHA1(72cb75a4d8352fe372db12046a59ea044360d5c3) )
ROM_END
@@ -1230,6 +1477,5 @@ GAME( 1987, megrescu, 0, megrescu, megrescu, ridleofp, ROT90, "Sega / Exa
GAME( 1987, opaopan, opaopa, segae, opaopa, segasyse, ROT0, "Sega", "Opa Opa (Rev A, unprotected)" )
GAME( 1988, tetrisse, 0, segae, tetrisse, segasyse, ROT0, "Sega", "Tetris (Japan, System E)" )
/* Not Working */
GAMEX(198?, fantzn2, 0, segae, dummy, segasyse, ROT0, "????", "Fantasy Zone 2", GAME_NOT_WORKING ) /* encrypted */
GAMEX(1987, opaopa, 0, segae, opaopa, segasyse, ROT0, "Sega", "Opa Opa (MC-8123, 317-0042)", GAME_NOT_WORKING ) /* encrypted */
GAME( 1987, opaopa, 0, segae_mc8123, opaopa, opaopa, ROT0, "Sega", "Opa Opa (MC-8123, 317-0042)" )
GAME( 1988, fantzn2, 0, segae_mc8123, fantzn2, fantzn2, ROT0, "Sega", "Fantasy Zone II - The Tears of Opa-Opa (MC-8123, 317-0057)" )
src/drivers/sharrier.c
+1457 -490
View File
File diff suppressed because it is too large. Load diff
src/drivers/skydiver.c
+4 -4
View File
@@ -319,11 +319,11 @@ INPUT_PORTS_START( skydiver )
PORT_BIT (0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT (0x40, IP_ACTIVE_LOW, IPT_TILT )
PORT_BIT (0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START
PORT_ADJUSTER( 67, "Whistle 1 Freq" )
PORT_START /* 14, read by the whistle 2 circuit (R65) */
PORT_ADJUSTER( 67, "Whistle 2 Freq" )
PORT_START
PORT_ADJUSTER( 75, "Whistle 2 Freq" )
PORT_START /* 15, read by the whistle 1 circuit (R66) */
PORT_ADJUSTER( 75, "Whistle 1 Freq" )
INPUT_PORTS_END
src/drivers/snk.c
+20
View File
@@ -216,6 +216,7 @@ Credits (in alphabetical order)
***************************************************************************/
#include "driver.h"
#include "state.h"
#include "vidhrdw/generic.h"
#include "cpu/z80/z80.h"
#include "snk.h"
@@ -289,6 +290,14 @@ static int hard_flags;
*/
static int snk_sound_register;
/* the sound handshake register is part of the save state (the sound CPU
went another way after loading a state in a new instance) */
static MACHINE_INIT( snk )
{
snk_sound_register = 0;
state_save_register_int("snk", 0, "sound_register", &snk_sound_register);
}
/*********************************************************************/
static int snk_rot8( int which ){
@@ -1058,6 +1067,7 @@ static MACHINE_DRIVER_START( tnk3 )
MDRV_PALETTE_INIT(aso)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(tnk3)
/* sound hardware */
@@ -1094,6 +1104,7 @@ static MACHINE_DRIVER_START( athena )
MDRV_PALETTE_INIT(aso)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(tnk3)
/* sound hardware */
@@ -1130,6 +1141,7 @@ static MACHINE_DRIVER_START( ikari )
MDRV_PALETTE_INIT(snk_3bpp_shadow)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(ikari)
/* sound hardware */
@@ -1168,6 +1180,7 @@ static MACHINE_DRIVER_START( victroad )
MDRV_PALETTE_INIT(snk_3bpp_shadow)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(ikari)
/* sound hardware */
@@ -1205,6 +1218,7 @@ static MACHINE_DRIVER_START( gwar )
MDRV_PALETTE_INIT(RRRR_GGGG_BBBB)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(gwar)
/* sound hardware */
@@ -1243,6 +1257,7 @@ static MACHINE_DRIVER_START( bermudat )
MDRV_PALETTE_INIT(RRRR_GGGG_BBBB)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(gwar)
/* sound hardware */
@@ -1280,6 +1295,7 @@ static MACHINE_DRIVER_START( psychos )
MDRV_PALETTE_INIT(RRRR_GGGG_BBBB)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(gwar)
/* sound hardware */
@@ -1317,6 +1333,7 @@ static MACHINE_DRIVER_START( chopper1 )
MDRV_PALETTE_INIT(RRRR_GGGG_BBBB)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(gwar)
/* sound hardware */
@@ -1354,6 +1371,7 @@ static MACHINE_DRIVER_START( tdfever )
MDRV_PALETTE_INIT(snk_4bpp_shadow)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(tdfever)
/* sound hardware */
@@ -1391,6 +1409,7 @@ static MACHINE_DRIVER_START( tdfever2 )
MDRV_PALETTE_INIT(snk_4bpp_shadow)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(tdfever)
/* sound hardware */
@@ -1428,6 +1447,7 @@ static MACHINE_DRIVER_START( ftsoccer )
MDRV_PALETTE_INIT(snk_4bpp_shadow)
MDRV_VIDEO_START(snk)
MDRV_MACHINE_INIT(snk)
MDRV_VIDEO_UPDATE(tdfever)
/* sound hardware */
src/drivers/stv.c
+2180 -1155
View File
File diff suppressed because it is too large. Load diff
src/drivers/stvhacks.c
+17 -41
View File
@@ -9,58 +9,34 @@ to be honest i think some of these cause more problems than they're worth ...
extern data32_t *stv_workram_h;
DRIVER_INIT ( stv );
/* Hack the boot vectors .. not right but allows several IC13 games (which fail the checksums before hacking) to boot */
/* the IC13 carts: their program ROM is now loaded as MAME loads it (odd
bytes, mirrored), so they need no boot vector patch */
DRIVER_INIT( ic13 )
{
/* this is WRONG but works for some games */
data32_t *rom = (data32_t *)memory_region(REGION_USER1);
rom[0xf10/4] = (rom[0xf10/4] & 0xff000000)|((rom[0xf10/4]/2)&0x00ffffff);
rom[0xf20/4] = (rom[0xf20/4] & 0xff000000)|((rom[0xf20/4]/2)&0x00ffffff);
rom[0xf30/4] = (rom[0xf30/4] & 0xff000000)|((rom[0xf30/4]/2)&0x00ffffff);
init_stv();
}
/*
06013AE8: MOV.L @($D4,PC),R5
06013AEA: MOV.L @($D8,PC),R0
06013AEC: MOV.W @R5,R5
06013AEE: MOV.L @R0,R0
06013AF0: AND R10,R5
06013AF2: TST R0,R0
06013AF4: BTS $06013B00
06013AF6: EXTS.W R5,R5
06013B00: EXTS.W R5,R5
06013B02: TST R5,R5
06013B04: BF $06013B0A
06013B06: TST R4,R4
06013B08: BT $06013AE8
(loops for 375868 instructions)
Super Major League / Final Arch: each frame the master queues a job for the slave
(the depth sort of the polygons), waits for the slave to take it (the read pointer
at 060ffc44) and then clears the "sort done" flag that the slave sets when the job
is over. The slave is much slower than the master on the real hardware, but in
coarse time slices it can take the job and finish it before the master looks at the
pointer again, so the flag is lost and the game hangs. A tight interleave while the
master polls keeps the order of the real hardware.
*/
READ32_HANDLER( stv_speedup_r )
static READ32_HANDLER( smleague_sync_r )
{
if (activecpu_get_pc()==0x60154b4) cpu_spinuntil_int(); /* bios menus..*/
return stv_workram_h[0x0335d0/4];
/* a slice of 16 SH-2 cycles is enough (a perfect one costs half the speed);
with 64 cycles Super Major League and Final Arch hang again */
cpu_boost_interleave(TIME_IN_HZ(57272720/32), TIME_IN_USEC(20));
return stv_workram_h[0x0ffc44/4];
}
READ32_HANDLER( stv_speedup2_r )
DRIVER_INIT( smleague )
{
if (activecpu_get_pc()==0x6013af0) cpu_spinuntil_int(); /* for use in japan*/
return stv_workram_h[0x0335bc/4];
}
void install_stvbios_speedups(void)
{
/* idle skip bios? .. not 100% sure this is safe .. we'll see */
install_mem_read32_handler(0, 0x60335d0, 0x60335d3, stv_speedup_r );
install_mem_read32_handler(0, 0x60335bc, 0x60335bf, stv_speedup2_r );
install_mem_read32_handler(0, 0x060ffc44, 0x060ffc47, smleague_sync_r);
init_stv();
}
static READ32_HANDLER( shienryu_slave_speedup_r )
src/drivers/system16.c
+173 -89
View File
@@ -151,6 +151,8 @@ Notes:
#include "cpu/i8039/i8039.h"
#include "system16.h"
#include "machine/fd1089.h"
#include "machine/fd1094.h"
#include "state.h"
#include "ost_samples.h"
extern void mc8123_decrypt_0066(void);
@@ -3060,6 +3062,9 @@ ROM_START( goldnaxj )
ROM_LOAD16_BYTE( "epr12521.a8", 0x80000, 0x20000, CRC(5001d713) SHA1(68cf3f48d6e440e5b800503a211adda02107d956) )
ROM_LOAD16_BYTE( "epr12519.a6", 0x80001, 0x20000, CRC(4438ca8e) SHA1(0af53d64f06abf41f4c46540d28d5f008a4835a3) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* FD1094 decryption key */
ROM_LOAD( "317-0121.key", 0x0000, 0x2000, CRC(72afed01) SHA1(3967390fde63fa5961e71ab49b6e71c4be2ac96f) )
ROM_REGION( 0x60000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
ROM_LOAD( "epr12385", 0x00000, 0x20000, CRC(b8a4e7e0) SHA1(9b36f50209d45a835ded53eb045f63c649b02fc9) )
ROM_LOAD( "epr12386", 0x20000, 0x20000, CRC(25d7d779) SHA1(2de14a76a5176d5abc7e7f7f723146c620927610) )
@@ -3174,7 +3179,7 @@ static MEMORY_WRITE16_START( goldnaxe_writemem )
{ 0x1f0000, 0x1f0003, SYS16_MWA16_EXTRAM, &sys16_extraram },
{ 0x200000, 0x200fff, SYS16_MWA16_SPRITERAM, &sys16_spriteram },
{ 0xc40000, 0xc40001, sys16_coinctrl_w },
{ 0xc43000, 0xc43001, MWA16_NOP }, /* ? */
{ 0xc43000, 0xc43fff, MWA16_NOP }, /* ? */
/* { 0xfe0006, 0xfe0007, MWA16_NOP }, I think this is the real sound out */
{ 0xffec1c, 0xffec1d, goldnaxe_prot_w },/* how does this really work? */
{ 0xffecfc, 0xffecfd, ga_sound_command_w },/* probably just a buffer */
@@ -3289,6 +3294,9 @@ ROM_START( goldnaxb )
ROM_LOAD16_BYTE( "epr12389.a2", 0x00000, 0x40000, CRC(35d5fa77) SHA1(b16b312eb1c91c412fee61002599812e30e321ee) )
ROM_LOAD16_BYTE( "epr12388.a1", 0x00001, 0x40000, CRC(72952a93) SHA1(b31888429ad81388a96333dc0b2c7e2223134834) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* FD1094 decryption key */
ROM_LOAD( "317-0110.key", 0x0000, 0x2000, CRC(cd517dc6) SHA1(db95adac8c089758832897854a9cb4d611974dee) )
ROM_REGION( 0x60000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
ROM_LOAD( "epr12385", 0x00000, 0x20000, CRC(b8a4e7e0) SHA1(9b36f50209d45a835ded53eb045f63c649b02fc9) )
ROM_LOAD( "epr12386", 0x20000, 0x20000, CRC(25d7d779) SHA1(2de14a76a5176d5abc7e7f7f723146c620927610) )
@@ -3313,6 +3321,9 @@ ROM_START( goldnaxc )
ROM_LOAD16_BYTE( "epr12543.a2", 0x00000, 0x40000, CRC(b0df9ca4) SHA1(240f3c2998f969569d992f796e006f5ea4434e55) )
ROM_LOAD16_BYTE( "epr12542.a1", 0x00001, 0x40000, CRC(b7994d3c) SHA1(87570f23826922fca465c69df6b892c59f14e103) )
ROM_REGION( 0x2000, REGION_USER2, 0 ) /* FD1094 decryption key */
ROM_LOAD( "317-0122.key", 0x0000, 0x2000, CRC(f123c2fb) SHA1(83463a6918afde0a6f7d919e00127ffdc563efd1) )
ROM_REGION( 0x60000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
ROM_LOAD( "epr12385", 0x00000, 0x20000, CRC(b8a4e7e0) SHA1(9b36f50209d45a835ded53eb045f63c649b02fc9) )
ROM_LOAD( "epr12386", 0x20000, 0x20000, CRC(25d7d779) SHA1(2de14a76a5176d5abc7e7f7f723146c620927610) )
@@ -3443,6 +3454,163 @@ static MACHINE_DRIVER_START( goldnaxa )
MDRV_MACHINE_INIT(goldnaxa)
MACHINE_DRIVER_END
/*
The FD1094 sets of the 171-5797 ROM board (goldnaxb, goldnaxc): no 8751,
the program reads the I/O and sends the sound commands itself, through
the 315-5195 memory mapper. Same memory map as goldnaxa, without the
handlers that stand in for the 8751 in the work RAM.
Every frame the program writes the mapper regions again from a table of
8 (0x36f6 in goldnaxb), which only differ in the base of the sprite RAM:
0x200000 to 0x900000 in turn, and the sprite list goes to the new base.
Writes that hit no device go to the mapper: register 3 is the sound
command, 0x19 the base of the sprite RAM (region 4).
*/
static UINT8 ga_mapper_regs[0x20];
static void ga_mapper_w( offs_t offset, data16_t data, data16_t mem_mask )
{
int reg = offset & 0x1f;
if( !ACCESSING_LSB )
return;
ga_mapper_regs[reg] = data & 0xff;
if( reg == 3 ){
soundlatch_w( 0, data & 0xff );
cpu_set_irq_line( 1, 0, HOLD_LINE );
}
}
static WRITE16_HANDLER( ga_fd1094_mapper_w )
{
ga_mapper_w( offset, data, mem_mask );
}
/* the sprite RAM (2KB, mirrored in its 64KB region) where the mapper puts it */
static int ga_sprite_window( offs_t address )
{
return ((address >> 16) & 0xff) == ga_mapper_regs[0x19];
}
static READ16_HANDLER( ga_fd1094_sprite_r )
{
offs_t address = 0x200000 + offset * 2;
if( ga_sprite_window( address ) )
return sys16_spriteram[(address & 0x7ff) / 2];
return 0xffff;
}
static WRITE16_HANDLER( ga_fd1094_sprite_w )
{
offs_t address = 0x200000 + offset * 2;
if( ga_sprite_window( address ) )
COMBINE_DATA( &sys16_spriteram[(address & 0x7ff) / 2] );
else
ga_mapper_w( offset, data, mem_mask );
}
static WRITE16_HANDLER( ga_fd1094_sprite2_w )
{
ga_fd1094_sprite_w( offset + 0x1000 / 2, data, mem_mask );
}
static MEMORY_READ16_START( goldnaxa_fd1094_readmem )
{ 0x000000, 0x07ffff, MRA16_ROM },
{ 0x100000, 0x10ffff, SYS16_MRA16_TILERAM },
{ 0x110000, 0x110fff, SYS16_MRA16_TEXTRAM },
{ 0x140000, 0x140fff, SYS16_MRA16_PALETTERAM },
{ 0x1e0008, 0x1e0009, ga_hardware_collision_r },
{ 0x1f0000, 0x1f0007, ga_hardware_multiplier_r },
{ 0x1f1008, 0x1f1009, ga_hardware_collision_r },
{ 0x1f2000, 0x1f2003, SYS16_MRA16_EXTRAM },
{ 0x200000, 0x9fffff, ga_fd1094_sprite_r },
{ 0xc41002, 0xc41003, input_port_0_word_r }, /* player1 */
{ 0xc41006, 0xc41007, input_port_1_word_r }, /* player2 */
{ 0xc41000, 0xc41001, input_port_2_word_r }, /* service */
{ 0xc42002, 0xc42003, input_port_3_word_r }, /* dip1 */
{ 0xc42000, 0xc42001, input_port_4_word_r }, /* dip2 */
{ 0xffc000, 0xffffff, SYS16_MRA16_WORKINGRAM },
MEMORY_END
static MEMORY_WRITE16_START( goldnaxa_fd1094_writemem )
{ 0x000000, 0x07ffff, MWA16_ROM },
{ 0x100000, 0x10ffff, SYS16_MWA16_TILERAM, &sys16_tileram },
{ 0x110000, 0x110fff, SYS16_MWA16_TEXTRAM, &sys16_textram },
{ 0x140000, 0x140fff, SYS16_MWA16_PALETTERAM, &paletteram16 },
{ 0x1e0000, 0x1e0009, ga_hardware_collision_w },
{ 0x1f0000, 0x1f0003, ga_hardware_multiplier_w },
{ 0x1f1000, 0x1f1009, ga_hardware_collision_w },
{ 0x1f2000, 0x1f2003, SYS16_MWA16_EXTRAM, &sys16_extraram },
{ 0x200000, 0x200fff, ga_fd1094_sprite_w, &sys16_spriteram },
{ 0x201000, 0x9fffff, ga_fd1094_sprite2_w },
{ 0xc40000, 0xc40001, sys16_coinctrl_w },
{ 0xc43000, 0xc43fff, MWA16_NOP },
{ 0xfe0000, 0xfeffff, ga_fd1094_mapper_w },
{ 0xffc000, 0xffffff, SYS16_MWA16_WORKINGRAM, &sys16_workingram },
MEMORY_END
static MACHINE_INIT( goldnaxa_fd1094 ){
static int bank[16] = {
0,1,4,5,
8,9,0,0,
2,3,6,7,
10,11,0,0
};
sys16_obj_bank = bank;
/* the tile banks: the program keeps them in the work RAM, as goldnaxa */
sys16_update_proc = goldnaxe_update_proc;
memset(ga_mapper_regs, 0, sizeof(ga_mapper_regs));
ga_mapper_regs[0x19] = 0x20;
fd1094_machine_init();
}
static DRIVER_INIT( goldnaxa_fd1094 ){
fd1094_driver_init(0, REGION_USER2);
state_save_register_UINT8("goldnaxa_fd1094", 0, "mapper", ga_mapper_regs, 0x20);
}
static MACHINE_DRIVER_START( goldnaxa_fd1094 )
MDRV_IMPORT_FROM(goldnaxa)
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(goldnaxa_fd1094_readmem,goldnaxa_fd1094_writemem)
MDRV_MACHINE_INIT(goldnaxa_fd1094)
MACHINE_DRIVER_END
/* goldnaxj: the FD1094 set of the 171-5704 ROM board, the memory map of goldnaxe */
static MEMORY_READ16_START( goldnaxe_fd1094_readmem )
{ 0x000000, 0x0bffff, MRA16_ROM },
{ 0x100000, 0x10ffff, SYS16_MRA16_TILERAM },
{ 0x110000, 0x110fff, SYS16_MRA16_TEXTRAM },
{ 0x140000, 0x140fff, SYS16_MRA16_PALETTERAM },
{ 0x1f0000, 0x1f0003, SYS16_MRA16_EXTRAM },
{ 0x200000, 0x9fffff, ga_fd1094_sprite_r },
{ 0xc41002, 0xc41003, input_port_0_word_r }, /* player1 */
{ 0xc41006, 0xc41007, input_port_1_word_r }, /* player2 */
{ 0xc41000, 0xc41001, input_port_2_word_r }, /* service */
{ 0xc42002, 0xc42003, input_port_3_word_r }, /* dip1 */
{ 0xc42000, 0xc42001, input_port_4_word_r }, /* dip2 */
{ 0xffc000, 0xffffff, SYS16_MRA16_WORKINGRAM },
MEMORY_END
static MEMORY_WRITE16_START( goldnaxe_fd1094_writemem )
{ 0x000000, 0x0bffff, MWA16_ROM },
{ 0x100000, 0x10ffff, SYS16_MWA16_TILERAM, &sys16_tileram },
{ 0x110000, 0x110fff, SYS16_MWA16_TEXTRAM, &sys16_textram },
{ 0x140000, 0x140fff, SYS16_MWA16_PALETTERAM, &paletteram16 },
{ 0x1f0000, 0x1f0003, SYS16_MWA16_EXTRAM, &sys16_extraram },
{ 0x200000, 0x200fff, ga_fd1094_sprite_w, &sys16_spriteram },
{ 0x201000, 0x9fffff, ga_fd1094_sprite2_w },
{ 0xc40000, 0xc40001, sys16_coinctrl_w },
{ 0xc43000, 0xc43fff, MWA16_NOP },
{ 0xfe0000, 0xfeffff, ga_fd1094_mapper_w },
{ 0xffc000, 0xffffff, SYS16_MWA16_WORKINGRAM, &sys16_workingram },
MEMORY_END
static MACHINE_DRIVER_START( goldnaxe_fd1094 )
MDRV_IMPORT_FROM(goldnaxe)
MDRV_CPU_MODIFY("main")
MDRV_CPU_MEMORY(goldnaxe_fd1094_readmem,goldnaxe_fd1094_writemem)
MDRV_MACHINE_INIT(goldnaxa_fd1094)
MACHINE_DRIVER_END
/***************************************************************************/
/* sys16B */
ROM_START( hwchamp )
@@ -5124,7 +5292,7 @@ static MEMORY_WRITE16_START( shinobi_writemem )
{ 0x440000, 0x440fff, SYS16_MWA16_SPRITERAM, &sys16_spriteram },
{ 0x840000, 0x840fff, SYS16_MWA16_PALETTERAM, &paletteram16 },
{ 0xc40000, 0xc40001, sys16_coinctrl_w },
{ 0xc43000, 0xc43001, MWA16_NOP },
{ 0xc43000, 0xc43fff, MWA16_NOP },
{ 0xfe0006, 0xfe0007, sound_command_w },
{ 0xffc000, 0xffffff, SYS16_MWA16_WORKINGRAM, &sys16_workingram },
MEMORY_END
@@ -6683,88 +6851,6 @@ static MACHINE_DRIVER_START( s16dummy )
MDRV_MACHINE_INIT(sys16_dummy)
MACHINE_DRIVER_END
/*****************************************************************************/
/* Cotton */
ROM_START( cotton )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
/* custom cpu 317-????? */
ROM_LOAD16_BYTE( "epr13858.a7", 0x000000, 0x20000, CRC(276f42fe) SHA1(47d2f910f6f101628cb0c660e5fd12c0e331bd99) )
ROM_LOAD16_BYTE( "epr13856.a5", 0x000001, 0x20000, CRC(14e6b5e7) SHA1(708c69cddd1c60e729a74f539d40e67b2a6d9d6f) )
ROM_LOAD16_BYTE( "epr13859.a8", 0x040000, 0x20000, CRC(4703ef9d) SHA1(8b03a71736a599c337ad5d95cbc812ea38b0cc43) )
ROM_LOAD16_BYTE( "epr13857.a6", 0x040001, 0x20000, CRC(de37e527) SHA1(124ce7c7eef1199c89735556cebf71255573a155) )
ROM_REGION( 0xc0000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
ROM_LOAD( "scr01.rom", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "scr11.rom", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "scr02.rom", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "scr12.rom", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "scr03.rom", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "scr13.rom", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "obj0-e.rom", 0x000001, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "obj0-o.rom", 0x000000, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "obj1-e.rom", 0x040001, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "obj1-o.rom", 0x040000, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "obj2-e.rom", 0x080001, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "obj2-o.rom", 0x080000, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "obj3-e.rom", 0x0c0001, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "obj3-o.rom", 0x0c0000, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "obj4-e.rom", 0x100001, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "obj4-o.rom", 0x100000, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "obj5-e.rom", 0x140001, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "obj5-o.rom", 0x140000, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "obj6-e.rom", 0x180001, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "obj6-o.rom", 0x180000, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "obj7-e.rom", 0x1c0001, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "obj7-o.rom", 0x1c0000, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x30000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "s-prog.rom", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "speech0.rom", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_END
ROM_START( cottona )
ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
/* custom cpu 317-0181a */
ROM_LOAD16_BYTE( "ep13921a.a7", 0x000000, 0x20000, CRC(f047a037) SHA1(e4a9eeb1f2cf6b5ee3b2fcf74be917ffd3e6ca0e) )
ROM_LOAD16_BYTE( "ep13919a.a5", 0x000001, 0x20000, CRC(651108b1) SHA1(1ab32085ca1a8cb3d464059b0abb10253decd423) )
ROM_LOAD16_BYTE( "ep13922a.a8", 0x040000, 0x20000, CRC(1ca248c5) SHA1(f7df2ccf54a3f1f09334c3b3df3dcd2ec33f99d1) )
ROM_LOAD16_BYTE( "ep13920a.a6", 0x040001, 0x20000, CRC(fa3610f9) SHA1(6127496bf7cd47d4343291fc2e11673d77ccc550) )
ROM_REGION( 0xc0000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
ROM_LOAD( "scr01.rom", 0x00000, 0x20000, CRC(a47354b6) SHA1(ce52813b245f1d491a134d4bd5ab074e71d20129) )
ROM_LOAD( "scr11.rom", 0x20000, 0x20000, CRC(d38424b5) SHA1(884ca190936aee2d2cac86491d4d0cdf4a45efe5) )
ROM_LOAD( "scr02.rom", 0x40000, 0x20000, CRC(8c990026) SHA1(07b4510936376c171f3b31d87ac6154361eb0cbc) )
ROM_LOAD( "scr12.rom", 0x60000, 0x20000, CRC(21c15b8a) SHA1(690d92420ec5465885e0f4870419992961420e33) )
ROM_LOAD( "scr03.rom", 0x80000, 0x20000, CRC(d2b175bf) SHA1(897b7c794d0e7229ea5e9a682f64266a947a818f) )
ROM_LOAD( "scr13.rom", 0xa0000, 0x20000, CRC(b9d62531) SHA1(e8c5e7b93339c00f75a3b66ce18f7838255577be) )
ROM_REGION( 0x200000, REGION_GFX2, 0 ) /* sprites */
ROM_LOAD16_BYTE( "obj0-e.rom", 0x000001, 0x20000, CRC(ab4b3468) SHA1(3071654a295152d609d2c2c1d4153b5ba3f174d5) )
ROM_LOAD16_BYTE( "obj0-o.rom", 0x000000, 0x20000, CRC(7024f404) SHA1(4b2f9cdfdd97218797a3e386106e53f713b8650d) )
ROM_LOAD16_BYTE( "obj1-e.rom", 0x040001, 0x20000, CRC(69b41ac3) SHA1(4c5a85e5a5ca9f8260557d4e97eb091dd857d63a) )
ROM_LOAD16_BYTE( "obj1-o.rom", 0x040000, 0x20000, CRC(6169bba4) SHA1(a24a418ee7cd0c1109870a2e7a91e430671897ed) )
ROM_LOAD16_BYTE( "obj2-e.rom", 0x080001, 0x20000, CRC(0801cf02) SHA1(3007bbbce2f327f4700e78e2b8672f4482189cd7) )
ROM_LOAD16_BYTE( "obj2-o.rom", 0x080000, 0x20000, CRC(b014f02d) SHA1(46f5ed0b44cee03a6aec9ec57b506bb15bf35e47) )
ROM_LOAD16_BYTE( "obj3-e.rom", 0x0c0001, 0x20000, CRC(f066f315) SHA1(bbeb24daaded994240d0cdb5cec2e662b677cb75) )
ROM_LOAD16_BYTE( "obj3-o.rom", 0x0c0000, 0x20000, CRC(e62a7cd6) SHA1(1e6d06345f7b6cef2e887d9b9cd45e0155140c5e) )
ROM_LOAD16_BYTE( "obj4-e.rom", 0x100001, 0x20000, CRC(1bd145f3) SHA1(4744ffe9fbda453785345b46eb61b56730048f42) )
ROM_LOAD16_BYTE( "obj4-o.rom", 0x100000, 0x20000, CRC(943aba8b) SHA1(d0dd1665a8d9495a92ae4e35d6b15b966e8d43cd) )
ROM_LOAD16_BYTE( "obj5-e.rom", 0x140001, 0x20000, CRC(4fd59bff) SHA1(2b4630e49b60593d668fe34d8faf712ac6928c14) )
ROM_LOAD16_BYTE( "obj5-o.rom", 0x140000, 0x20000, CRC(7ea93200) SHA1(8e2d8cd48a12306772653f25bddc99ad0597a698) )
ROM_LOAD16_BYTE( "obj6-e.rom", 0x180001, 0x20000, CRC(6a66868d) SHA1(60961a8b1f193d0b08c1906f4a79123fa0db443a) )
ROM_LOAD16_BYTE( "obj6-o.rom", 0x180000, 0x20000, CRC(1c942190) SHA1(514fac5cc7362e9e3168c84975c8fe0e34bb4471) )
ROM_LOAD16_BYTE( "obj7-e.rom", 0x1c0001, 0x20000, CRC(1c5ffad8) SHA1(13e5886ceece564cc71ba7f43a26d2b1782ccfc8) )
ROM_LOAD16_BYTE( "obj7-o.rom", 0x1c0000, 0x20000, CRC(856f3ee2) SHA1(72346d887ff9738ebe93acb2e3f8cd80d494621e) )
ROM_REGION( 0x30000, REGION_CPU2, 0 ) /* sound CPU */
ROM_LOAD( "s-prog.rom", 0x00000, 0x08000, CRC(6a57b027) SHA1(8f9de548df203605bb4ab9eececf09739b55adf1) )
ROM_LOAD( "speech0.rom", 0x10000, 0x20000, CRC(4d21153f) SHA1(173ddd9633f255c39ca508c37d0562e374704e7b) )
ROM_END
/*****************************************************************************/
/* MVP */
@@ -6978,8 +7064,6 @@ GAMEX(1989, bayrtbl1, bayroute, bayroute, bayroute, bayrtbl1, ROT0, "bootleg"
GAMEX(1989, bayrtbl2, bayroute, bayroute, bayroute, bayrtbl1, ROT0, "bootleg", "Bay Route (bootleg set 2)", GAME_NOT_WORKING )
/* Bullet */
/* Charon */
GAMEX(19??, cotton, 0, s16dummy, s16dummy, 0, ROT0, "Sega", "Cotton (Japan)", GAME_NOT_WORKING )
GAMEX(19??, cottona, cotton, s16dummy, s16dummy, 0, ROT0, "Sega", "Cotton", GAME_NOT_WORKING )
GAME( 1989, dduxbl, 0, dduxbl, dduxbl, dduxbl, ROT0, "bootleg", "Dynamite Dux (bootleg)" )
GAMEX(1989, eswat, 0, eswat, eswat, eswat, ROT0, "Sega", "E-Swat - Cyber Police", GAME_NOT_WORKING )
GAME( 1989, eswatbl, eswat, eswat, eswat, eswat, ROT0, "bootleg", "E-Swat - Cyber Police (bootleg)" )
@@ -6990,11 +7074,11 @@ GAME( 1989, fpointbl, fpoint, fpointbl, fpoint, fpointbl, ROT0, "bootleg"
GAME( 1989, fpointbj, fpoint, fpointbl, fpointbj, fpointbl, ROT0, "bootleg", "Flash Point (Japan, bootleg)" )
GAME( 1989, goldnaxe, 0, goldnaxe, goldnaxe, 0, ROT0, "Sega", "Golden Axe (Version 1)" )
GAMEX(1989, goldnaxj, goldnaxe, goldnaxe, goldnaxe, 0, ROT0, "Sega", "Golden Axe (Version 1, Japan)", GAME_NOT_WORKING )
GAME( 1989, goldnaxj, goldnaxe, goldnaxe_fd1094, goldnaxe, goldnaxa_fd1094, ROT0, "Sega", "Golden Axe (set 4, Japan) (FD1094 317-0121)" )
GAMEX(1989, goldnabl, goldnaxe, goldnaxe, goldnaxe, goldnabl, ROT0, "bootleg", "Golden Axe (bootleg)", GAME_NOT_WORKING )
GAME( 1989, goldnaxa, goldnaxe, goldnaxa, goldnaxe, 0, ROT0, "Sega", "Golden Axe (set 6, US) (8751 317-123A)" )
GAMEX(1989, goldnaxb, goldnaxe, goldnaxa, goldnaxe, 0, ROT0, "Sega", "Golden Axe (Version 2 317-0110)", GAME_NOT_WORKING )
GAMEX(1989, goldnaxc, goldnaxe, goldnaxa, goldnaxe, 0, ROT0, "Sega", "Golden Axe (Version 2 317-0122)", GAME_NOT_WORKING )
GAME( 1989, goldnaxb, goldnaxe, goldnaxa_fd1094, goldnaxe, goldnaxa_fd1094, ROT0, "Sega", "Golden Axe (set 1, World) (FD1094 317-0110)" )
GAME( 1989, goldnaxc, goldnaxe, goldnaxa_fd1094, goldnaxe, goldnaxa_fd1094, ROT0, "Sega", "Golden Axe (set 5, US) (FD1094 317-0122)" )
GAME( 1987, hwchamp, 0, hwchamp, hwchamp, 0, ROT0, "Sega", "Heavyweight Champ" )
GAMEX(19??, mvp, 0, s16dummy, s16dummy, 0, ROT0, "Sega", "MVP", GAME_NOT_WORKING )
GAMEX(1988, passsht, 0, passsht, passsht, 0, ROT270, "Sega", "Passing Shot (2 Players)", GAME_NOT_WORKING )
src/drivers/system18.c
+2587 -543
View File
File diff suppressed because it is too large. Load diff
src/drivers/tagteam.c
+1 -1
View File
@@ -296,7 +296,7 @@ static struct AY8910interface ay8910_interface =
static struct DACinterface dac_interface =
{
1,
{ 255 }
{ 25 }
};
static MACHINE_DRIVER_START( tagteam )
src/drivers/tourtabl.c
+1 -1
View File
@@ -106,7 +106,7 @@ static const struct R6532interface r6532_interface_1 =
static struct TIAinterface tia_interface =
{
31400, 255, TIA_DEFAULT_GAIN
31400, 25, TIA_DEFAULT_GAIN
};
src/drivers/tx1.c
+1531
View File
File diff suppressed because it is too large. Load diff
src/drivers/ultratnk.c
+2 -2
View File
@@ -408,10 +408,10 @@ INPUT_PORTS_START( ultratnk )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICKRIGHT_DOWN | IPF_PLAYER2 )
PORT_BIT( 0x50, IP_ACTIVE_HIGH, IPT_JOYSTICKRIGHT_UP | IPF_PLAYER2 ) /* note that this sets 2 bits */
PORT_START /* 5 */
PORT_ADJUSTER( 5, "Motor 1 RPM" )
PORT_ADJUSTER( 60, "Motor 1 RPM" )
PORT_START /* 6 */
PORT_ADJUSTER( 10, "Motor 2 RPM" )
PORT_ADJUSTER( 40, "Motor 2 RPM" )
INPUT_PORTS_END
src/drivers/zn.c
+8 -503
View File
@@ -155,6 +155,7 @@ Sound: Analog Devices ADSP-2181
#include "machine/intelfsh.h"
#include "machine/ataflash.h"
#include "cpu/adsp2100/adsp2100.h"
#include "sndhrdw/acclaim_rax.h"
static int zn_bank_secsel; /* the game ROM bank follows this register (Raizing) */
static UINT32 tecmo_bank;
@@ -2829,507 +2830,11 @@ MACHINE_DRIVER_END
read the ROM from the bank written in the high half (inverted bit 4),
and the backup RAM is still written there.
RAX sound board (MAME shared/rax.cpp): an ADSP-2181 at 16.67MHz with
8MB of ROM (two banks of 4MB) read by its byte DMA (BDMA), 4 banks of
8K words of external data RAM behind the data memory overlay, and two
DACs fed by SPORT0 in autobuffer mode. The main CPU writes 16-bit
commands to 0x1fbfff80; the ADSP reads them at I/O 3, which clears its
IRQL0.
RAX sound board: sndhrdw/acclaim_rax.c, 8MB of ROM (two banks of 4MB).
The main CPU writes its 16-bit commands to 0x1fbfff80.
***************************************************************************/
/* the ADSP-2181 control registers, data memory 0x3fe0-0x3fff */
enum
{
RAX_IDMA_CONTROL_REG = 0, /* 3fe0 */
RAX_BDMA_INT_ADDR_REG, /* 3fe1 */
RAX_BDMA_EXT_ADDR_REG, /* 3fe2 */
RAX_BDMA_CONTROL_REG, /* 3fe3 */
RAX_BDMA_WORD_COUNT_REG, /* 3fe4 */
RAX_PROG_FLAG_DATA_REG, /* 3fe5 */
RAX_PROG_FLAG_CONTROL_REG, /* 3fe6 */
RAX_S1_AUTOBUF_REG = 15, /* 3fef */
RAX_S1_RFSDIV_REG, /* 3ff0 */
RAX_S1_SCLKDIV_REG, /* 3ff1 */
RAX_S1_CONTROL_REG, /* 3ff2 */
RAX_S0_AUTOBUF_REG, /* 3ff3 */
RAX_S0_RFSDIV_REG, /* 3ff4 */
RAX_S0_SCLKDIV_REG, /* 3ff5 */
RAX_S0_CONTROL_REG, /* 3ff6 */
RAX_S0_MCTXLO_REG, /* 3ff7 */
RAX_S0_MCTXHI_REG, /* 3ff8 */
RAX_S0_MCRXLO_REG, /* 3ff9 */
RAX_S0_MCRXHI_REG, /* 3ffa */
RAX_TIMER_SCALE_REG, /* 3ffb */
RAX_TIMER_COUNT_REG, /* 3ffc */
RAX_TIMER_PERIOD_REG, /* 3ffd */
RAX_WAITSTATES_REG, /* 3ffe */
RAX_SYSCONTROL_REG /* 3fff */
};
#define RAX_CLOCK 16670000
#define RAX_BUFFER_SIZE 0x4000 /* DAC samples per channel */
#define RAX_BUFFER_MASK ( RAX_BUFFER_SIZE - 1 )
static int rax_cpunum;
static UINT8 *rax_rom;
static UINT16 *rax_banked_ram; /* 5 x 8K words: internal, then external 0-3 */
static UINT16 rax_control_regs[ 32 ];
static UINT16 rax_data_in;
static UINT16 rax_data_out;
static UINT8 rax_pf0;
static UINT16 rax_data_bank;
static UINT16 rax_rom_bank;
static UINT32 rax_dmovlay;
static UINT16 rax_size;
static UINT16 rax_incs;
static INT32 rax_ireg;
static UINT16 rax_ireg_base;
static UINT8 rax_dac_enabled[ 2 ];
/* the timers are not saved by the core: their time left is */
static void *rax_reg_timer;
static void *rax_dma_timer;
static double rax_reg_timer_period;
static double rax_reg_timer_left;
static double rax_dma_timer_left;
static UINT32 rax_dma_param;
/* the DACs */
static int rax_stream;
static INT16 *rax_buffer[ 2 ];
static UINT32 rax_buffer_in[ 2 ];
static UINT32 rax_buffer_out[ 2 ];
static UINT32 rax_sample_rate;
static UINT32 rax_sample_step;
static UINT32 rax_sample_position;
static void rax_update_data_ram_bank( void )
{
int n_entry = ( rax_dmovlay == 0 ) ? 0 : 1 + rax_data_bank;
cpu_setbank( 14, rax_banked_ram + n_entry * 0x2000 );
}
/* data memory as the ADSP sees it, outside its context (DMA, DACs) */
static UINT16 *rax_data_ptr( UINT32 n_addr )
{
n_addr &= 0x3fff;
if( n_addr < 0x2000 )
return rax_banked_ram + ( ( rax_dmovlay == 0 ) ? 0 : 1 + rax_data_bank ) * 0x2000 + n_addr;
if( n_addr < 0x3fe0 )
return (UINT16 *)( memory_region( REGION_CPU1 + rax_cpunum ) + ADSP2181_DATA_OFFSET + ( n_addr << 1 ) );
return NULL;
}
static void rax_dma_done( int param )
{
/* update the external address and the page */
rax_control_regs[ RAX_BDMA_WORD_COUNT_REG ] = 0;
rax_control_regs[ RAX_BDMA_EXT_ADDR_REG ] = param & 0x3fff;
rax_control_regs[ RAX_BDMA_CONTROL_REG ] &= ~0xff00;
rax_control_regs[ RAX_BDMA_CONTROL_REG ] |= ( ( param >> 14 ) & 0xff ) << 8;
if( rax_control_regs[ RAX_BDMA_CONTROL_REG ] & 8 )
cpu_set_reset_line( rax_cpunum, PULSE_LINE );
else
cpu_set_irq_line( rax_cpunum, ADSP2181_BDMA, PULSE_LINE );
timer_adjust( rax_dma_timer, TIME_NEVER, 0, 0 );
}
/* the byte DMA: from the ROM to program or data memory, at once; the end
(its interrupt, or the reset of a boot load) after a cycle per word */
static void rax_bdma( UINT32 n_count_reg )
{
const UINT8 *adsp_rom = rax_rom + ( rax_rom_bank & 1 ) * 0x400000;
UINT32 page = ( rax_control_regs[ RAX_BDMA_CONTROL_REG ] >> 8 ) & 0xff;
UINT32 dir = ( rax_control_regs[ RAX_BDMA_CONTROL_REG ] >> 2 ) & 1;
UINT32 type = rax_control_regs[ RAX_BDMA_CONTROL_REG ] & 3;
UINT32 src_addr = ( page << 14 ) | rax_control_regs[ RAX_BDMA_EXT_ADDR_REG ];
UINT32 count = rax_control_regs[ RAX_BDMA_WORD_COUNT_REG ];
if( !dir )
{
while( count )
{
UINT32 n_addr = rax_control_regs[ RAX_BDMA_INT_ADDR_REG ];
if( type == 0 )
{
/* 24-bit words to program memory */
UINT32 n_word = ( adsp_rom[ ( src_addr + 0 ) & 0x3fffff ] << 16 ) |
( adsp_rom[ ( src_addr + 1 ) & 0x3fffff ] << 8 ) | adsp_rom[ ( src_addr + 2 ) & 0x3fffff ];
UINT32 *pgm = (UINT32 *)( memory_region( REGION_CPU1 + rax_cpunum ) + ADSP2181_PGM_OFFSET );
pgm[ n_addr & 0x3fff ] = n_word;
src_addr += 3;
}
else
{
/* 16-bit words, or bytes (MSB or LSB aligned) to data memory */
UINT16 n_word;
UINT16 *p;
if( type == 1 )
{
n_word = ( adsp_rom[ src_addr & 0x3fffff ] << 8 ) | adsp_rom[ ( src_addr + 1 ) & 0x3fffff ];
src_addr += 2;
}
else
{
n_word = adsp_rom[ src_addr & 0x3fffff ] << ( ( type == 2 ) ? 8 : 0 );
src_addr++;
}
p = rax_data_ptr( n_addr );
if( p )
*p = n_word;
}
rax_control_regs[ RAX_BDMA_INT_ADDR_REG ] = ( n_addr + 1 ) & 0x3fff;
count--;
}
}
rax_dma_param = src_addr;
timer_adjust( rax_dma_timer, TIME_IN_HZ( RAX_CLOCK ) * ( n_count_reg & 0x3fff ), rax_dma_param, 0 );
}
static READ16_HANDLER( rax_control_r )
{
if( offset == RAX_PROG_FLAG_DATA_REG )
return rax_pf0;
return rax_control_regs[ offset ];
}
static WRITE16_HANDLER( rax_control_w )
{
rax_control_regs[ offset ] = data;
switch( offset )
{
case RAX_BDMA_INT_ADDR_REG:
rax_control_regs[ offset ] = data & 0x3fff;
break;
case RAX_BDMA_EXT_ADDR_REG:
rax_control_regs[ offset ] = data & 0x3fff;
break;
case RAX_BDMA_CONTROL_REG:
rax_control_regs[ offset ] = data & 0xff0f;
break;
case RAX_BDMA_WORD_COUNT_REG:
rax_control_regs[ offset ] = data & 0x3fff;
rax_bdma( data );
break;
case RAX_S1_AUTOBUF_REG:
/* autobuffer off: the right DAC stops */
if( !( data & 2 ) )
{
stream_update( rax_stream, 0 );
rax_dac_enabled[ 1 ] = 0;
rax_buffer_in[ 1 ] = rax_buffer_out[ 1 ] = 0;
}
break;
case RAX_S0_AUTOBUF_REG:
/* autobuffer off: the left DAC and the transfers stop */
if( !( data & 2 ) )
{
stream_update( rax_stream, 0 );
rax_dac_enabled[ 0 ] = 0;
rax_buffer_in[ 0 ] = rax_buffer_out[ 0 ] = 0;
timer_adjust( rax_reg_timer, TIME_NEVER, 0, 0 );
rax_reg_timer_period = 0;
}
break;
}
}
/* the I/O space: data RAM bank, ROM bank, and the latches */
static UINT16 rax_io_r( UINT32 offset )
{
if( offset == 3 )
{
cpu_set_irq_line( rax_cpunum, ADSP2181_IRQL0, CLEAR_LINE );
return rax_data_in;
}
return 0xffff;
}
static void rax_io_w( UINT32 offset, UINT16 data )
{
switch( offset )
{
case 0:
/* the board has two more RAM sockets, empty */
rax_data_bank = data & 3;
rax_update_data_ram_bank();
break;
case 1:
rax_rom_bank = data;
break;
case 3:
rax_data_out = data;
rax_pf0 = 0;
break;
}
}
static void rax_dmovlay_w( UINT32 data )
{
rax_dmovlay = ( data != 0 );
rax_update_data_ram_bank();
}
/* a quarter of the autobuffer, to the DACs (left, right interleaved) */
static void rax_irq( int param )
{
int reg = cpunum_get_reg( rax_cpunum, ADSP2100_I0 + rax_ireg );
int count = rax_size / ( 4 * ( rax_incs ? rax_incs : 1 ) );
int i;
stream_update( rax_stream, 0 );
for( i = 0; i < ( count & ~1 ); i++ )
{
UINT16 *p = rax_data_ptr( reg );
int n_channel = i & 1;
if( rax_dac_enabled[ n_channel ] )
{
rax_buffer[ n_channel ][ rax_buffer_in[ n_channel ] & RAX_BUFFER_MASK ] = p ? (INT16)*p : 0;
if( rax_buffer_in[ n_channel ] - rax_buffer_out[ n_channel ] < RAX_BUFFER_SIZE - 1 )
rax_buffer_in[ n_channel ]++;
}
reg += rax_incs;
}
/* check for wrapping */
if( reg >= rax_ireg_base + rax_size )
reg = rax_ireg_base;
cpunum_set_reg( rax_cpunum, ADSP2100_I0 + rax_ireg, reg );
}
/* SPORT0 transmit: the autobuffer starts */
static void rax_tx_callback( int port, INT32 data )
{
if( port != 0 )
return;
/* SPORT0 enabled */
if( rax_control_regs[ RAX_SYSCONTROL_REG ] & 0x1000 )
{
/* autobuffer only, which is what this board uses */
if( rax_control_regs[ RAX_S0_AUTOBUF_REG ] & 0x0002 )
{
int mreg, lreg;
UINT16 source;
stream_update( rax_stream, 0 );
rax_ireg = ( rax_control_regs[ RAX_S0_AUTOBUF_REG ] >> 9 ) & 7;
mreg = ( rax_control_regs[ RAX_S0_AUTOBUF_REG ] >> 7 ) & 3;
mreg |= rax_ireg & 0x04; /* msb comes from ireg */
lreg = rax_ireg;
source = cpunum_get_reg( rax_cpunum, ADSP2100_I0 + rax_ireg );
rax_incs = cpunum_get_reg( rax_cpunum, ADSP2100_M0 + mreg );
rax_size = cpunum_get_reg( rax_cpunum, ADSP2100_L0 + lreg );
/* the base value, kept for the wrapping; back one, so that the
first sample is not lost */
source -= rax_incs;
cpunum_set_reg( rax_cpunum, ADSP2100_I0 + rax_ireg, source );
rax_ireg_base = source;
/* a sample every 16 serial clocks; the DACs at that rate */
rax_sample_rate = RAX_CLOCK / ( 16 * ( rax_control_regs[ RAX_S0_SCLKDIV_REG ] + 1 ) );
rax_sample_step = (UINT32)( (double)rax_sample_rate * 65536.0 / (double)Machine->sample_rate );
rax_dac_enabled[ 0 ] = rax_dac_enabled[ 1 ] = 1;
/* a timer every quarter of the buffer (two samples per pair) */
if( rax_incs )
{
rax_reg_timer_period = TIME_IN_HZ( rax_sample_rate ) * rax_size / ( 4 * 2 * rax_incs );
timer_adjust( rax_reg_timer, rax_reg_timer_period, 0, rax_reg_timer_period );
}
return;
}
}
/* anything else: no sound */
stream_update( rax_stream, 0 );
rax_dac_enabled[ 0 ] = rax_dac_enabled[ 1 ] = 0;
rax_buffer_in[ 0 ] = rax_buffer_out[ 0 ] = rax_buffer_in[ 1 ] = rax_buffer_out[ 1 ] = 0;
timer_adjust( rax_reg_timer, TIME_NEVER, 0, 0 );
rax_reg_timer_period = 0;
}
/* both DACs, resampled to the output rate; silence when one runs out */
static void rax_dac_update( int num, INT16 **buffer, int length )
{
UINT32 n_end = rax_sample_position;
int n_channel;
for( n_channel = 0; n_channel < 2; n_channel++ )
{
INT16 *dest = buffer[ n_channel ];
UINT32 current = rax_sample_position;
UINT32 n_used;
int i;
for( i = 0; i < length; i++ )
{
UINT32 n_index = rax_buffer_out[ n_channel ] + ( current >> 16 );
if( !rax_dac_enabled[ n_channel ] || n_index >= rax_buffer_in[ n_channel ] )
break;
dest[ i ] = rax_buffer[ n_channel ][ n_index & RAX_BUFFER_MASK ];
current += rax_sample_step;
}
for( ; i < length; i++ )
dest[ i ] = 0;
/* drop the samples played, keep the fraction */
n_used = current >> 16;
if( n_used > rax_buffer_in[ n_channel ] - rax_buffer_out[ n_channel ] )
n_used = rax_buffer_in[ n_channel ] - rax_buffer_out[ n_channel ];
rax_buffer_out[ n_channel ] += n_used;
if( n_channel == 0 )
n_end = current & 0xffff;
}
rax_sample_position = n_end;
}
static int rax_custom_start( const struct MachineSound *msound )
{
const char *names[] = { "RAX DAC L", "RAX DAC R" };
int vols[] = { MIXER( 100, MIXER_PAN_LEFT ), MIXER( 100, MIXER_PAN_RIGHT ) };
int i;
rax_stream = stream_init_multi( 2, names, vols, Machine->sample_rate, 0, rax_dac_update );
for( i = 0; i < 2; i++ )
{
rax_buffer[ i ] = auto_malloc( RAX_BUFFER_SIZE * sizeof( INT16 ) );
if( !rax_buffer[ i ] )
return 1;
memset( rax_buffer[ i ], 0, RAX_BUFFER_SIZE * sizeof( INT16 ) );
}
state_save_register_INT16( "rax", 0, "buffer_l", rax_buffer[ 0 ], RAX_BUFFER_SIZE );
state_save_register_INT16( "rax", 0, "buffer_r", rax_buffer[ 1 ], RAX_BUFFER_SIZE );
return 0;
}
static struct CustomSound_interface rax_custom_interface =
{
rax_custom_start, 0, 0
};
static MEMORY_READ16_START( rax_readmem )
{ ADSP_DATA_ADDR_RANGE( 0x0000, 0x1fff ), MRA16_BANK14 }, /* internal RAM, or external through DMOVLAY */
{ ADSP_DATA_ADDR_RANGE( 0x2000, 0x3fdf ), MRA16_RAM }, /* internal RAM */
{ ADSP_DATA_ADDR_RANGE( 0x3fe0, 0x3fff ), rax_control_r }, /* control registers */
{ ADSP_PGM_ADDR_RANGE( 0x0000, 0x3fff ), MRA16_RAM }, /* internal program RAM */
MEMORY_END
static MEMORY_WRITE16_START( rax_writemem )
{ ADSP_DATA_ADDR_RANGE( 0x0000, 0x1fff ), MWA16_BANK14 },
{ ADSP_DATA_ADDR_RANGE( 0x2000, 0x3fdf ), MWA16_RAM },
{ ADSP_DATA_ADDR_RANGE( 0x3fe0, 0x3fff ), rax_control_w },
{ ADSP_PGM_ADDR_RANGE( 0x0000, 0x3fff ), MWA16_RAM },
MEMORY_END
static void rax_presave( void )
{
rax_reg_timer_left = timer_timeleft( rax_reg_timer );
rax_dma_timer_left = timer_timeleft( rax_dma_timer );
}
static void rax_postload( void )
{
rax_update_data_ram_bank();
if( rax_reg_timer_period > 0 && rax_reg_timer_left < TIME_NEVER / 2 )
timer_adjust( rax_reg_timer, ( rax_reg_timer_left > 0 ) ? rax_reg_timer_left : 0, 0, rax_reg_timer_period );
else
timer_adjust( rax_reg_timer, TIME_NEVER, 0, 0 );
if( rax_dma_timer_left < TIME_NEVER / 2 )
timer_adjust( rax_dma_timer, ( rax_dma_timer_left > 0 ) ? rax_dma_timer_left : 0, rax_dma_param, 0 );
else
timer_adjust( rax_dma_timer, TIME_NEVER, 0, 0 );
}
static void rax_init( int cpunum )
{
rax_cpunum = cpunum;
rax_rom = memory_region( REGION_SOUND1 );
rax_banked_ram = auto_malloc( 0x2000 * 5 * sizeof( UINT16 ) );
memset( rax_banked_ram, 0, 0x2000 * 5 * sizeof( UINT16 ) );
rax_reg_timer = timer_alloc( rax_irq );
rax_dma_timer = timer_alloc( rax_dma_done );
adsp2181_set_tx_callback( rax_tx_callback );
adsp2181_set_io_callbacks( rax_io_r, rax_io_w );
adsp2181_set_dmovlay_callback( rax_dmovlay_w );
state_save_register_UINT16( "rax", 0, "banked_ram", rax_banked_ram, 0x2000 * 5 );
state_save_register_UINT16( "rax", 0, "control_regs", rax_control_regs, 32 );
state_save_register_UINT16( "rax", 0, "data_in", &rax_data_in, 1 );
state_save_register_UINT16( "rax", 0, "data_out", &rax_data_out, 1 );
state_save_register_UINT8( "rax", 0, "pf0", &rax_pf0, 1 );
state_save_register_UINT16( "rax", 0, "data_bank", &rax_data_bank, 1 );
state_save_register_UINT16( "rax", 0, "rom_bank", &rax_rom_bank, 1 );
state_save_register_UINT32( "rax", 0, "dmovlay", &rax_dmovlay, 1 );
state_save_register_UINT16( "rax", 0, "size", &rax_size, 1 );
state_save_register_UINT16( "rax", 0, "incs", &rax_incs, 1 );
state_save_register_INT32( "rax", 0, "ireg", &rax_ireg, 1 );
state_save_register_UINT16( "rax", 0, "ireg_base", &rax_ireg_base, 1 );
state_save_register_UINT8( "rax", 0, "dac_enabled", rax_dac_enabled, 2 );
state_save_register_double( "rax", 0, "reg_timer_period", &rax_reg_timer_period, 1 );
state_save_register_double( "rax", 0, "reg_timer_left", &rax_reg_timer_left, 1 );
state_save_register_double( "rax", 0, "dma_timer_left", &rax_dma_timer_left, 1 );
state_save_register_UINT32( "rax", 0, "dma_param", &rax_dma_param, 1 );
state_save_register_UINT32( "rax", 0, "buffer_in", rax_buffer_in, 2 );
state_save_register_UINT32( "rax", 0, "buffer_out", rax_buffer_out, 2 );
state_save_register_UINT32( "rax", 0, "sample_rate", &rax_sample_rate, 1 );
state_save_register_UINT32( "rax", 0, "sample_step", &rax_sample_step, 1 );
state_save_register_UINT32( "rax", 0, "sample_position", &rax_sample_position, 1 );
state_save_register_func_presave( rax_presave );
state_save_register_func_postload( rax_postload );
}
static void rax_reset( void )
{
UINT32 *pgm = (UINT32 *)( memory_region( REGION_CPU1 + rax_cpunum ) + ADSP2181_PGM_OFFSET );
int i;
/* the boot: 32 program words (96 bytes) from the ROM, as by BDMA */
for( i = 0; i < 32; i++ )
pgm[ i ] = ( rax_rom[ i * 3 + 0 ] << 16 ) | ( rax_rom[ i * 3 + 1 ] << 8 ) | rax_rom[ i * 3 + 2 ];
rax_pf0 = 1;
rax_rom_bank = 0;
rax_size = 0;
rax_incs = 0;
rax_ireg = 0;
memset( rax_control_regs, 0, sizeof( rax_control_regs ) );
rax_dmovlay = 0;
rax_data_bank = 0;
rax_update_data_ram_bank();
rax_dac_enabled[ 0 ] = rax_dac_enabled[ 1 ] = 0;
rax_buffer_in[ 0 ] = rax_buffer_out[ 0 ] = rax_buffer_in[ 1 ] = rax_buffer_out[ 1 ] = 0;
rax_sample_position = 0;
rax_sample_step = 0x10000;
rax_reg_timer_period = 0;
timer_adjust( rax_reg_timer, TIME_NEVER, 0, 0 );
timer_adjust( rax_dma_timer, TIME_NEVER, 0, 0 );
}
/* from the main CPU: a command, IRQL0 on the ADSP */
static void rax_data_w( UINT16 data )
{
rax_data_in = data;
cpu_set_irq_line( rax_cpunum, ADSP2181_IRQL0, ASSERT_LINE );
cpu_boost_interleave( 0, TIME_IN_USEC( 5 ) );
}
/* the main board side */
static UINT8 *nbajamex_sram; /* 71256 */
@@ -3399,7 +2904,7 @@ static WRITE32_HANDLER( nbajamex_sound_80_w )
{
/* all 16 bits go to the latch of the sound board (see the sound test) */
if( ( mem_mask & 0x0000ffff ) != 0x0000ffff )
rax_data_w( data & 0xffff );
acclaim_rax_data_w( data & 0xffff );
}
static MEMORY_READ32_START( nbajamex_readmem )
@@ -3453,7 +2958,7 @@ static DRIVER_INIT( nbajamex )
znsec_init( 0, memory_region( REGION_USER4 ) ); /* AC01 */
znsec_init( 1, memory_region( REGION_USER5 ) ); /* AC02 */
rax_init( mame_find_cpu_index( "rax" ) );
acclaim_rax_init( mame_find_cpu_index( "rax" ), REGION_SOUND1 );
state_save_register_UINT8( "zn", 0, "nbajamex_sram", nbajamex_sram, 0x8000 );
state_save_register_UINT32( "zn", 0, "nbajamex_rombank", nbajamex_rombank, 2 );
@@ -3468,7 +2973,7 @@ static MACHINE_INIT( nbajamex )
nbajamex_rombank[ 0 ] = nbajamex_rombank[ 1 ] = 0;
nbajamex_bankmap = 0;
nbajamex_update_banks();
rax_reset();
acclaim_rax_reset();
}
/* ZN-1, 2MB VRAM (COH-1000A), SPU and the RAX sound board */
@@ -3479,7 +2984,7 @@ static MACHINE_DRIVER_START( nbajamex )
MDRV_CPU_ADD_TAG( "rax", ADSP2181, RAX_CLOCK )
MDRV_CPU_FLAGS( CPU_AUDIO_CPU )
MDRV_CPU_MEMORY( rax_readmem, rax_writemem )
MDRV_CPU_MEMORY( acclaim_rax_readmem, acclaim_rax_writemem )
MDRV_FRAMES_PER_SECOND( 60 )
MDRV_VBLANK_DURATION( 0 )
@@ -3499,7 +3004,7 @@ static MACHINE_DRIVER_START( nbajamex )
MDRV_SOUND_ATTRIBUTES( SOUND_SUPPORTS_STEREO )
MDRV_SOUND_ADD( PSXSPU, zn_spu_interface )
MDRV_SOUND_ADD( CUSTOM, rax_custom_interface )
MDRV_SOUND_ADD( CUSTOM, acclaim_rax_custom_interface )
MACHINE_DRIVER_END
src/includes/galaxian.h
+1
View File
@@ -153,6 +153,7 @@ DRIVER_INIT( scrambls );
DRIVER_INIT( theend );
DRIVER_INIT( ckongs );
DRIVER_INIT( mariner );
DRIVER_INIT( knockoutb );
DRIVER_INIT( mars );
DRIVER_INIT( devilfsh );
DRIVER_INIT( hotshock );
src/includes/megadriv.h
+107
View File
@@ -0,0 +1,107 @@
/*************************************************************************
Sega Mega Drive (Genesis) based boards
Shared by System C/C2, Mega-Tech, Mega Play, the Mega Drive bootlegs,
Genie / Y-BOX and Sun Mixing.
**************************************************************************/
#ifndef MEGADRIV_H
#define MEGADRIV_H
#include "vidhrdw/segavdp.h"
/*----------- defined in machine/megadriv.c -----------*/
/* the 68000 interrupts from the VDP (and the YM3438 on System C/C2) */
INTERRUPT_GEN( genesis_vblank_interrupt );
void megadriv_ym3438_irq(int state);
void megadriv_vdp_irq_update(void);
void megadriv_irq_init(const UINT8 *hint_mask);
void megadriv_irq_state_register(void);
void genesis_enable_iack(void);
extern data16_t *genesis_68k_ram;
extern unsigned char *genesis_z80_ram;
extern data16_t *genesis_io_ram;
MACHINE_DRIVER_EXTERN( genesis_base );
MACHINE_DRIVER_EXTERN( genesis ); /* genesis_base and the PSG */
MACHINE_INIT( genesis );
READ16_HANDLER( genesis_68k_to_z80_r );
WRITE16_HANDLER( genesis_68k_to_z80_w );
READ16_HANDLER( genesis_68000_io_r );
WRITE16_HANDLER( genesis_68000_io_w );
READ16_HANDLER( genesis_ctrl_r );
WRITE16_HANDLER( genesis_ctrl_w );
WRITE16_HANDLER( genesis_io_w );
WRITE16_HANDLER( sn76489_w );
READ_HANDLER( genesis_z80_r );
WRITE_HANDLER( genesis_z80_w );
READ_HANDLER( genesis_z80_bank_r );
extern struct YM2612interface gen_ym3438_intf;
/*----------- defined in drivers/megatech.c -----------*/
/* the Master System VDP of the Mega-Tech and Mega Play BIOS */
READ_HANDLER( megatech_bios_port_be_bf_r );
WRITE_HANDLER( megatech_bios_port_be_bf_w );
extern struct SN76496interface megatech_sn76489_intf;
/*----------- defined in vidhrdw/segac2_vidhrdw.c -----------*/
VIDEO_START( megadriv );
VIDEO_START( megatech );
VIDEO_START( megaplay );
VIDEO_EOF( segac2 );
VIDEO_UPDATE( segac2 );
VIDEO_UPDATE( megaplay );
/* the two Mega Drive pads */
#define GENESIS_PORTS \
PORT_START \
\
PORT_START /* Player 1 Controls - part 1 */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
\
PORT_START /* Player 1 Controls - part 2 */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) \
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
\
PORT_START /* Player 2 Controls - part 1 */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 ) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 ) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
\
PORT_START /* Player 2 Controls - part 2 */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) \
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
#endif
src/includes/model2.h
+2
View File
@@ -11,6 +11,8 @@
extern data32_t *model2_bufferram;
extern data32_t *model2_textureram0;
extern data32_t *model2_textureram1;
extern UINT8 *model2_texdec0; /* the sheets one byte per texel, y * 2048 + x */
extern UINT8 *model2_texdec1;
extern data16_t *model2_palram;
extern data16_t *model2_colorxlat;
extern UINT8 *model2_lumaram;
src/includes/namcos22.h
+72 -30
View File
@@ -1,7 +1,16 @@
#include "driver.h"
#include "vidhrdw/generic.h"
/***************************************************************************
extern enum namcos22_gametype
Namco System 22 / Super System 22
Backported from current MAME (Phil Stroffolino, hap, R. Belmont and
others, BSD-3-Clause).
***************************************************************************/
#ifndef NAMCOS22_H
#define NAMCOS22_H
enum
{
NAMCOS22_AIR_COMBAT22,
NAMCOS22_ALPINE_RACER,
@@ -10,38 +19,71 @@ extern enum namcos22_gametype
NAMCOS22_PROP_CYCLE,
NAMCOS22_RAVE_RACER,
NAMCOS22_RIDGE_RACER,
NAMCOS22_RIDGE_RACER2,
NAMCOS22_TIME_CRISIS,
NAMCOS22_VICTORY_LAP,
NAMCOS22_ACE_DRIVER
} namcos22_gametype;
NAMCOS22_ACE_DRIVER,
NAMCOS22_ALPINE_RACER_2,
NAMCOS22_ALPINE_SURFER,
NAMCOS22_TOKYO_WARS,
NAMCOS22_AQUA_JET,
NAMCOS22_DIRT_DASH,
NAMCOS22_ARMADILLO_RACING
};
#define NAMCOS22_NUM_ROWS 30
#define NAMCOS22_NUM_COLS 40
#define NAMCOS22_ALPHA_GFX 1
/* big endian views of the 32-bit RAMs (stored as native data32_t) */
#define NTHBYTE32(base, n) (((base)[(n) >> 2] >> (8 * (~(n) & 3))) & 0xff)
#define NTHWORD32(base, n) (((base)[(n) >> 1] >> (16 * (~(n) & 1))) & 0xffff)
#define NAMCOS22_PALETTE_SIZE 0x8000
#define SIGNED12(v) ((INT32)((UINT32)(v) << 20) >> 20)
#define SIGNED18(v) ((INT32)((UINT32)(v) << 14) >> 14)
#define SIGNED24(v) ((INT32)((UINT32)(v) << 8) >> 8)
extern data32_t *namcos22_cgram;
extern data32_t *namcos22_textram;
extern data32_t *namcos22_polygonram;
extern data32_t *namcos22_gamma;
READ32_HANDLER( namcos22_cgram_r );
WRITE32_HANDLER( namcos22_cgram_w );
READ32_HANDLER( namcos22_paletteram_r );
WRITE32_HANDLER( namcos22_paletteram_w );
READ32_HANDLER( namcos22_textram_r );
WRITE32_HANDLER( namcos22_textram_w );
READ32_HANDLER( namcos22_gamma_r );
WRITE32_HANDLER( namcos22_gamma_w );
READ32_HANDLER( namcos22_dspram_r );
WRITE32_HANDLER( namcos22_dspram_w );
VIDEO_UPDATE( namcos22 );
/* drivers/namcos22.c */
extern int namcos22_gametype;
extern int namcos22_is_ss22;
extern data32_t *namcos22_polygonram; /* 0x8000 dwords, 24 bits connected */
extern data32_t *namcos22_spriteram;
extern data32_t *namcos22_vics_data;
extern data32_t *namcos22_vics_control;
extern data32_t *namcos22_mixer;
extern data32_t *namcos22_paletteram;
extern data32_t *namcos22_cgram; /* text layer tiles; the tilemap is at 0x1e000 */
extern data32_t *namcos22_czram; /* System 22 */
extern data16_t *namcos22_shareram;
extern data8_t *namcos22_gamma_proms; /* System 22 */
extern int namcos22_pdp_render_done;
extern int namcos22_render_refresh;
extern int namcos22_slave_simulation_active;
extern UINT32 namcos22_pdp_frame;
extern INT32 namcos22_point_read(offs_t offs);
extern void namcos22_pdp_handle_commands(UINT16 offs);
extern UINT8 namcos22_syscontrol[0x20];
extern int namcos22_irq_enabled, namcos22_irq_state;
void namcos22_draw_crosshairs(struct mame_bitmap *bitmap, const struct rectangle *cliprect);
/* vidhrdw/namcos22_vidhrdw.c */
VIDEO_START( namcos22s );
VIDEO_START( namcos22 );
VIDEO_UPDATE( namcos22s );
VIDEO_UPDATE( namcos22 );
VIDEO_STOP( namcos22 );
int namcos22_video_threads_available(void);
void namcos22_video_reset(void);
void namcos22_draw_direct_poly(const UINT16 *src);
WRITE32_HANDLER( namcos22_paletteram_w );
WRITE32_HANDLER( namcos22_cgram_w );
READ32_HANDLER( namcos22_tilemapattr_r );
WRITE32_HANDLER( namcos22_tilemapattr_w );
READ32_HANDLER( namcos22s_czattr_r );
WRITE32_HANDLER( namcos22s_czattr_w );
READ32_HANDLER( namcos22s_czram_r );
WRITE32_HANDLER( namcos22s_czram_w );
READ32_HANDLER( namcos22s_spotram_r );
WRITE32_HANDLER( namcos22s_spotram_w );
READ32_HANDLER( namcos22s_vics_control_r );
WRITE32_HANDLER( namcos22s_vics_control_w );
WRITE32_HANDLER( namcos22s_chipselect_w );
#endif
src/includes/segac2.h
+2 -21
View File
@@ -4,27 +4,8 @@
**************************************************************************/
/*----------- defined in vidhrdw/segac2.c -----------*/
#include "megadriv.h"
extern UINT8 segac2_vdp_regs[];
extern int segac2_bg_palbase;
extern int segac2_sp_palbase;
extern int segac2_palbank;
extern UINT16 scanbase;
VIDEO_START( puckpkmn );
VIDEO_START( megatech );
VIDEO_START( megaplay );
/*----------- defined in vidhrdw/segac2_vidhrdw.c -----------*/
VIDEO_START( segac2 );
VIDEO_EOF( segac2 );
VIDEO_UPDATE( segac2 );
VIDEO_UPDATE( megatech );
VIDEO_UPDATE( megaplay );
void segac2_enable_display(int enable);
READ16_HANDLER ( segac2_vdp_r );
WRITE16_HANDLER( segac2_vdp_w );
src/includes/segas32.h
+1 -2
View File
@@ -19,9 +19,8 @@ extern UINT16 *system32_paletteram[2];
extern UINT16 system32_displayenable[2];
extern UINT16 system32_tilebank_external;
extern bool opaquey_hack;
extern bool opaque_blend;
extern bool titlef_kludge;
extern bool f1lap_kludge;
extern void system32_set_vblank(int state);
src/includes/stv.h
+43
View File
@@ -0,0 +1,43 @@
/***************************************************************************
Sega ST-V: interface between the driver and the video (VDP1, VDP2)
***************************************************************************/
#ifndef STV_H
#define STV_H
/* vidhrdw/stvvid.c */
extern UINT16 *vdp2_regs;
extern UINT32 *vdp2_vram;
extern UINT32 *vdp2_cram;
extern UINT32 *vdp1_vram;
extern UINT16 *vdp1_regs;
READ32_HANDLER( stv_vdp1_regs_r );
WRITE32_HANDLER( stv_vdp1_regs_w );
READ32_HANDLER( stv_vdp1_vram_r );
WRITE32_HANDLER( stv_vdp1_vram_w );
READ32_HANDLER( stv_vdp1_framebuffer0_r );
WRITE32_HANDLER( stv_vdp1_framebuffer0_w );
READ32_HANDLER( stv_vdp2_vram_r );
WRITE32_HANDLER( stv_vdp2_vram_w );
READ32_HANDLER( stv_vdp2_cram_r );
WRITE32_HANDLER( stv_vdp2_cram_w );
READ32_HANDLER( stv_vdp2_regs_r );
WRITE32_HANDLER( stv_vdp2_regs_w );
VIDEO_START( stv_vdp2 );
VIDEO_STOP( stv_vdp2 );
VIDEO_UPDATE( stv_vdp2 );
/* drivers/stv.c: the lightgun crosshairs, over the finished screen */
void stv_draw_crosshairs(struct mame_bitmap *bitmap, const struct rectangle *clip);
/* frame timing, from the driver's scanline interrupt */
int stv_vdp2_vblank_start_line(void); /* the line vblank-in happens on */
void stv_vdp2_scanline(int line); /* the start of each line, 0 to 262 */
void stv_vdp1_video_update(void); /* at vblank-in: frame change, automatic draw */
void stv_vdp1_vblank_erase(void); /* one line after vblank-in */
#endif
src/includes/system16.h
+4 -7
View File
@@ -118,8 +118,6 @@ extern struct GfxDecodeInfo sys16_gfxdecodeinfo[];
/* encryption decoding */
void endurob2_decode_data(data16_t *dest,data16_t *source,int size);
void endurob2_decode_data2(data16_t *dest,data16_t *source,int size);
void enduror_decode_data(data16_t *dest,data16_t *source,int size);
void enduror_decode_data2(data16_t *dest,data16_t *source,int size);
void aurail_decode_data(data16_t *dest,data16_t *source,int size);
void aurail_decode_opcode1(data16_t *dest,data16_t *source,int size);
@@ -270,11 +268,10 @@ void system18_set_grayscale(int enable);
void system18_set_vdp_enable(int enable);
void system18_set_vdp_mixing(int mixing);
/* vidhrdw/segac2.c */
void update_system18_vdp( struct mame_bitmap *bitmap, const struct rectangle *cliprect );
void start_system18_vdp(void);
READ16_HANDLER( segac2_vdp_r );
WRITE16_HANDLER( segac2_vdp_w );
/* the System 18 VDP (vidhrdw/segas18.c, on vidhrdw/segavdp.c) */
int system18_vdp_start(void);
void system18_vdp_update( struct mame_bitmap *bitmap, const struct rectangle *cliprect );
VIDEO_EOF( system18 );
/* video driver constants (vary with game) */
src/includes/tx1.h
+139
View File
@@ -0,0 +1,139 @@
/***************************************************************************
Tatsumi TX-1 / Buggy Boy hardware
From current MAME (src/mame/tatsumi/tx1*, Philip Bennett)
***************************************************************************/
#ifndef TX1_H
#define TX1_H
#include "cpu/i86/i86intf.h"
#define TX1_PIXEL_CLOCK (18000000 / 3)
#define TX1_HBSTART 256
#define TX1_HTOTAL 384
#define TX1_VBSTART 240
#define TX1_VTOTAL 264
/* as MAME: VTOTAL increased to fix a missing start countdown tone */
#define BB_PIXEL_CLOCK (18000000 / 3)
#define BB_HBSTART 256
#define BB_HTOTAL 384
#define BB_VBSTART 240
#define BB_VTOTAL (288 + 1)
#define CPU_MASTER_CLOCK 15000000
#define BUGGYBOY_ZCLK (CPU_MASTER_CLOCK / 2)
/* the TEST pin of the 8086 (WAIT instruction), see cpu/i86 */
#define TX1_TEST_LINE I86_TEST_LINE
/* machine (tx1_machine.c): the arithmetic unit */
struct tx1_math_t
{
UINT16 cpulatch;
UINT16 promaddr;
UINT16 inslatch;
UINT32 mux;
UINT16 ppshift;
UINT32 i0ff;
UINT16 retval;
UINT16 muxlatch; /* TX-1 */
};
/* SN74S516 16x16 multiplier/divider */
struct tx1_sn74s516_t
{
INT16 X;
INT16 Y;
INT32 ZW32; /* Z: high 16 bits, W: low 16 bits */
INT32 code;
INT32 state;
INT32 ZWfl;
};
extern struct tx1_math_t tx1_math;
extern struct tx1_sn74s516_t tx1_sn74s516;
READ16_HANDLER( tx1_math_r );
WRITE16_HANDLER( tx1_math_w );
READ16_HANDLER( tx1_spcs_rom_r );
READ16_HANDLER( tx1_spcs_ram_r );
WRITE16_HANDLER( tx1_spcs_ram_w );
READ16_HANDLER( buggyboy_math_r );
WRITE16_HANDLER( buggyboy_math_w );
READ16_HANDLER( buggyboy_spcs_rom_r );
READ16_HANDLER( buggyboy_spcs_ram_r );
WRITE16_HANDLER( buggyboy_spcs_ram_w );
MACHINE_INIT( tx1 );
void tx1_machine_state_register(void);
/* video (tx1_vidhrdw.c) */
extern data16_t *tx1_math_ram;
extern data16_t *tx1_vram;
extern data16_t *tx1_objram;
extern data16_t *tx1_rcram;
extern size_t tx1_vram_size;
READ16_HANDLER( tx1_crtc_r );
WRITE16_HANDLER( tx1_crtc_w );
WRITE16_HANDLER( tx1_bankcs_w );
WRITE16_HANDLER( tx1_slincs_w );
WRITE16_HANDLER( tx1_slock_w );
WRITE16_HANDLER( tx1_scolst_w );
WRITE16_HANDLER( tx1_flgcs_w );
WRITE16_HANDLER( buggyboy_gas_w );
WRITE16_HANDLER( buggyboy_sky_w );
WRITE16_HANDLER( buggyboy_scolst_w );
PALETTE_INIT( tx1 );
PALETTE_INIT( buggyboy );
VIDEO_START( tx1 );
VIDEO_START( buggyboy );
VIDEO_START( buggybjr );
VIDEO_UPDATE( tx1 );
VIDEO_UPDATE( buggyboy );
VIDEO_UPDATE( buggybjr );
VIDEO_EOF( tx1 );
VIDEO_EOF( buggyboy );
/* sound (tx1_sndhrdw.c) */
READ16_HANDLER( tx1_dipswitches_r );
WRITE16_HANDLER( tx1_z80_busreq_w );
READ16_HANDLER( tx1_z80_shared_r );
WRITE16_HANDLER( tx1_z80_shared_w );
WRITE_HANDLER( tx1_z80_intreq_w );
READ_HANDLER( tx1_ts_r );
WRITE_HANDLER( tx1_ts_w );
READ_HANDLER( tx1_pit8253_r );
WRITE_HANDLER( tx1_pit8253_w );
WRITE_HANDLER( tx1_ppi_latch_w );
READ_HANDLER( tx1_ppi_porta_r );
READ_HANDLER( tx1_ppi_portb_r );
WRITE_HANDLER( tx1_coin_cnt_w );
WRITE_HANDLER( tx1_ay8910_a_w );
WRITE_HANDLER( tx1_ay8910_b_w );
READ_HANDLER( bb_analog_r );
READ_HANDLER( bbjr_analog_r );
WRITE_HANDLER( bb_coin_cnt_w );
WRITE_HANDLER( bb_ym1_a_w );
WRITE_HANDLER( bb_ym2_a_w );
WRITE_HANDLER( bb_ym2_b_w );
WRITE_HANDLER( bbjr_ym2_b_w );
INTERRUPT_GEN( tx1_z80_irq );
int tx1_sh_start(const struct MachineSound *msound);
int buggyboy_sh_start(const struct MachineSound *msound);
void tx1_sh_reset(void);
void buggyboy_sh_reset(void);
extern data8_t *tx1_z80_ram;
/* the input ports, numbered as in the driver */
#define TX1_PORT_DSW 0
#define TX1_PORT_STEERING 1
#define TX1_PORT_ACCEL 2
#define TX1_PORT_BRAKE 3
#define TX1_PORT_PPI_A 4 /* Buggy Boy: PPI port A / BB Jr: YM2149 IC19 port A */
#define TX1_PORT_PPI_C 5 /* TX-1: PPI port C; Buggy Boy: PPI port C / BB Jr: YM2149 IC19 port B */
#endif
src/machine/7474.c
+13
View File
@@ -39,6 +39,7 @@
#include "driver.h"
#include "machine/7474.h"
#include "state.h"
#define MAX_TTL7474 12
@@ -158,4 +159,16 @@ void TTL7474_config(int which, const struct TTL7474_interface *intf)
chips[which].last_clock = 1;
chips[which].last_output = -1;
chips[which].last_output_comp = -1;
/* save states (a reset configures the chip again: the entries are
registered once, the duplicates are ignored) */
state_save_register_INT32("ttl7474", which, "clear", (INT32 *)&chips[which].clear, 1);
state_save_register_INT32("ttl7474", which, "preset", (INT32 *)&chips[which].preset, 1);
state_save_register_INT32("ttl7474", which, "clock", (INT32 *)&chips[which].clock, 1);
state_save_register_INT32("ttl7474", which, "d", (INT32 *)&chips[which].d, 1);
state_save_register_INT32("ttl7474", which, "output", (INT32 *)&chips[which].output, 1);
state_save_register_INT32("ttl7474", which, "output_comp", (INT32 *)&chips[which].output_comp, 1);
state_save_register_INT32("ttl7474", which, "last_clock", (INT32 *)&chips[which].last_clock, 1);
state_save_register_INT32("ttl7474", which, "last_output", (INT32 *)&chips[which].last_output, 1);
state_save_register_INT32("ttl7474", which, "last_output_comp", (INT32 *)&chips[which].last_output_comp, 1);
}
src/machine/bublbobl_machine.c
+39 -2
View File
@@ -10,12 +10,26 @@
#include "driver.h"
#include "cpu/z80/z80.h"
#include "vidhrdw/generic.h"
#include "state.h"
unsigned char *bublbobl_sharedram1,*bublbobl_sharedram2;
extern int bublbobl_video_enable;
/* the ROM bank at 0x8000, -1 until the game selects one */
static int bublbobl_bank = -1;
static void bublbobl_set_bank(void)
{
unsigned char *ROM = memory_region(REGION_CPU1);
if (bublbobl_bank >= 0)
cpu_setbank(1,&ROM[0x10000 + 0x4000 * bublbobl_bank]);
else
cpu_setbank(1,&ROM[0x8000]);
}
READ_HANDLER( bublbobl_sharedram1_r )
{
@@ -41,7 +55,8 @@ WRITE_HANDLER( bublbobl_bankswitch_w )
unsigned char *ROM = memory_region(REGION_CPU1);
/* bits 0-2 select ROM bank */
cpu_setbank(1,&ROM[0x10000 + 0x4000 * ((data ^ 4) & 7)]);
bublbobl_bank = (data ^ 4) & 7;
cpu_setbank(1,&ROM[0x10000 + 0x4000 * bublbobl_bank]);
/* bit 3 n.c. */
@@ -65,7 +80,8 @@ WRITE_HANDLER( tokio_bankswitch_w )
unsigned char *ROM = memory_region(REGION_CPU1);
/* bits 0-2 select ROM bank */
cpu_setbank(1,&ROM[0x10000 + 0x4000 * (data & 7)]);
bublbobl_bank = data & 7;
cpu_setbank(1,&ROM[0x10000 + 0x4000 * bublbobl_bank]);
/* bits 3-7 unknown */
}
@@ -257,3 +273,24 @@ WRITE_HANDLER( bublbobl_68705_ddrB_w )
{
ddrB = data;
}
/* save states: the ROM bank, the display enable, the sound NMI and the
68705 ports of Bubble Bobble and Tokio */
void bublbobl_save_state(void)
{
bublbobl_bank = -1;
state_save_register_int ("bublbobl", 0, "bank", &bublbobl_bank);
state_save_register_int ("bublbobl", 0, "video_enable", &bublbobl_video_enable);
state_save_register_int ("bublbobl", 0, "sound_nmi_enable", &sound_nmi_enable);
state_save_register_int ("bublbobl", 0, "pending_nmi", &pending_nmi);
state_save_register_UINT8("bublbobl", 0, "portA_in", &portA_in, 1);
state_save_register_UINT8("bublbobl", 0, "portA_out", &portA_out, 1);
state_save_register_UINT8("bublbobl", 0, "ddrA", &ddrA, 1);
state_save_register_UINT8("bublbobl", 0, "portB_in", &portB_in, 1);
state_save_register_UINT8("bublbobl", 0, "portB_out", &portB_out, 1);
state_save_register_UINT8("bublbobl", 0, "ddrB", &ddrB, 1);
state_save_register_int ("bublbobl", 0, "address", &address);
state_save_register_int ("bublbobl", 0, "latch", &latch);
state_save_register_func_postload(bublbobl_set_bank);
}
src/machine/fd1094.c
+46 -12
View File
@@ -49,6 +49,15 @@ static UINT16 *fd1094_current; /* the one for the current state */
static UINT8 fd1094_state;
static UINT8 fd1094_irqmode;
/* CPU address windows that fetch their opcodes from the ROM, through the
decryption: by default the whole ROM at its own address */
#define FD1094_MAX_WINDOWS 4
static int fd1094_numwindows;
static offs_t fd1094_win_start[FD1094_MAX_WINDOWS];
static offs_t fd1094_win_end[FD1094_MAX_WINDOWS];
static offs_t fd1094_win_rgnoffs[FD1094_MAX_WINDOWS];
static int fd1094_curwin; /* window of the current opcode base, or -1 */
/* opcodes using PC-relative addressing, replaced by FFFF */
static const UINT16 masked_opcodes[] =
{
@@ -373,17 +382,22 @@ static UINT16 *fd1094_get_decrypted(UINT8 state)
static OPBASE_HANDLER( fd1094_setopbase )
{
if (address < fd1094_rom_size)
{
OP_RAM = (UINT8 *)fd1094_rom;
OP_ROM = (UINT8 *)fd1094_current;
OP_MEM_MIN = 0;
OP_MEM_MAX = fd1094_rom_size - 1;
opcode_entry = STATIC_ROM;
return ~0;
}
int w;
for (w = 0; w < fd1094_numwindows; w++)
if (address >= fd1094_win_start[w] && address <= fd1094_win_end[w])
{
OP_RAM = (UINT8 *)fd1094_rom + fd1094_win_rgnoffs[w] - fd1094_win_start[w];
OP_ROM = (UINT8 *)fd1094_current + fd1094_win_rgnoffs[w] - fd1094_win_start[w];
OP_MEM_MIN = fd1094_win_start[w];
OP_MEM_MAX = fd1094_win_end[w];
opcode_entry = STATIC_ROM;
fd1094_curwin = w;
return ~0;
}
/* let the memory system find the base, with no offset for the opcodes */
fd1094_curwin = -1;
OP_ROM = OP_RAM;
return address;
}
@@ -399,8 +413,12 @@ static void fd1094_refresh(void)
fd1094_current = fd1094_get_decrypted(fd1094_irqmode ? fd1094_key[0] : fd1094_state);
cpuintrf_push_context(fd1094_cpunum);
if (OP_RAM == (UINT8 *)fd1094_rom)
OP_ROM = (UINT8 *)fd1094_current;
if (fd1094_curwin >= 0)
{
offs_t delta = fd1094_win_rgnoffs[fd1094_curwin] - fd1094_win_start[fd1094_curwin];
if (OP_RAM == (UINT8 *)fd1094_rom + delta)
OP_ROM = (UINT8 *)fd1094_current + delta;
}
cpuintrf_pop_context();
}
@@ -477,6 +495,12 @@ void fd1094_driver_init(int cpunum, int keyregion)
fd1094_cache[i] = NULL;
build_masked_opcodes_lookup();
fd1094_numwindows = 1;
fd1094_win_start[0] = 0;
fd1094_win_end[0] = fd1094_rom_size - 1;
fd1094_win_rgnoffs[0] = 0;
fd1094_curwin = -1;
fd1094_state = 0;
fd1094_irqmode = 0;
fd1094_current = fd1094_get_decrypted(0);
@@ -486,6 +510,15 @@ void fd1094_driver_init(int cpunum, int keyregion)
state_save_register_func_postload(fd1094_postload);
}
void fd1094_set_window(int which, offs_t start, offs_t end, offs_t rgnoffs)
{
fd1094_win_start[which] = start;
fd1094_win_end[which] = end;
fd1094_win_rgnoffs[which] = rgnoffs;
if (fd1094_numwindows < which + 1)
fd1094_numwindows = which + 1;
}
void fd1094_machine_init(void)
{
/* the hooks are cleared when the CPUs are initialised */
@@ -498,8 +531,9 @@ void fd1094_machine_init(void)
cpuintrf_push_context(fd1094_cpunum);
OP_RAM = (UINT8 *)fd1094_rom;
OP_MEM_MIN = 0;
OP_MEM_MAX = fd1094_rom_size - 1;
OP_MEM_MAX = fd1094_win_end[0];
opcode_entry = STATIC_ROM;
fd1094_curwin = 0;
cpuintrf_pop_context();
fd1094_cpu_reset();
src/machine/fd1094.h
+5 -1
View File
@@ -4,9 +4,13 @@
/* Hitachi FD1094 (encrypted 68000), see machine/fd1094.c.
DRIVER_INIT: fd1094_driver_init(cpu, key region).
MACHINE_INIT: fd1094_machine_init().
When the hardware resets the CPU: fd1094_cpu_reset(). */
When the hardware resets the CPU: fd1094_cpu_reset().
The opcodes of CPU addresses start-end come decrypted from the ROM at
rgnoffs: window 0 is the whole ROM at its own address, and
fd1094_set_window() (after fd1094_driver_init) changes it or adds one. */
void fd1094_driver_init(int cpunum, int keyregion);
void fd1094_machine_init(void);
void fd1094_cpu_reset(void);
void fd1094_set_window(int which, offs_t start, offs_t end, offs_t rgnoffs);
#endif
src/machine/mc8123.c
+330
View File
@@ -3122,3 +3122,333 @@ void mc8123_decrypt_ninjakid2(void)
rom[A] = mc8123_decrypt(A,src,key,0);
}
}
/***************************************************************************
Key based MC-8123 decryption (backport of the current MAME mc8123
device). The 0x2000 byte key is the dump of the battery-backed RAM of
the CPU (317-xxxx.key in the current MAME sets): the first half holds
the tables used for opcodes, the second half the ones used for data.
***************************************************************************/
static UINT8 mc8123k_decrypt_type0(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,7,5,3,1,2,0,6,4);
if (swap == 1) val = BITSWAP8(val,5,3,7,2,1,0,4,6);
if (swap == 2) val = BITSWAP8(val,0,3,4,6,7,1,5,2);
if (swap == 3) val = BITSWAP8(val,0,7,3,2,6,4,1,5);
if (BIT(param,3) && BIT(val,7))
val ^= 0x29;
if (BIT(param,2) && BIT(val,6))
val ^= 0x86;
if (BIT(val,6)) val ^= 0x80;
if (BIT(param,1) && BIT(val,7))
val ^= 0x40;
if (BIT(val,2)) val ^= 0x21;
val ^= 0x1a;
if (BIT(param,2)) val ^= 0x25;
if (BIT(param,1)) val ^= 0xc0;
if (BIT(param,0)) val ^= 0x21;
if (BIT(param,0)) val = BITSWAP8(val,7,6,5,1,4,3,2,0);
return val;
}
static UINT8 mc8123k_decrypt_type1a(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,4,2,6,5,3,7,1,0);
if (swap == 1) val = BITSWAP8(val,6,0,5,4,3,2,1,7);
if (swap == 2) val = BITSWAP8(val,2,3,6,1,4,0,7,5);
if (swap == 3) val = BITSWAP8(val,6,5,1,3,2,7,0,4);
if (BIT(param,2)) val = BITSWAP8(val,7,6,1,5,3,2,4,0);
if (BIT(val,1)) val ^= 0x01;
if (BIT(val,6)) val ^= 0x08;
if (BIT(val,7)) val ^= 0x48;
if (BIT(val,2)) val ^= 0x4a;
if (BIT(val,4)) val ^= 0xc4;
if (BIT(val,7) ^ BIT(val,2))
val ^= 0x10;
val ^= 0x4b;
if (BIT(param,3)) val ^= 0x84;
if (BIT(param,1)) val ^= 0x48;
if (BIT(param,0)) val = BITSWAP8(val,7,6,1,4,3,2,5,0);
return val;
}
static UINT8 mc8123k_decrypt_type1b(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,1,0,3,2,5,6,4,7);
if (swap == 1) val = BITSWAP8(val,2,0,5,1,7,4,6,3);
if (swap == 2) val = BITSWAP8(val,6,4,7,2,0,5,1,3);
if (swap == 3) val = BITSWAP8(val,7,1,3,6,0,2,5,4);
if (BIT(val,2) && BIT(val,0))
val ^= 0x90;
if (BIT(val,7)) val ^= 0x04;
if (BIT(val,5)) val ^= 0x84;
if (BIT(val,1)) val ^= 0x20;
if (BIT(val,6)) val ^= 0x02;
if (BIT(val,4)) val ^= 0x60;
if (BIT(val,0)) val ^= 0x46;
if (BIT(val,3)) val ^= 0xc7;
val ^= 0x51;
if (BIT(param,3)) val ^= 0x12;
if (BIT(param,2)) val ^= 0xc9;
if (BIT(param,1)) val ^= 0x18;
if (BIT(param,0)) val ^= 0x47;
return val;
}
static UINT8 mc8123k_decrypt_type2a(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,0,1,4,3,5,6,2,7);
if (swap == 1) val = BITSWAP8(val,6,3,0,5,7,4,1,2);
if (swap == 2) val = BITSWAP8(val,1,6,4,5,0,3,7,2);
if (swap == 3) val = BITSWAP8(val,4,6,7,5,2,3,1,0);
if (BIT(val,3) || (BIT(param,1) && BIT(val,2)))
val = BITSWAP8(val,6,0,7,4,3,2,1,5);
if (BIT(val,5)) val ^= 0x80;
if (BIT(val,6)) val ^= 0x20;
if (BIT(val,0)) val ^= 0x40;
if (BIT(val,4)) val ^= 0x09;
if (BIT(val,1)) val ^= 0x04;
val ^= 0xf2;
if (BIT(param,2)) val ^= 0x1f;
if (BIT(param,3))
{
if (BIT(param,0))
val = BITSWAP8(val,7,6,5,3,4,1,2,0);
else
val = BITSWAP8(val,7,6,5,1,2,4,3,0);
}
else if (BIT(param,0))
{
val = BITSWAP8(val,7,6,5,2,1,3,4,0);
}
return val;
}
static UINT8 mc8123k_decrypt_type2b(UINT8 val, UINT8 param, unsigned swap)
{
/* only 0x20 possible encryptions for this method - all others have 0x40 */
/* this happens because BIT(param,2) cancels the other three */
if (swap == 0) val = BITSWAP8(val,1,3,4,6,5,7,0,2);
if (swap == 1) val = BITSWAP8(val,0,1,5,4,7,3,2,6);
if (swap == 2) val = BITSWAP8(val,3,5,4,1,6,2,0,7);
if (swap == 3) val = BITSWAP8(val,5,2,3,0,4,7,6,1);
if (BIT(val,7) && BIT(val,3))
val ^= 0x51;
if (BIT(val,7)) val ^= 0x04;
if (BIT(val,5)) val ^= 0x88;
if (BIT(val,1)) val ^= 0x20;
if (BIT(val,4)) val ^= 0xaa;
if (BIT(val,7) && BIT(val,5))
val ^= 0x11;
if (BIT(val,5) && BIT(val,1))
val ^= 0x11;
if (BIT(val,6)) val ^= 0xa0;
if (BIT(val,3)) val ^= 0xe2;
if (BIT(val,2)) val ^= 0x0a;
val ^= 0x8e;
if (BIT(param,3)) val ^= 0x4a;
if (BIT(param,2)) val ^= 0xee; /* same as the other three combined */
if (BIT(param,1)) val ^= 0x80;
if (BIT(param,0)) val ^= 0x24;
return val;
}
static UINT8 mc8123k_decrypt_type3a(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,5,3,1,7,0,2,6,4);
if (swap == 1) val = BITSWAP8(val,3,1,2,5,4,7,0,6);
if (swap == 2) val = BITSWAP8(val,5,6,1,2,7,0,4,3);
if (swap == 3) val = BITSWAP8(val,5,6,7,0,4,2,1,3);
if (BIT(val,2)) val ^= 0xb0;
if (BIT(val,3)) val ^= 0x01;
if (BIT(param,0)) val = BITSWAP8(val,7,2,5,4,3,1,0,6);
if (BIT(val,1)) val ^= 0x41;
if (BIT(val,3)) val ^= 0x16;
if (BIT(param,3)) val ^= 0x18;
if (BIT(val,3)) val = BITSWAP8(val,5,6,7,4,3,2,1,0);
if (BIT(val,5)) val ^= 0x06;
val ^= 0x78;
if (BIT(param,2)) val ^= 0x80;
if (BIT(param,1)) val ^= 0x10;
if (BIT(param,0)) val ^= 0x01;
return val;
}
static UINT8 mc8123k_decrypt_type3b(UINT8 val, UINT8 param, unsigned swap)
{
if (swap == 0) val = BITSWAP8(val,3,7,5,4,0,6,2,1);
if (swap == 1) val = BITSWAP8(val,7,5,4,6,1,2,0,3);
if (swap == 2) val = BITSWAP8(val,7,4,3,0,5,1,6,2);
if (swap == 3) val = BITSWAP8(val,2,6,4,1,3,7,0,5);
if (BIT(val,2)) val ^= 0x80;
if (BIT(val,7)) val = BITSWAP8(val,7,6,3,4,5,2,1,0);
if (BIT(param,3)) val ^= 0x80;
if (BIT(val,4)) val ^= 0x40;
if (BIT(val,1)) val ^= 0x54;
if (BIT(val,7) && BIT(val,6))
val ^= 0x02;
if (BIT(val,7)) val ^= 0x02;
if (BIT(param,3)) val ^= 0x80;
if (BIT(param,2)) val ^= 0x01;
if (BIT(param,3)) val = BITSWAP8(val,4,6,3,2,5,0,1,7);
if (BIT(val,4)) val ^= 0x02;
if (BIT(val,5)) val ^= 0x10;
if (BIT(val,7)) val ^= 0x04;
val ^= 0x2c;
if (BIT(param,1)) val ^= 0x80;
if (BIT(param,0)) val ^= 0x08;
return val;
}
static UINT8 mc8123k_decrypt_internal(UINT8 val, UINT8 key, int opcode)
{
unsigned type = 0;
unsigned swap = 0;
UINT8 param = 0;
key ^= 0xff;
/* no encryption */
if (key == 0x00)
return val;
type ^= BIT(key,0) << 0;
type ^= BIT(key,2) << 0;
type ^= BIT(key,0) << 1;
type ^= BIT(key,1) << 1;
type ^= BIT(key,2) << 1;
type ^= BIT(key,4) << 1;
type ^= BIT(key,4) << 2;
type ^= BIT(key,5) << 2;
swap ^= BIT(key,0) << 0;
swap ^= BIT(key,1) << 0;
swap ^= BIT(key,2) << 1;
swap ^= BIT(key,3) << 1;
param ^= BIT(key,0) << 0;
param ^= BIT(key,0) << 1;
param ^= BIT(key,2) << 1;
param ^= BIT(key,3) << 1;
param ^= BIT(key,0) << 2;
param ^= BIT(key,1) << 2;
param ^= BIT(key,6) << 2;
param ^= BIT(key,1) << 3;
param ^= BIT(key,6) << 3;
param ^= BIT(key,7) << 3;
if (!opcode)
{
param ^= 0x01;
type ^= 0x01;
}
switch (type)
{
default:
case 0: return mc8123k_decrypt_type0(val, param, swap);
case 1: return mc8123k_decrypt_type0(val, param, swap);
case 2: return mc8123k_decrypt_type1a(val, param, swap);
case 3: return mc8123k_decrypt_type1b(val, param, swap);
case 4: return mc8123k_decrypt_type2a(val, param, swap);
case 5: return mc8123k_decrypt_type2b(val, param, swap);
case 6: return mc8123k_decrypt_type3a(val, param, swap);
case 7: return mc8123k_decrypt_type3b(val, param, swap);
}
}
static UINT8 mc8123k_decrypt(const UINT8 *key, offs_t addr, UINT8 val, int opcode)
{
/* pick the translation table from bits fd57 of the address */
offs_t tbl_num =
(BIT(addr,15) << 11) | (BIT(addr,14) << 10) | (BIT(addr,13) << 9) | (BIT(addr,12) << 8) |
(BIT(addr,11) << 7) | (BIT(addr,10) << 6) | (BIT(addr, 8) << 5) | (BIT(addr, 6) << 4) |
(BIT(addr, 4) << 3) | (BIT(addr, 2) << 2) | (BIT(addr, 1) << 1) | BIT(addr, 0);
return mc8123k_decrypt_internal(val, key[tbl_num | (opcode ? 0x0000 : 0x1000)], opcode);
}
/* decode the bytes of 'rom' from offset 'start' up to 'end' (excluded):
data is decrypted in place, opcodes are written at the same offsets of
'opcodes'. As in MAME, offsets from 0xc000 up are banked ROM, seen by the
CPU at 0x8000-0xbfff. */
void mc8123_decode(UINT8 *rom, UINT8 *opcodes, const UINT8 *key, int start, int end)
{
int i;
for (i = start; i < end; i++)
{
offs_t adr = (i >= 0xc000) ? ((i & 0x3fff) | 0x8000) : i;
UINT8 src = rom[i];
/* decode the opcodes */
opcodes[i] = mc8123k_decrypt(key, adr, src, 1);
/* decode the data */
rom[i] = mc8123k_decrypt(key, adr, src, 0);
}
}
src/machine/megadriv.c
+986
View File
@@ -0,0 +1,986 @@
/***************************************************************************
Sega Mega Drive (Genesis) based boards
The Mega Drive part shared by the Mega-Tech, Mega Play, bootleg, Genie /
Y-BOX and Sun Mixing boards, as megadriv.cpp in current MAME: the 68000
interrupts from the VDP (also used by System C/C2), the sound Z80 and
its bus, the Mega Drive I/O and the machine drivers. Moved here from
drivers/segac2.c; the VDP is in vidhrdw/segavdp.c and the video glue in
vidhrdw/segac2_vidhrdw.c.
***************************************************************************/
#include "driver.h"
#include "cpu/m68000/m68000.h"
#include "state.h"
#include "megadriv.h"
#define MASTER_CLOCK 53693100
/* interrupt states */
static UINT8 ym3438_int; /* INT2 - from YM3438 */
static UINT8 scanline_int; /* INT4 - programmable */
static UINT8 vblank_int; /* INT6 - on every VBLANK */
/* System C/C2: bit 4 of I/O port H masks the H-INT (NULL on the other boards) */
static const UINT8 *hint_mask_reg;
/* the sound Z80 */
static unsigned int z80_68000_latch;
static unsigned int z80_latch_bitcount;
static int z80running;
data16_t *genesis_68k_ram;
unsigned char *genesis_z80_ram;
/******************************************************************************
Interrupt handling
*******************************************************************************
The C/C2 System and the Mega Drive use 3 Different Interrupts, IRQ2, IRQ4
and IRQ6 (IRQ2 is only connected on System C/C2).
IRQ6 = Vblank, this happens after the last visible line of the display has
been drawn (after line 224)
IRQ4 = H-Int, this happens based upon the value in H-Int Counter. If the
Horizontal Interrupt is enabled and the Counter Value = 0 there
will be a Level 4 Interrupt Triggered
IRQ2 = sound int, generated by the YM3438
--------
More H-Counter Information:
Providing Horizontal Interrupts are active the H-Counter will be loaded
with the value stored in register #10 (0x0A) at the following times:
(1) At the top of the display, before drawing the first line
(2) When the counter has expired
(3) During the VBlank Period (lines 224-261)
The Counter is decreased by 1 after every line.
******************************************************************************/
/* Mega Play: H-INT/V-INT are cleared by the 68000 interrupt acknowledge
(see genesis_irq_ack_callback) instead of timing out; also selects the
corrected HBLANK status bit of the VDP (segavdp_set_iack_mode) */
static int genesis_vdp_iack;
/* System C/C2: V-INT comes from the line that drives the Z80 interrupt on a
Mega Drive (not masked by the VDP register 1 enable, the usual V-INT line
isn't connected), H-INT as usual; both stay asserted until the 68000 takes
them, as in current MAME */
static int c2_iack;
static int genesis_irq_ack_callback(int irqline);
/* call this whenever the interrupt state has changed */
static void update_interrupts(void)
{
int level = 0;
/* determine which interrupt is active */
if (ym3438_int) level = 2;
if (c2_iack)
{
if (scanline_int) level = 4;
if (vblank_int) level = 6;
}
else if (genesis_vdp_iack)
{
/* Mega Play: a pending H-INT/V-INT only drives the line while it is
enabled in VDP register 0/1, as on the real 315-5313 (Mazin Wars masks
H-INT this way while its V-INT handler borrows a5/a6, which its H-INT
handler jumps through) */
if (scanline_int && (segavdp_get_reg(0) & 0x10)) level = 4;
if (vblank_int && (segavdp_get_reg(1) & 0x20)) level = 6;
}
else
{
if (scanline_int) level = 4;
if (vblank_int) level = 6;
}
/* either set or clear the appropriate lines */
if (level)
cpu_set_irq_line(0, level, ASSERT_LINE);
else
cpu_set_irq_line(0, 7, CLEAR_LINE);
}
/* timer callback to turn off the IRQ4 signal after a short while */
static void vdp_int4_off(int param)
{
scanline_int = 0;
update_interrupts();
}
/* timer callback to handle reloading the H counter and generate IRQ4 */
static void vdp_reload_counter(int scanline)
{
/* generate an int if they're enabled */
if ((segavdp_get_reg(0) & 0x10) && !(hint_mask_reg && (*hint_mask_reg & 0x10)))
if (scanline != 0 || segavdp_get_reg(10) == 0)
{
scanline_int = 1;
update_interrupts();
/* with IACK emulation the line stays asserted until the 68000 takes it */
if (!genesis_vdp_iack && !c2_iack)
timer_set(segavdp_scanlinetime(scanline + 1), 0, vdp_int4_off);
}
/* advance to the next scanline */
/* behavior 2: 0 count means interrupt after one scanline */
/* (this behavior matches the Sega C2 emulator) */
/* (in this case the vidhrdw ichidant kludge should be -2) */
scanline += segavdp_get_reg(10) + 1;
if (scanline >= 224)
scanline = 0;
/* set a timer */
timer_set(segavdp_scanlinetime(scanline) + segavdp_scanlineperiod() * (320. / 342.), scanline, vdp_reload_counter);
}
/* timer callback to turn off the IRQ6 signal after a short while */
static void vdp_int6_off(int param)
{
vblank_int = 0;
update_interrupts();
}
/* interrupt callback to generate the VBLANK interrupt */
/* Mega Play: V-INT raised shortly after the VBLANK status bit */
static void genesis_vint_delayed(int param)
{
/* the pending flag is always set; update_interrupts() gates it with R1 */
vblank_int = 1;
update_interrupts();
}
/* called by the VDP after a write to R0/R1 (Mega Play only) */
void megadriv_vdp_irq_update(void)
{
if (genesis_vdp_iack)
update_interrupts();
}
INTERRUPT_GEN( genesis_vblank_interrupt )
{
/* with IACK emulation V-INT stays pending until the 68000 takes it, so it
is not lost while an H-INT handler has the interrupts masked; as on the
real 315-5313 it only drives the 68000 while enabled in VDP register 1 */
if (genesis_vdp_iack)
{
/* the VBLANK status bit rises first and V-INT follows about 788 master
clocks later (~112 68000 cycles): code polling the status bit gets to
see VBLANK before the interrupt takes over. Mazin Wars depends on it:
its V-INT handler outlasts the blanking period, so without the gap its
main loop never sees VBLANK and hangs in a fade loop after coin-up. */
segavdp_set_vblank();
timer_set(TIME_IN_USEC(788.0 * 1000000.0 / 53693100.0), 0, genesis_vint_delayed);
return;
}
/* generate the interrupt */
vblank_int = 1;
update_interrupts();
if (c2_iack)
return;
/* set a timer to turn it off */
timer_set(segavdp_scanlineperiod() * (22. / 342.), 0, vdp_int6_off);
}
/* interrupt callback to generate the YM3438 interrupt */
void megadriv_ym3438_irq(int state)
{
ym3438_int = state;
update_interrupts();
}
/* System C/C2: the interrupts of the board at reset */
void megadriv_irq_init(const UINT8 *hint_mask)
{
/* the Mega Play interrupt acknowledge is not used here */
genesis_vdp_iack = 0;
segavdp_set_iack_mode(0);
hint_mask_reg = hint_mask;
c2_iack = 1;
scanline_int = vblank_int = 0;
cpu_set_irq_callback(0, genesis_irq_ack_callback);
/* set the first scanline 0 timer to go off */
timer_set(segavdp_scanlinetime(0) + segavdp_scanlineperiod() * (320. / 342.), 0, vdp_reload_counter);
}
/* the interrupt states, saved by every board */
void megadriv_irq_state_register(void)
{
state_save_register_UINT8 ("C2_main", 0, "Int 2 Status", &ym3438_int, 1);
state_save_register_UINT8 ("C2_main", 0, "Int 4 Status", &scanline_int, 1);
state_save_register_UINT8 ("C2_main", 0, "Int 6 Status", &vblank_int, 1);
}
static void genesis_state_register(void);
MACHINE_INIT( genesis )
{
genesis_vdp_iack = 0;
c2_iack = 0;
segavdp_set_iack_mode(0);
hint_mask_reg = NULL;
/* the Mega Drive, Mega-Tech and Mega Play state (repeated registrations are ignored) */
genesis_state_register();
/* the following ensures that the Z80 begins without running away from 0 */
/* 0x76 is just a forced 'halt' as soon as the CPU is initially run */
genesis_z80_ram[0] = 0x76;
genesis_z80_ram[0x38] = 0x76;
cpu_set_halt_line(1, ASSERT_LINE);
z80running = 0;
log_cb(RETRO_LOG_DEBUG, LOGPRE "Machine init\n");
timer_set(segavdp_scanlinetime(0) + segavdp_scanlineperiod() * (320. / 342.), 0, vdp_reload_counter);
}
/* On the real 315-5313 VDP the H-INT (level 4) and V-INT (level 6) pending
flags are cleared when the 68000 acknowledges the interrupt.
The old timed pulses break games that use H-INT on every line:
- IRQ4 held for a whole scanline re-enters a short H-INT handler over and
over and the main program starves;
- IRQ6 dropped after 22 pixels is lost when the H-INT handler of line 223
still has the interrupts masked, so the game never sees V-INT again.
Gunstar Heroes hits both (68000 stuck at $FFEE04, its H-INT handler in RAM). */
static int genesis_irq_ack_callback(int irqline)
{
int level = 0;
if (irqline == 4)
scanline_int = 0;
else if (irqline == 6)
vblank_int = 0;
if (ym3438_int) level = 2;
if (c2_iack)
{
if (scanline_int) level = 4;
if (vblank_int) level = 6;
}
else
{
if (scanline_int && (segavdp_get_reg(0) & 0x10)) level = 4;
if (vblank_int && (segavdp_get_reg(1) & 0x20)) level = 6;
}
/* drop the line now (an immediate clear cannot re-enter the CPU core),
then re-assert whatever is still pending */
activecpu_set_irq_line(7, INTERNAL_CLEAR_LINE);
if (level)
cpu_set_irq_line(0, level, ASSERT_LINE);
return MC68000_INT_ACK_AUTOVECTOR;
}
/* Mega Play: the H-INT/V-INT are acknowledged by the 68000 (machine init) */
void genesis_enable_iack(void)
{
genesis_vdp_iack = 1;
segavdp_set_iack_mode(1);
scanline_int = vblank_int = 0;
cpu_set_irq_callback(0, genesis_irq_ack_callback);
}
/* handle writes to the SN764896 */
WRITE16_HANDLER( sn76489_w )
{
/* only works if we're accessing the low byte */
if (ACCESSING_LSB)
SN76496_0_w(0, data & 0xff);
}
/******************** Sega Genesis ******************************/
/* from MESS */
READ16_HANDLER(genesis_ctrl_r)
{
/* int returnval; */
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "genesis_ctrl_r %x\n", offset); */
switch (offset)
{
case 0: /* DRAM mode is write only */
return 0xffff;
break;
case 0x80: /* return Z80 CPU Function Stop Accessible or not */
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "Returning z80 state\n"); */
return (z80running ? 0x0100 : 0x0);
break;
case 0x100: /* Z80 CPU Reset - write only */
return 0xffff;
break;
}
return 0x00;
}
/* from MESS */
WRITE16_HANDLER(genesis_ctrl_w)
{
data &= ~mem_mask;
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "genesis_ctrl_w %x, %x\n", offset, data); */
switch (offset)
{
case 0: /* set DRAM mode... we have to ignore this for production cartridges */
return;
break;
case 0x80: /* Z80 BusReq */
if (data == 0x100)
{
z80running = 0;
cpu_set_halt_line(1, ASSERT_LINE); /* halt Z80 */
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "z80 stopped by 68k BusReq\n"); */
}
else
{
z80running = 1;
cpu_setbank(1, &genesis_z80_ram[0]);
cpu_set_halt_line(1, CLEAR_LINE);
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "z80 started, BusReq ends\n"); */
}
return;
break;
case 0x100: /* Z80 CPU Reset */
if (data == 0x00)
{
cpu_set_halt_line(1, ASSERT_LINE);
cpu_set_reset_line(1, PULSE_LINE);
cpu_set_halt_line(1, ASSERT_LINE);
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "z80 reset, ram is %p\n", &genesis_z80_ram[0]); */
z80running = 0;
return;
}
else
{
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "z80 out of reset\n"); */
}
return;
break;
}
}
READ16_HANDLER ( genesis_68k_to_z80_r )
{
offset *= 2;
offset &= 0x7fff;
/* Shared Ram */
if ((offset >= 0x0000) && (offset <= 0x3fff))
{
offset &=0x1fff;
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "soundram_r returning %x\n",(gen_z80_shared[offset] << 8) + gen_z80_shared[offset+1]);*/
return (genesis_z80_ram[offset] << 8) + genesis_z80_ram[offset+1];
}
/* YM2610 */
if ((offset >= 0x4000) && (offset <= 0x5fff))
{
switch (offset & 3)
{
case 0:
if (ACCESSING_MSB) return YM2612_status_port_0_A_r(0) << 8;
else return YM2612_read_port_0_r(0);
break;
case 2:
if (ACCESSING_MSB) return YM2612_status_port_0_B_r(0) << 8;
else return 0;
break;
}
}
/* Bank Register */
if ((offset >= 0x6000) && (offset <= 0x60ff))
{
}
/* Unused / Illegal */
if ((offset >= 0x6100) && (offset <= 0x7eff))
{
/* nothing */
}
/* VDP */
if ((offset >= 0x7f00) && (offset <= 0x7fff))
{
}
return 0x0000;
}
WRITE16_HANDLER ( genesis_68k_to_z80_w )
{
offset *= 2;
offset &= 0x7fff;
/* Shared Ram */
if ((offset >= 0x0000) && (offset <= 0x3fff))
{
offset &=0x1fff;
if (ACCESSING_LSB) genesis_z80_ram[offset+1] = data & 0xff;
if (ACCESSING_MSB) genesis_z80_ram[offset] = (data >> 8) & 0xff;
}
/* YM2610 */
if ((offset >= 0x4000) && (offset <= 0x5fff))
{
switch (offset & 3)
{
case 0:
if (ACCESSING_MSB) YM2612_control_port_0_A_w (0, (data >> 8) & 0xff);
else YM2612_data_port_0_A_w (0, (data >> 0) & 0xff);
break;
case 2:
if (ACCESSING_MSB) YM2612_control_port_0_B_w (0, (data >> 8) & 0xff);
else YM2612_data_port_0_B_w (0, (data >> 0) & 0xff);
break;
}
}
/* Bank Register */
if ((offset >= 0x6000) && (offset <= 0x60ff))
{
}
/* Unused / Illegal */
if ((offset >= 0x6100) && (offset <= 0x7eff))
{
/* nothing */
}
/* VDP */
if ((offset >= 0x7f00) && (offset <= 0x7fff))
{
offset &= 0x1f;
if ( (offset >= 0x10) && (offset <=0x17) )
{
if (ACCESSING_LSB) SN76496_0_w(0, data & 0xff);
if (ACCESSING_MSB) SN76496_0_w(0, (data >>8) & 0xff);
}
}
}
/* Gen I/O */
/*
cgfm info
$A10001 Version
$A10003 Port A data
$A10005 Port B data
$A10007 Port C data
$A10009 Port A control
$A1000B Port B control
$A1000D Port C control
$A1000F Port A TxData
$A10011 Port A RxData
$A10013 Port A serial control
$A10015 Port B TxData
$A10017 Port B RxData
$A10019 Port B serial control
$A1001B Port C TxData
$A1001D Port C RxData
$A1001F Port C serial control
*/
data16_t *genesis_io_ram;
WRITE16_HANDLER ( genesis_io_w )
{
/* log_cb(RETRO_LOG_DEBUG, LOGPRE "write io offset :%02x data %04x PC: 0x%06x\n",offset,data,activecpu_get_previouspc()); */
switch (offset)
{
case 0x00:
/*??*/
break;
case 0x01:/* port A data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x04])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x04]));
break;
case 0x02: /* port B data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x05])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x05]));
break;
case 0x03: /* port C data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x06])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x06]));
break;
case 0x04: /* port A control */
genesis_io_ram[offset] = data;
break;
case 0x05: /* port B control */
genesis_io_ram[offset] = data;
break;
case 0x06: /* port C control */
genesis_io_ram[offset] = data;
break;
case 0x07: /* port A TxData */
genesis_io_ram[offset] = data;
break;
default:
genesis_io_ram[offset] = data;
}
}
READ16_HANDLER ( genesis_68000_io_r )
{
int paddata,p;
int inlines, outlines;
/*printf("I/O read .. offset %02x data %02x\n",offset,genesis_io_ram[offset]); */
switch (offset)
{
case 0x00: /* version register */
return genesis_io_ram[offset];
case 0x01:
/* printf("I/O Data A read \n"); */
/*
When TH=0 When TH=1
D6 : (TH) 0 1
D5 : (TR) Start button Button C
D4 : (TL) Button A Button B
D3 : (D3) 0 D-pad Right
D2 : (D2) 0 D-pad Left
D1 : (D1) D-pad Down D-pad Down
D0 : (D0) D-pad Up D-pad Up
*/
/* process pad input for std 3 button pad */
p = readinputport(0);
if (genesis_io_ram[offset]&0x40)
{
paddata = ((p&0x0f)>>0) | ((p&0xc0)>>2) | 0x40;
}
else
{
paddata = ((p&0x03)>>0) | ((p&0x30)>>0) | 0x00;
}
inlines = (genesis_io_ram[0x04]^0xff)&0x7f;
outlines = (genesis_io_ram[0x04] | 0x80);
/* printf ("ioram %02x inlines %02x paddata %02x outlines %02x othdata %02x\n",genesis_io_ram[0x04], inlines, paddata, outlines, genesis_io_ram[0x01]); */
p = (paddata & inlines) | (genesis_io_ram[0x01] & outlines);
return p | p << 8;
return genesis_io_ram[offset];
case 0x02:
/* printf("I/O Data B read \n"); */
p = readinputport(1);
if (genesis_io_ram[offset]&0x40)
{
paddata = ((p&0x0f)>>0) | ((p&0xc0)>>2) | 0x40;
}
else
{
paddata = ((p&0x03)>>0) | ((p&0x30)>>0) | 0x00;
}
inlines = (genesis_io_ram[0x05]^0xff)&0x7f;
outlines = (genesis_io_ram[0x05] | 0x80);
p = (paddata & inlines) | (genesis_io_ram[0x02] & outlines);
return p | p <<8;
case 0x03:
/* printf("I/O Data C read \n"); */
return genesis_io_ram[offset];
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
default:
printf("Unhandled I/O read \n");
return genesis_io_ram[offset];
}
return genesis_io_ram[offset];
/*
D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
D6 : Video type is 1= PAL, 0= NTSC
D5 : Sega CD unit is 1= not present, 0= connected.
D4 : Unused (always returns zero)
D3 : Bit 3 of version number
D2 : Bit 2 of version number
D1 : Bit 1 of version number
D0 : Bit 0 of version number
*/
/* return 0x30; */
/* return mame_rand(); */
/* return 0xff; */
}
/*
The I/O chip is mapped to $A10000-$A1001F in the 68000/VDP/Z80 banked address space.
It is normally read and written in byte units at odd addresses. The chip gets /LWR only,
so writing to even addresses has no effect. Reading even addresses returns the same data
ou'd get from an odd address. If a word-sized write is done, the LSB is sent to the I/O chip
and the MSB is ignored.
*/
/*
$A10001 Version
$A10003 Port A data
$A10005 Port B data
$A10007 Port C data
$A10009 Port A control
$A1000B Port B control
$A1000D Port C control
$A1000F Port A TxData
$A10011 Port A RxData
$A10013 Port A serial control
$A10015 Port B TxData
$A10017 Port B RxData
$A10019 Port B serial control
$A1001B Port C TxData
$A1001D Port C RxData
$A1001F Port C serial contro
*/
WRITE16_HANDLER ( genesis_68000_io_w )
{
/* printf("I/O write offset %02x data %04x\n",offset,data); */
switch (offset)
{
case 0x00: /* Version (read only?) */
printf("attempted write to version register?!\n");
break;
case 0x01: /* Port A data */
/* printf("write to data port A with control register A %02x step1 %02x step2 %02x\n", genesis_io_ram[0x04], (genesis_io_ram[0x01] & !((genesis_io_ram[0x04]&0x7f)|0x80)), (data & ((genesis_io_ram[0x04]&0x7f)|0x80)) ); */
genesis_io_ram[0x01] = (genesis_io_ram[0x01] & ((genesis_io_ram[0x04]^0xff)|0x80)) | (data & ((genesis_io_ram[0x04]&0x7f)|0x80));
break;
case 0x02: /* Port B data */
/* printf("write to data port B with control register B %02x\n", genesis_io_ram[0x05]); */
genesis_io_ram[0x02] = (genesis_io_ram[0x02] & ((genesis_io_ram[0x05]^0xff)|0x80)) | (data & ((genesis_io_ram[0x05]&0x7f)|0x80));
break;
case 0x03: /* Port C data */
/* printf("write to data port C with control register C %02x\n", genesis_io_ram[0x06]); */
genesis_io_ram[0x03] = (genesis_io_ram[0x03] & ((genesis_io_ram[0x06]^0xff)|0x80)) | (data & ((genesis_io_ram[0x06]&0x7f)|0x80));
break;
case 0x04: /* Port A control */
genesis_io_ram[offset]=data;
break;
case 0x05: /* Port B control */
genesis_io_ram[offset]=data;
break;
case 0x06: /* Port C control */
genesis_io_ram[offset]=data;
break;
/* unhandled */
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
default:
genesis_io_ram[offset]=data;
printf("unhandled IO write (offset %02x data %02x)\n",offset,data);
break;
}
}
/* Z80 Sound Hardware - based on MESS code, to be improved, it can do some strange things */
#ifdef MSB_FIRST
#define BYTE_XOR(a) (a)
#else
#define BYTE_XOR(a) ((a) ^ 1)
#endif
static WRITE_HANDLER ( genesis_bank_select_w ) /* note value will be meaningless unless all bits are correctly set in */
{
if (offset !=0 ) return;
/* if (!z80running) log_cb(RETRO_LOG_DEBUG, LOGPRE "undead Z80 latch write!\n");*/
if (z80_latch_bitcount == 0) z80_68000_latch = 0;
z80_68000_latch = z80_68000_latch | ((( ((unsigned char)data) & 0x01) << (15+z80_latch_bitcount)));
log_cb(RETRO_LOG_DEBUG, LOGPRE "value %x written to latch\n", data);
z80_latch_bitcount++;
if (z80_latch_bitcount == 9)
{
z80_latch_bitcount = 0;
log_cb(RETRO_LOG_DEBUG, LOGPRE "latch set, value %x\n", z80_68000_latch);
}
}
READ_HANDLER ( genesis_z80_r )
{
offset += 0x4000;
/* YM2610 */
if ((offset >= 0x4000) && (offset <= 0x5fff))
{
switch (offset & 3)
{
case 0: return YM2612_status_port_0_A_r(0);
case 1: return YM2612_read_port_0_r(0);
case 2: return YM2612_status_port_0_B_r(0);
case 3: return 0;
}
}
/* Bank Register */
if ((offset >= 0x6000) && (offset <= 0x60ff))
{
}
/* Unused / Illegal */
if ((offset >= 0x6100) && (offset <= 0x7eff))
{
/* nothing */
}
/* VDP */
if ((offset >= 0x7f00) && (offset <= 0x7fff))
{
}
return 0x00;
}
WRITE_HANDLER ( genesis_z80_w )
{
offset += 0x4000;
/* YM2610 */
if ((offset >= 0x4000) && (offset <= 0x5fff))
{
switch (offset & 3)
{
case 0: YM2612_control_port_0_A_w (0, data);
break;
case 1: YM2612_data_port_0_A_w (0, data);
break;
case 2: YM2612_control_port_0_B_w (0, data);
break;
case 3: YM2612_data_port_0_B_w (0, data);
break;
}
}
/* Bank Register */
if ((offset >= 0x6000) && (offset <= 0x60ff))
{
genesis_bank_select_w(offset & 0xff, data);
}
/* Unused / Illegal */
if ((offset >= 0x6100) && (offset <= 0x7eff))
{
/* nothing */
}
/* VDP */
if ((offset >= 0x7f00) && (offset <= 0x7fff))
{
offset &= 0x1f;
if ( (offset >= 0x10) && (offset <=0x17) )
{
SN76496_0_w(0, data & 0xff);
}
}
}
READ_HANDLER ( genesis_z80_bank_r )
{
int address = (z80_68000_latch) + (offset & 0x7fff);
if (!z80running) log_cb(RETRO_LOG_DEBUG, LOGPRE "undead Z80->68000 read!\n");
if (z80_latch_bitcount != 0) log_cb(RETRO_LOG_DEBUG, LOGPRE "reading whilst latch being set!\n");
log_cb(RETRO_LOG_DEBUG, LOGPRE "z80 read from address %x\n", address);
/* Read the data out of the 68k ROM */
if (address < 0x400000) return memory_region(REGION_CPU1)[BYTE_XOR(address)];
/* else read the data out of the 68k RAM */
/* else if (address > 0xff0000) return genesis_68k_ram[BYTE_XOR(offset)];*/
return -1;
}
static MEMORY_READ_START(genesis_z80_readmem)
{ 0x0000, 0x1fff, MRA_BANK1 },
{ 0x2000, 0x3fff, MRA_BANK2 }, /* mirror */
{ 0x4000, 0x7fff, genesis_z80_r },
{ 0x8000, 0xffff, genesis_z80_bank_r },
MEMORY_END
static MEMORY_WRITE_START(genesis_z80_writemem)
{ 0x0000, 0x1fff, MWA_BANK1, &genesis_z80_ram },
{ 0x2000, 0x3fff, MWA_BANK2 }, /* mirror */
{ 0x4000, 0x7fff, genesis_z80_w },
/* { 0x8000, 0xffff, genesis_z80_bank_w },*/
MEMORY_END
/******************************************************************************
Sound interfaces
******************************************************************************/
struct YM2612interface gen_ym3438_intf =
{
1, /* One chip */
MASTER_CLOCK/7, /* Clock: 7.67 MHz */
{ YM3012_VOL(50,MIXER_PAN_CENTER,50,MIXER_PAN_CENTER) }, /* Volume */
{ 0 }, /* port I/O */
{ 0 }, /* port I/O */
{ 0 }, /* port I/O */
{ 0 }, /* port I/O */
/* no IRQ: the YM3438 interrupt line isn't connected on the Mega Drive */
};
static struct SN76496interface sn76489_intf =
{
1, /* One chip */
{ MASTER_CLOCK/15 }, /* Clock: 3.58 MHz */
{ 50 } /* Volume */
};
/******************************************************************************
Machine drivers
******************************************************************************/
MACHINE_DRIVER_START( genesis_base )
/*basic machine hardware */
MDRV_CPU_ADD_TAG("main", M68000, 53693100 / 7)
/* each board sets its own memory map */
MDRV_CPU_VBLANK_INT(genesis_vblank_interrupt,1)
MDRV_CPU_ADD_TAG("sound", Z80, 53693100 / 15)
MDRV_CPU_MEMORY(genesis_z80_readmem, genesis_z80_writemem)
MDRV_CPU_VBLANK_INT(irq0_line_hold, 1) /* from vdp at scanline 0xe0 */
MDRV_FRAMES_PER_SECOND(60)
MDRV_VBLANK_DURATION((int)(((262. - 224.) / 262.) * 1000000. / 60.))
MDRV_INTERLEAVE(100)
MDRV_MACHINE_INIT(genesis)
/* video hardware */
MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_HAS_SHADOWS | VIDEO_HAS_HIGHLIGHTS)
MDRV_SCREEN_SIZE(320,224)
MDRV_VISIBLE_AREA(0, 319, 0, 223)
MDRV_PALETTE_LENGTH(2048)
MDRV_VIDEO_START(megadriv)
MDRV_VIDEO_EOF(segac2)
MDRV_VIDEO_UPDATE(segac2)
/* sound hardware */
MDRV_SOUND_ADD(YM2612, gen_ym3438_intf )
MACHINE_DRIVER_END
MACHINE_DRIVER_START( genesis )
MDRV_IMPORT_FROM( genesis_base )
MDRV_SOUND_ADD(SN76496, sn76489_intf)
MACHINE_DRIVER_END
/******************************************************************************
Save states of the Mega Drive based boards: the interrupts, the Z80 RAM
and bus state, so that a state loaded in a new instance (netplay,
RunAhead with a second instance) continues exactly as the one that
saved it
******************************************************************************/
static void genesis_state_register(void)
{
megadriv_irq_state_register();
state_save_register_int ("genesis", 0, "z80running", &z80running);
state_save_register_UINT32("genesis", 0, "z80_68000_latch", (UINT32 *)&z80_68000_latch, 1);
state_save_register_UINT32("genesis", 0, "z80_latch_bitcount", (UINT32 *)&z80_latch_bitcount, 1);
if (genesis_z80_ram)
state_save_register_UINT8("genesis", 0, "z80_ram", genesis_z80_ram, 0x2000);
}
src/machine/model1_machine.c
+17 -17
View File
@@ -496,7 +496,7 @@ static float ram_get_f(void)
return u2f( m_copro_ram_data[ ram_scan() ] );
}
static void fadd(void)
static void tgp_fadd(void)
{
float a = fifoin_pop_f();
float b = fifoin_pop_f();
@@ -505,7 +505,7 @@ static void fadd(void)
fifoout_push_f(r);
}
static void fsub(void)
static void tgp_fsub(void)
{
float a = fifoin_pop_f();
float b = fifoin_pop_f();
@@ -514,7 +514,7 @@ static void fsub(void)
fifoout_push_f(r);
}
static void fmul(void)
static void tgp_fmul(void)
{
float a = fifoin_pop_f();
float b = fifoin_pop_f();
@@ -523,7 +523,7 @@ static void fmul(void)
fifoout_push_f(r);
}
static void fdiv(void)
static void tgp_fdiv(void)
{
float a = fifoin_pop_f();
float b = fifoin_pop_f();
@@ -1300,7 +1300,7 @@ static void matrix_sdir(void)
m_t71 = f2u( b );
}
static void fsqrt(void)
static void tgp_fsqrt(void)
{
float a = fifoin_pop_f();
LOG(("TGP fsqrt %f (%x)\n", a, m_pushpc));
@@ -2561,10 +2561,10 @@ static void matrix_settrans_vf(void)
static const struct tgp_function ftab_vr[] = {
{ fadd, 2 }, /* 0x00 */ /* 0b5 09b */
{ fsub, 2 }, /* 0ba 0a0 */
{ fmul, 2 }, /* 0bf 0a5 */
{ fdiv, 2 }, /* 0c4 0aa */
{ tgp_fadd, 2 }, /* 0x00 */ /* 0b5 09b */
{ tgp_fsub, 2 }, /* 0ba 0a0 */
{ tgp_fmul, 2 }, /* 0bf 0a5 */
{ tgp_fdiv, 2 }, /* 0c4 0aa */
{ NULL, 0 }, /* 0d2 0b9 */
{ matrix_push, 0 }, /* 0e3 0cc */
{ matrix_pop, 0 }, /* 0f7 0e0 */
@@ -2608,7 +2608,7 @@ static const struct tgp_function ftab_vr[] = {
{ f42, 3 }, /* 329 34b */
{ f43, 6 }, /* 36c 38f */
{ track_read_tri, 1 }, /* 3c2 3e2 */
{ fsqrt, 1 }, /* 3c7 3e9 */
{ tgp_fsqrt, 1 }, /* 3c7 3e9 */
{ vlength, 3 }, /* 3cf 3f2 */
{ NULL, 0 }, /* 3ef 411 */
@@ -2642,9 +2642,9 @@ static const struct tgp_function ftab_vr[] = {
/* 315-5724 (Virtua Fighter): its own versions where its program differs
from 315-5573 */
static const struct tgp_function ftab_vf[] = {
{ fadd, 2 }, /* 0x00 */
{ fsub, 2 },
{ fmul, 2 },
{ tgp_fadd, 2 }, /* 0x00 */
{ tgp_fsub, 2 },
{ tgp_fmul, 2 },
{ fdiv_vf, 2 },
{ nop_tgp, 0 },
{ matrix_push, 0 },
@@ -2758,10 +2758,10 @@ static const struct tgp_function ftab_vf[] = {
/* f49_swa */
static const struct tgp_function ftab_swa[] = {
{ fadd, 2 }, /* 0x00 */
{ fsub, 2 },
{ fmul, 2 },
{ fdiv, 2 },
{ tgp_fadd, 2 }, /* 0x00 */
{ tgp_fsub, 2 },
{ tgp_fmul, 2 },
{ tgp_fdiv, 2 },
{ f04_swa, 2 },
{ matrix_push_swa, 0 },
{ matrix_pop, 0 },
src/machine/model2_machine.c
+23
View File
@@ -526,11 +526,27 @@ READ32_HANDLER( model2_copro_status_r )
static UINT32 fifo_in_save[ FIFO_ALLOC ], fifo_out_save[ FIFO_ALLOC ];
static int fifo_in_count, fifo_out_count;
static INT32 fifo_waits_save[ 4 ];
static void fifo_wait_load( struct m2_fifo *f, int reader_waits, int writer_waits )
{
f->reader_waits = reader_waits ? 1 : 0;
f->writer_waits = writer_waits ? 1 : 0;
if( f->reader_waits )
cpunum_suspend( f->reader, SUSPEND_REASON_SPIN, 1 );
if( f->writer_waits )
cpunum_suspend( f->writer, SUSPEND_REASON_SPIN, 1 );
}
static void copro_presave( void )
{
int i;
fifo_in_count = fifo_in.count;
fifo_out_count = fifo_out.count;
fifo_waits_save[ 0 ] = fifo_in.reader_waits;
fifo_waits_save[ 1 ] = fifo_in.writer_waits;
fifo_waits_save[ 2 ] = fifo_out.reader_waits;
fifo_waits_save[ 3 ] = fifo_out.writer_waits;
for( i = 0; i < fifo_in.count; i++ )
fifo_in_save[ i ] = fifo_in.data[ ( fifo_in.head + i ) % FIFO_ALLOC ];
for( i = 0; i < fifo_out.count; i++ )
@@ -548,6 +564,12 @@ static void copro_postload( void )
fifo_out.data[ i ] = fifo_out_save[ i ];
fifo_in.count = fifo_in_count;
fifo_out.count = fifo_out_count;
if( model2_copro_type == MODEL2_COPRO_SHARC )
sharc_flags_update();
/* the CPUs waiting on a FIFO at the save wait again, so that the
access that ends the wait resumes them */
fifo_wait_load( &fifo_in, fifo_waits_save[ 0 ], fifo_waits_save[ 1 ] );
fifo_wait_load( &fifo_out, fifo_waits_save[ 2 ], fifo_waits_save[ 3 ] );
if( tgp_booted )
cpunum_resume( CPU_TGP, SUSPEND_REASON_HALT );
else
@@ -585,6 +607,7 @@ void model2_copro_init( void )
state_save_register_UINT32( "model2tgp", 0, "fifo_out", fifo_out_save, FIFO_ALLOC );
state_save_register_int( "model2tgp", 0, "fifo_in_count", &fifo_in_count );
state_save_register_int( "model2tgp", 0, "fifo_out_count", &fifo_out_count );
state_save_register_INT32( "model2tgp", 0, "fifo_waits", fifo_waits_save, 4 );
state_save_register_func_presave( copro_presave );
state_save_register_func_postload( copro_postload );
}
src/machine/mspacman.c
+23 -5
View File
@@ -1,6 +1,7 @@
#include "driver.h"
#include "vidhrdw/generic.h"
#include "state.h"
/*
@@ -180,11 +181,26 @@ void mspacman_decode(void)
}
MACHINE_INIT( mspacman )
/* the board boots from the original Pac-Man ROMs and switches to the
decoded Ms. Pac-Man ROMs on a write to 0x5006; the switch is part of the
save state, so that a state loaded in a new instance runs the same code */
static UINT8 mspacman_rom_active;
static void mspacman_set_bank(void)
{
unsigned char *RAM = memory_region(REGION_CPU1);
cpu_setbank (1, &RAM[mspacman_rom_active ? 0x10000 : 0x00000]);
}
MACHINE_INIT( mspacman )
{
mspacman_decode();
cpu_setbank (1, &RAM[0x00000]);
mspacman_rom_active = 0;
mspacman_set_bank();
state_save_register_UINT8("mspacman", 0, "rom_active", &mspacman_rom_active, 1);
state_save_register_func_postload(mspacman_set_bank);
machine_init_pacman();
}
@@ -192,7 +208,9 @@ MACHINE_INIT( mspacman )
WRITE_HANDLER( mspacman_activate_rom )
{
unsigned char *RAM = memory_region(REGION_CPU1);
if(data==1) cpu_setbank (1, &RAM[0x10000]);
if (data == 1)
{
mspacman_rom_active = 1;
mspacman_set_bank();
}
}
src/machine/scramble_machine.c
+10
View File
@@ -936,6 +936,16 @@ DRIVER_INIT( ckongs )
ppi8255_set_portCread(0, ckongs_input_port_2_r);
}
/* Knock Out!! bootlegs: an extra ROM, as Mariner */
DRIVER_INIT( knockoutb )
{
init_scramble_ppi();
/* extra ROM */
install_mem_read_handler (0, 0x5800, 0x67ff, MRA_ROM);
install_mem_write_handler(0, 0x5800, 0x67ff, MWA_ROM);
}
DRIVER_INIT( mariner )
{
init_scramble_ppi();
src/machine/scudsp.c
+65 -3
View File
@@ -1,5 +1,7 @@
#include "driver.h"
#include "state.h"
#include "machine/scudsp.h"
#include "cpu/sh2/sh2.h"
/*SCU DSP functions */
/*V0.03*/
@@ -75,10 +77,13 @@ extern data32_t* stv_scu;
static UINT32 opcode;
static UINT8 update_mul = 0;
#define DEBUG_DSP
/* writes dsp.log in the current directory, for debugging only */
/*#define DEBUG_DSP*/
#ifdef DEBUG_DSP
static char dasm_buffer[100];
static FILE *log_file = NULL;
#endif
void dsp_dasm_opcode( UINT32 op, char *buffer );
@@ -266,12 +271,61 @@ static UINT32 dsp_get_mem_source_dma( UINT32 memcode, UINT32 counter )
return 0;
}
/* the save state: the 48-bit MUL and ALU go as two 32-bit halves */
static UINT32 dsp_ss_mul[2], dsp_ss_alu[2];
static void scudsp_presave(void)
{
dsp_ss_mul[0] = (UINT32)(dsp_reg.mul >> 32);
dsp_ss_mul[1] = (UINT32)dsp_reg.mul;
dsp_ss_alu[0] = (UINT32)(dsp_reg.alu >> 32);
dsp_ss_alu[1] = (UINT32)dsp_reg.alu;
}
static void scudsp_postload(void)
{
dsp_reg.mul = ((UINT64)dsp_ss_mul[0] << 32) | dsp_ss_mul[1];
dsp_reg.alu = ((UINT64)dsp_ss_alu[0] << 32) | dsp_ss_alu[1];
}
void scudsp_state_save_register(void)
{
state_save_register_UINT8 ("scudsp", 0, "pc", &dsp_reg.pc, 1);
state_save_register_UINT8 ("scudsp", 0, "delay", &dsp_reg.delay, 1);
state_save_register_UINT8 ("scudsp", 0, "top", &dsp_reg.top, 1);
state_save_register_UINT16("scudsp", 0, "lop", &dsp_reg.lop, 1);
state_save_register_UINT8 ("scudsp", 0, "ct0", &dsp_reg.ct0, 1);
state_save_register_UINT8 ("scudsp", 0, "ct1", &dsp_reg.ct1, 1);
state_save_register_UINT8 ("scudsp", 0, "ct2", &dsp_reg.ct2, 1);
state_save_register_UINT8 ("scudsp", 0, "ct3", &dsp_reg.ct3, 1);
state_save_register_UINT32("scudsp", 0, "md0", dsp_reg.md0, 0x40);
state_save_register_UINT32("scudsp", 0, "md1", dsp_reg.md1, 0x40);
state_save_register_UINT32("scudsp", 0, "md2", dsp_reg.md2, 0x40);
state_save_register_UINT32("scudsp", 0, "md3", dsp_reg.md3, 0x40);
state_save_register_UINT8 ("scudsp", 0, "ra", &dsp_reg.ra, 1);
state_save_register_UINT32("scudsp", 0, "rx", &dsp_reg.rx, 1);
state_save_register_UINT32("scudsp", 0, "mul", dsp_ss_mul, 2);
state_save_register_UINT32("scudsp", 0, "ry", &dsp_reg.ry, 1);
state_save_register_UINT32("scudsp", 0, "alu", dsp_ss_alu, 2);
state_save_register_UINT16("scudsp", 0, "ph", &dsp_reg.ph, 1);
state_save_register_UINT32("scudsp", 0, "pl", &dsp_reg.pl, 1);
state_save_register_UINT16("scudsp", 0, "ach", &dsp_reg.ach, 1);
state_save_register_UINT32("scudsp", 0, "acl", &dsp_reg.acl, 1);
state_save_register_UINT32("scudsp", 0, "ra0", &dsp_reg.ra0, 1);
state_save_register_UINT32("scudsp", 0, "wa0", &dsp_reg.wa0, 1);
state_save_register_UINT32("scudsp", 0, "internal_prg", dsp_reg.internal_prg, 0x100);
state_save_register_UINT32("scudsp", 0, "opcode", &opcode, 1);
state_save_register_UINT8 ("scudsp", 0, "update_mul", &update_mul, 1);
state_save_register_func_presave(scudsp_presave);
state_save_register_func_postload(scudsp_postload);
}
void dsp_prg_ctrl(UINT32 data)
{
if(LEF) dsp_reg.pc = (data & 0xff);
if(EXF) dsp_execute_program();
if(EF && (!(stv_scu[40] & 0x0020)))
cpu_set_irq_line_and_vector(0, 0xa, HOLD_LINE , 0x45);
if(EF)
stv_scu_raise_irq(5); /* DSP end */
}
void dsp_prg_data(UINT32 data)
@@ -630,6 +684,8 @@ static void dsp_dma( void )
for ( counter = 0; counter < transfer_cnt; counter++ )
{
cpu_writemem32bedw_dword( dest, cpu_readmem32bew_word( dsp_get_mem_source_dma( dsp_mem, counter ) ) );
if ( sh2_jit_code_present )
sh2_jit_ram_written( dest, 4 );
dest += add;
}
@@ -698,6 +754,7 @@ static void dsp_loop( void )
}
}
#ifdef DEBUG_DSP
static void dsp_dump_mem( FILE *f )
{
UINT16 i;
@@ -724,12 +781,15 @@ static void dsp_dump_mem( FILE *f )
}
fprintf( f, "}\n" );
}
#endif
void dsp_execute_program()
{
UINT32 cycles_run = 0;
UINT8 cont = 1;
#ifdef DEBUG_DSP
UINT16 i;
#endif
#ifdef DEBUG_DSP
if ( log_file == NULL )
@@ -758,7 +818,9 @@ void dsp_execute_program()
dsp_reg.pc++;
}
#ifdef DEBUG_DSP
dsp_dasm_opcode( opcode, dasm_buffer );
#endif
switch( (opcode & 0xc0000000) >> 30 )
{
src/machine/scudsp.h
+4
View File
@@ -6,3 +6,7 @@ extern void dsp_ram_addr_ctrl(UINT32 data);
extern void dsp_ram_addr_w(UINT32 data);
extern UINT32 dsp_ram_addr_r(void);
extern void dsp_execute_program(void);
extern void scudsp_state_save_register(void);
/* raise an SCU interrupt source (bit of the status register), drivers/stv.c */
extern void stv_scu_raise_irq(int bit);
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